BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

Digital Learning
Part A: Content Design.

Course Title IC FABRICATION TECHNOLOGY

Course No. MEL G611

Credit Units 5

Credit Model Theory + Laboratory Component

Course Author SINDHU S

Course Description

Material properties; Crystal growth and doping; diffusion; oxidation; epitaxy; Ion implantation;
Deposition of films using CVD, LPCVD and sputtering techniques; Wet and dry etching and
cleaning; Lithographic process; Device and circuit fabrication

Course Objectives:
The objective of this course is to teach students with the issues involved in VLSI fabrication technologies for
micron and sub-micron technologies. More specifically, there will be increased focus on techniques
employed in the industry for such important phases of VLSI fabrication as doping, diffusion, oxidation,
epitaxy, ion implementation, film depositing techniques, etching and photo-lithographic processes. As the
device and circuit fabrication in sub- and deep sub-micron technologies tends to be different from that of
conventional technologies due to technology scaling, emphasis will be given on new device structures that
facilitate easy fabrication with better yield and reliability.
No. Course Objective
CO1 Understanding the manufacturing methods involved for integrated circuit fabrication
CO2 Underlying scientific principles in the context of technologies used in VLSI chip fabrication
Processes involved in silicon integrated circuit fabrication for sub and deep sub-micron
CO3
technologies.

Text Book(s):
Sze S. M., “VLSI Technology,” McGraw Hill Education
T1
C. Kittel “Introduction to Solid State Physics

Reference Book(s) and Other Resources:

R1 “A Basic Introduction to Clean Rooms” By Roger McFadden, Senior Scientist, Staples Inc.
R2 Wolf S. and Tauber R. N., “Silicon Processing for the VLSI Era,” Lattice Press
Plummer J. D., Deal M. D., and Griffin P. B., “Silicon VLSI Technology,” Prentice Hall- Electronics
R3
and VLSI series, 2000.
Learning Outcomes:
No. Learning Outcomes
LO1 Strong understanding of fabrication of micro chips
LO2 Different integrated circuits fabrication techniques
LO3 Link with day to day work
PART B – Course Handout
Academic Term First Semester 2023– 2024
Course Title IC Fabrication Technology
Course No. MEL G611
Lead Instructor SINDHU S

Contact List of Topic Topic # References

Hour (Chap/Sec)(Textbook)
1,2 History and Development Crystal structure and basics. Crystal T1 , R1
Concepts of Crystal structure, Miller indices, orientation, Structure
defects. Introduction to clean room, Clean room basics, and basics ,
Clean room attire, Standards of cleanrooms Clean room
3,4 Crystallography , crystal structure, miller indices, Crystal T1-Ch 1
orientation and crystal structure of Silicon, Crystal Growth and
growth techniques wafer
Czochralski and FZ growth methods, preparation
Wafer preparation and specifications, SOI wafer
manufacturing
5 Photolithography, Light sources, Wafer exposure Lithography T1-3.5
systems, Photoresists, Baking and development, Mask processing
making, Measurement of mask features and defects,
resist patterns and etched features
6 Different types of etching, dry etching, wet etching, Etching T1-Ch5
plasma etching, etching of materials using VLSI,
modelling of etching
7 Vacuum system, vacuum pump, gauges, spectroscopic
techniques overview,
8-9 Thin film process, Vacuum System, Chemical and Thin film T1-Ch 2
physical vapour deposition,Sputtering and Thermal deposition
evaporation epitaxial growth, manufacturing methods process and
and systems, Epitaxial process of Silicon wafers, techniques
Molecular Beam epitaxy, Thin film characterization and epitaxy
techniques, Thin film
characterizat
ion
10 Types of oxidation, Thermal Oxidation, D-G model, Oxidation T1-Ch 3
 dopant distribution in oxide layer, growth of oxide layer.
Wet and Dry oxidation, growth kinetics and models,
defects, measurement methods and characterization.
11 Models for diffused layers, Characterization methods, Diffusion T1-Ch7
Segregation, Interfacial dopant pileup, oxidation
enhanced diffusion, dopant-defect interaction.
12 Basic concepts, High energy and ultralow energy Ion T1-Ch7
implantation, shallow junction formation . Electronic Implantation
stopping, Damage production and annealing, RTA
Process & dopant activation. Channelling
13 Aluminium metallization, Copper metallization, contacts, Metallization T1-Ch8
interconnects, multilevel interconnects
14 Chemical Mechanical Planarization process, Planarization T1-Ch8
electrochemical mechanical planarization
15 Yield and reliability, bath tub curve Yield T1-Ch12
16 Assembly and packing Assembly T1-Ch13
and packing
16 Lab demonstration session

Detailed Plan for Lab Work / Design Work

Lab Lab Objective Lab Sheet Content Reference
No. Access URL
1 Semiconductor Process and Device Simulator Class room Free process Simulator
General-purpose Semiconductor Simulator session only (http://www.siborg.ca/microtec.
html)

Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No. Name Type Duration Weight Day, Date, Session, Time
EC-1 Quiz / Assignment / Online - 20%+10 To be announced
Seminar/lab %
EC-2 Mid-semester Test Closed Book 2 hours 30% Sunday, 24/09/2023 (AN)
EC-3 Comprehensive Exam Open Book 2½ 40%
Sunday, 26/11/2023 (AN)
hours

Syllabus for Mid-Semester Test (closed Book): Topics covered till Mid-Semester test
Syllabus for Comprehensive Exam (Open Book): All topics
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest
announcements and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the ELearn
portal.
Evaluation Guidelines:
EC-1 consists of Quiz. Students will attempt them through the course pages on the Elearn portal.
Announcements will be made on the portal, in a timely manner.
EL-1 is the experiential leaning component on the project assigned to you. You will have presentation/
submission at the mid-term and towards the end of the course. Dates will be announced on the portal well
in advance.
For Closed Book tests: No books or reference material of any kind will be permitted.
For Open Book exams: Use of books and any printed / written reference material (filed or bound) is
permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted in all exams.
Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.
If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student should
follow the procedure to apply for the Make-Up Test/Exam which will be made available on the Elearn portal.
The Make-Up Test/Exam will be conducted only at selected exam centres on the dates to be announced
later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study schedule as
given in the course handout, attend the online lectures, and take all the prescribed evaluation components
such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the evaluation scheme
provided in the handout.