تطبيقات رقميه الماده المشتركه

Ministry of Higher Education and Scientific Research
Al-Furat Al-Awsat Technical University

Engineering Technical College - Najaf
Communications Techniques Eng. Dpt.
Digital applications
2nd stage
Lecture # 11
Digital applications Lecture # 11
➢ Explain the Operation of a Johnson Counter.

➢ Draw the Timing Diagram for Johnson Counter.
➢ Explain the Operation of a Ring Counter.
➢ Draw the Timing Diagram for Ring Counter.
The Johnson Counter
➢ A Johnson counter will produce a modulus of 2n, where n is the number
of flip-flop in the counter.
➢ The implementation of the Four-bit Johnson counter is shown in Figure

below.
➢ The complement of the output of the last flip-flop is connected back to

the D input of the first flip-flop. The Q output of each stage is connected
to the D input of the next stage.
• Prepared by Huda Hussein Abed
Four-bit Johnson sequence Mod-8

Timing sequence for a 4-bit Johnson counter

D0=Q3
D1=Q0
D2=Q1
D3=Q2
5-bit Johnson counters.
Five-bit Johnson sequence.
Mod-10

The Ring Counter

➢ A Ring counter will produce a modulus of n , where n is the number of flip-
flop in the counter.
➢ A logic diagram for Mod- 6 ring counter is shown in Figure below. Initially, a
1 is preset into the first flip-flop, and the rest of the flip-flops are cleared.
Notice that the interstage connections are the same as those for a Johnson
counter, except that Q rather than Q is fed back from the last stage.
A 6-bit ring counter

6-bit ring counter sequence.
➢ A logic diagram for a 10-bit ring counter is shown in Figure below. Initially, a
1 is preset into the first flip-flop, and the rest of the flip-flops are cleared.
A 10-bit ring counter

Ten-bit ring counter sequence.
Note:
Modified sequences can be achieved by having more than a single 1 in the counter.

Example: If a 10-bit ring counter has the initial state as shown in figure
below, determine the counter sequence.
Note: Initially, a 1 is preset into the first and third flip-flops, and the rest of the flip-flops are cleared.
Solution:

Example: Q0Q1Q2Q3Q4Q5Q6Q7Q8Q9
If a 10-bit ring counter has the initial state 1010000000, determine the
waveform for each of the Q outputs. Note: D flip-flop

1. Thomas L. Floyd, “Digital Fundamentals” Pearson Education ,

11th edition , ISBN 10: 1-292-07598-8, 2015.
Prepared by Huda Hussein Abed

Digital application
2nd stage
Lecture # 12
➢ Describe the operation of four types of shift registers.

▪ Explain how data bits are entered into a shift register.
▪ Explain how data bits are taken out of a shift register.
Shift Register
➢ A shift register is a type of sequential logic circuit.
➢ A shift register consists of an arrangement of flip‐flops, each one of

which shares a common clock.
➢ The two basic functions of shift register : data storage and data
movement.
➢ The storage capacity of a register is the total number of bits (1s and 0s)
of digital data it can retain. An n-bit register consists of a group of n flip-
flops capable of storing n bits of binary information.
➢ The shift capability of a register permits the movement of data from

stage to stage within the register or out of the register upon application
of clock pulses.
➢ There are four types of shift registers based on data input and output
(inputs/outputs), as listed below.
1. Serial In /Serial Out Shift Registers (SISO).
2. Serial In/Parallel Out Shift Registers (SIPO).
3. Parallel In/Serial Out Shift Registers (PISO).
4. Parallel In/Parallel Out Shift Registers(PIPO).

Serial In/Serial Out Shift Registers
➢ The serial in/serial out shift register accepts data serially.
➢ It has one serial input, and one bit is loaded from serial input into the
register by every clock pulse.
➢ It produces the stored information on its output also in serial form.
4-bit Shift Register implemented with D flip-flops Logic block symbol
➢ This register can store up to four bits of data.

❖ Note: The design shown in the figure above is regarded as a right shift SISO shift register

➢ Table below shows the entry of the four bits 1010 into the register,
beginning with the least significant bit into the register. The register is
initially clear.
Data input
Note: For serial data, one bit at a time is transferred.
➢ After CLK4 in the data-entry operation, the bit, 0, appears on the Q3 output.

➢ If you want to get the data out of the register, the bits must be shifted out
serially to the Q3 output, as the Table below illustrates.
Clarification
1 0 1 0
0 1 0 1
0
0 0 1 0 1 0
0 0 0 1 0 1 0
0 0 0 0 1 0 1 0

Example: The sequence 1011 is applied to the input of a 4-bit serial shift
register (beginning with the least significant bit) that is initially cleared .What
is the state of the shift register after three clock pulses ?
Solution: 1011
CLK Q0 Q1 Q2 Q3
Initial 0 0 0 0
1st CLK 1 0 0 0
2nd CLK 1 1 0 0
3rd CLK 0 1 1 0

➢ A shift register made up of JK or SR flip-flops has non-inverting output Q

of one flip-flop connected to J or S input of next flip-flop and inverting
output Q' connected to K or R input respectively.
➢ For the first flip-flop, between J and K ( or S and R) an inverter is

connected and J ( or S) input is treated as serial data in.
4-bit SISO Shift Register Using J-K Flip-Flop

Serial In / Parallel Out Shift Registers
❖ Data bits are entered serially into a serial in / parallel out shift register.
❖ Once the data are stored, each bit appears on its respective output line,
and all bits are available simultaneously.
❖ The figure below shows a 4-bit serial in / parallel out shift register and
its logic block symbol.
A Serial in / Parallel out Shift Register Logic Block Symbol

➢ Table below shows the entry of the four bits 1011 into the shift register,
beginning with the least significant bit. The register is initially clear.
CLK Q0 Q1 Q2 Q3
Initial 0 0 0 0
1st CLK 1 0 0 0
2nd CLK 1 1 0 0
3rd CLK 0 1 1 0
4th CLK 1 0 1 1
➢ After four clock pulses, the data becomes available simultaneously on the
four outputs Q0 to Q3.
➢ In a serial output shift register, clock pulses are required to read the data, but
in parallel out shift register, clock pulses are not required to read the data.

Example: The bit sequence 1101 is serially entered (least-significant bit
first) into a 4-bit parallel out shift register that is initially clear. What are the
Q outputs after two clock pulses?
Solution:
CLK Q0 Q1 Q2 Q3
Initial 0 0 0 0
1st CLK 1 0 0 0
2nd CLK 0 1 0 0
The Q outputs 0100 after two clock pulses

Example 2:
Show the states of the 4-bit shift register (SRG 4) for the data input and
clock waveforms in the figure below. The register initially contains all 1s.

Solution:
Q0Q1Q2Q3
The register contains 0 1 1 0 after four clock pulses.

Parallel In/Serial Out Shift Registers
❖ The bits are entered simultaneously into their respective stages on
parallel lines rather than on a bit-by-bit basis on one line as with serial
data inputs.
❖ The serial output is the same as in serial in / serial out shift registers,
once the data are completely stored in the register.
A 4-bit parallel in/serial out shift register Logic Block Symbol


Example : Show the data-output waveform for a 4-bit register with the
parallel input data and the clock and SHIFT/LOAD waveforms given in the
figure below.

1 0 1 0
Solution:
On clock pulse 1, the parallel data (D0D1D2D3 = 1010) are loaded into the register, making Q3
a 0. On clock pulse 2 the 1 from Q2 is shifted onto Q3; on clock pulse 3 the 0 is shifted onto
Q3; on clock pulse 4 the last data bit (1) is shifted onto Q3.

Parallel In / Parallel Out Shift Registers
❖ The parallel in/parallel out register is shown in Figure below. There are
four inputs, D0, D1, D2, and D3, and four outputs, Q0, Q1, Q2, and Q3. When
the input bits are applied on the data inputs, they simultaneously appear on
the parallel outputs on the positive going edge of the clock pulse.

Example:
In figure below, D0 = 1, D1 = 0, D2 = 0, and D3 = 1. After three clock
pulses, what are the data outputs?
Solution:
After three clock pulses, the data outputs are 1001.

➢ G. K. Kharate, “Digital Electronics” Oxford university press , 7th

edition , ISBN 13: 978-0-19-806183-0, 2013.
➢ Thomas L. Floyd, “Digital Fundamentals” Pearson Education ,
11th edition , ISBN 10: 1-292-07598-8, 2015.
➢ Ata Elahi, “Computer Systems”, Springer, ISBN 978-3-319-
66774-4, 2018.
➢ Shuqin Lou, Chunling Yang, “Digital Electronic Circuits ”
Science Press, 4th edition , ISBN 978-3-11-061466-4, 2019.

Digital application
2nd stage
Lecture # 13
➢ Explain the Basic Operation of a Multiplexer.

➢ Implement Two-input, and Four-input Multiplexers Using Logic Gates.
➢ Design Higher order Multiplexer Using lower order Multiplexers.
Multiplexer (MUX)
➢ A multiplexer (Data Selectors) is a combinational logic circuit that accepts
several data inputs and selects one of them at any given time to pass on to
the output. The routing of the desired digital data input to the output is
controlled by selection inputs.
➢ If there are m selection inputs, then the number of maximum possible input
lines (N) is 2m and such multiplexer is referred to as a N-to-1 multiplexer.
Note:
N = 2m
m= log2 N
m : number of select inputs.
N: number of data inputs lines
Selection inputs
The functional diagram of a general digital multiplexer.

Implement 2 to 1 Mux Using Logic Gates
➢ A two-to-one (21-to-1) multiplexer (MUX) is a combinational logic circuit with
two input lines, D0 and D1 ; one output line, Y and one selection line, S0.
No. of input lines = 2

No. of selection lines (S) = 1
➢ It can be represented by the symbol given in the figure below .
Data select Output

D0 Inputs
D1 S Y
0 𝐷0
1 𝐷1
2-to-1 multiplexer Logic Symbols Function table
➢ The logic expression of the 2:1 multiplexer is given by:

𝑌 = 𝑆ഥ . 𝐷0 +𝑆. 𝐷1

𝑌 = 𝐷0 𝑆ഥ + 𝐷1 𝑆
2
Logic Diagram for a 2-Input Multiplexer
➢ The logic level applied to the S input determines which AND gate is enabled so
that its data input passes through the OR gate to output Y.
➢ With S = 0, this expression becomes

𝑌 = 𝐷0 . 1 + 𝐷1 . 0
𝑌 = 𝐷0
➢ With S = 1, this expression becomes
𝑌 = 𝐷0 . 0 + 𝐷1 . 1
𝑌 = 𝐷1
Implement 4 to 1 Mux Using Logic Gates
➢ A 4-to-1 multiplexer has four data input lines, a single output line, and two
selection lines. The selection lines select data from one of four data input lines then
the selected data are transmitted to the output line. No. of inputs = 4
No. of selection line (S) = log2 4
= log2 22
= 2 log2 2
= 2

D0
D1
D2
D3
S1 S0
Function table 4-to-1 Multiplexer Logic Symbols
➢ The logic expression of the 4:1 multiplexer is given by:

D0 1
D1 0
D2 1
D3 0
0
1
Logic Diagram for a 4-Input Multiplexer
❖ In the Figure above , D0 = 1, D1 = 0, D2 = 1, D3 = 0, S0 = 1, and S1 = 0. What is the output?
The output is 0.

➢ Multiplexers offered by integrated circuit manufacturers most often have
an active low enable input, as shown below.
2-to-1 multiplexer with an active-low enable input
4-to-1 multiplexer with an active-low enable input

Example: Implement 8-to-1 Mux with active-low enable input using logic gates
Solution:
Eight-to-one multiplexer (MUX) is a combinational circuit with eight input lines, I0,
I1, I2, I3, I4, I5, I6 and I7, one output line, O and three selection lines, S2, S1 and S0. On
receiving active low enable input, multiplexer is able to perform its intended function.
8-to-1 line multiplexer selects binary information present on any one of I0, I1, I2, I3, I4,
I5, I6 or I7 input line, depending upon the logic status of three selection inputs, S2, S1
and S0, and sends it to the output line, O.
Function table

The Boolean expression for the output is given below.
Logic Diagram for 8-to-1 line MUX

with active low enable input

Design Higher order Multiplexer Using Lower Order Multiplexers
➢ Higher order multiplexers can be constructed by using lower order
multiplexers. This method of expansion of multiplexers is also known
as multiplexer tree
Example: Construct 4-to-1 lines multiplexer using 2-to-1 line multiplexer.

Solution:
Let N = 4 (Input lines of MUX to be constructed) and M = 2 (Input lines of available
MUX)
Number of MUX required in Level I: N1= (4/2)
=2
Number of MUX required in Level II: N2 = (2/2)
=1
Three (2 + 1) 2-to-1 lines MUX are required and arranged in two levels. Least
significant selection line S0 is connected to two MUX of level I. Higher significant
selection line S1 is given to MUX of level II. Outputs of MUX of level I are connected
to input lines of MUX of Level II.

Block diagram of 4:1 MUX

using 2:1 MUX
Example: Construct 8-to-1 line multiplexer using 2-to-1 line multiplexer.

Solution:
MUX)
=4
Number of MUX required in Level II: N2 = (4/2)
=2
Number of MUX required in Level III: N3 = (2/2)
=1
❖ 7(4 + 2 + 1) 2-to-1 line MUX are required and arranged in three levels. Least
significant selection line S0 is connected to four MUX of level I. Higher
significant selection line S1 is given to MUX of level II. Most significant
selection line S2 is given to MUX of level III.

using 2:1 MUX

Example: Construct 16-to-1 line multiplexer using 4-to-1 line multiplexer.
Solution:
MUX)


using 4:1 MUX

Example: Construct 8-to-1 line multiplexer using 4-to-1 line multiplexer
with enable lines.
Solution: Let N = 8 (Input lines of MUX to be constructed) and M = 4 (Input lines
of available MUX)
=2

Example: Construct 8-to-1 line multiplexer using 4:1 and 2:1 multiplexers.
Solution: Let N = 8 (Input lines of MUX to be constructed) and M = 4 (Input lines of

available MUX)
Number of MUX required in Level I:
N1= (8/4)
=2
2<4
Number of 2:1 MUX required:

2/2=1

Summary
Implement Two-input, and Four-input Multiplexers Using Logic Gates
Design Higher order Multiplexer Using Lower Order Multiplexers

➢ G. K. Kharate, “Digital Electronics” Oxford university press , 7th edition ,

ISBN 13: 978-0-19-806183-0, 2013.
➢ D. P. Kothari, and J. S. Dhillon “Digital Circuits and Design” Pearson
Education , ISBN 978-93-325-4353-9, 2015.
➢ T. Ndjountche “Digital Electronics 1”, John Wiley & Sons, 1st edition,
ISBN 978-1-84821-984-7, 2016.
➢ Neal S. widmer and Gregory L. Moss “Digital Systems Principles and
Applications” Pearson Education , 12th edition , ISBN 10: 0-13-422013-7,
2017.
➢ Ata Elahi, “Computer Systems”, Springer, ISBN 978-3-319-66774-4, 2018.

Digital applications
2nd stage
Lecture # 14
➢ Implementation of Logic Functions Using Multiplexers

➢ Explain the Basic Operation of a Demultiplexer, then Implement 1:2,
1:4, and 1:8 Demultiplexers Using Logic Gates.
➢ Design Higher order Demultiplexer Using lower order Demultiplexers.
Implementation of Logic Functions Using Multiplexers
Example: Implement the logic function specified in the truth table below using
8:1 multiplexer.
Solution:
❖ The truth table is made of three variables.
❖ The A, B, and C variables are connected to the selection lines of 8:1 MUX, and the inputs
of the MUX correspond to the output of truth table.
❖ Notice from the truth table that F is a 1 for the following input variable combinations:011,
100, 110, and 111. For all other combinations, F is 0.
❖ For this function to be implemented with the 8:1 MUX, the data input selected by each of
the above-mentioned combinations must be connected to a HIGH. All the other data inputs
must be connected to a LOW .

F(A,B,C)= σ 𝑚(3, 4,6,7)

F
Implementation of the Logic Function Using 8:1 Multiplexer
Example: Implement the logic function specified in the truth table below using
8:1 multiplexer.
Solution:
❖ The truth table is made of four variables.
❖ The A, B, and C variables are connected to the selection lines
of 8:1 MUX.
❖ It becomes possible to regroup the rows of the truth table in
pairs, with each pair being characterized by the same
combination of selection inputs.
❖ Connect the data inputs of the multiplexer to either the logic
level 1 or 0, or to the remaining variable or its complement.

❖ The selection inputs are A B C . In the first row of the

table, A B C = 000 and Y = D. In the second row,
where A B C again is 000, Y= D. Thus, D is connected
to the 0 input (I0).
❖ In the third row of the table, A B C = 001 and Y = 1.
Also, in the fourth row, when A B C again is 001,
Y = 1. Thus, logic 1 is connected to the 1 input (I1).
❖ This analysis is continued until each input is properly
connected according to the specified rules. The
implementation is shown in the Figure below.
Implementation of the Logic Function

Using 8:1 Multiplexer

Example: Implement the logic function, F(A,B,C) =σ 𝑚(0, 1,3,4) using 4:1 multiplexer.
Solution:
F(A,B,C) =σ 𝑚(0, 1,3,4)
❖ The truth table is made of three variables.

❖ The A, and B variables are connected to the selection lines of 4:1 MUX.
❖ It becomes possible to regroup the rows of the truth table in pairs, with each pair
being characterized by the same combination of selection inputs.
❖ Connect the data inputs of the multiplexer to either the logic level 1 or 0, or to the
remaining variable or its complement according to the analysis based on comparison
between the output (Y) and the remaining variable (C).

❖ The selection inputs are A B . In the first row of the table,

A B = 00 and Y = 1. In the second row, where A B again is 00,
Y= 1. Thus, 1 is connected to the 0 input (I0).
❖ In the third row of the table, A B = 01 and Y = C. Also, in the
fourth row, when A B again is 01, Y = C. Thus, C is connected
to the 1 input (I1).
❖ This analysis is continued until each input is properly
connected according to the specified rules. The implementation
is shown in the Figure below.
Implementation of the Logic Function

Using 4:1 Multiplexer

Demultiplexer (DEMUX)
➢ The demultiplexer (Data Distributor) is a combinational logic circuit having a
single input and many outputs. It performs the reverse operation of a multiplexer.
It accepts a single input and sends it to one of the output lines, according to the
selection code.
➢ If there are m selection lines, then the number of maximum possible output lines
(N) is 2m and such demultiplexer is referred to as a 1-to-N demultiplexer.
N = 2m
Data input is transmitted to

m= log2 N only one of the outputs as
determined by selection code
m : number of selection lines.

N: number of outputs lines
Selection lines
The functional diagram of a general digital demultiplexer.

Implement 1-to-2 Demultiplexer (active low enable input) Using Logic Gates
➢ A one-to-two (1-to-21) line demultiplexer (DeMUX) is a combinational circuit with
one input line, I two output lines, O0 and O1 and one selection line, S0. It places
binary information available on input line, I on either O0 or O1 output line. The
output line is selected based on the logic status of the selection input, S0.
No. of output lines = 2
No. of selection lines (S) = 1
➢ It can be represented by the symbol given in the figure below.

Function Table
E S0 O0 O1
1 X 0 0
0 0 I 0
0 1 0 I
Block diagram of 1-to-2 line DeMUX

with active-low enable input
➢ Boolean expressions for outputs are given below.

Logic Diagram for 1-to-2 lines DeMUX

with active low enable input
➢ On receiving active low enable input, demultiplexer is able to perform its
intended function.
➢ With S0 = 0, the input data are transferred to 𝑂0, the expression becomes
𝑂0 = 𝑰
➢ With S0 = 1, the input data are transferred to 𝑂1, the expression becomes
𝑂1 = 𝑰

Implement 1-to-4 Demultiplexer (active low enable input) Using Logic Gates
➢ A 1-to-4 line demultiplexer (DeMUX) is a combinational circuit with one input
line, I four output lines, O0, O1, O2, and O3 and two selection lines, S1 and S0. It
places binary information available on input line, I, on any one O0, O1, O2 or O3
output line. The output line is selected based on the logic status of the selection
inputs, S1 and S0 .
No. of output lines = 4
No. of selection line (S) = log2 4
= 2
➢ On receiving active low enable input, demultiplexer is able to perform its intended
function.
Block diagram of 1-to-2 line DeMUX

with active-low enable input

Function Table
E S1 S0 O0 O1 O2 O3
1 X X 0 0 0 0
0 0 0 I 0 0 0
0 0 1 0 I 0 0
0 1 0 0 0 I 0
0 1 1 0 0 0 I
❖ Boolean expressions for outputs are given below.
I
I
I
Logic Diagram for 1-to-4 line DeMUX with

active low enable input

Implement 1-to-8 Demultiplexer (active-low enable input) Using Logic Gates
Solution:
1-to-8-line demultiplexer (DeMUX) is a combinational circuit with one input line, I, eight
output lines, O0, O1, O2, O3, O4, O5, O6 and O7 and three selection lines, S2, S1 and S0. On
receiving active low enable input, demultiplexer is able to perform its intended function. A
1-to-8-line demultiplexer places binary information available on input line, I, on any one of
O0 to O7 output lines. The output line is selected based on the logic status of the selection
inputs, S2, S1 and S0.
Function Table

The logic expressions are given below:
Logic Diagram for 1-to-8 DeMUX with Active

Low Enable Input

Design Higher order Demultiplexer Using Lower Order Demultiplexers
Example: Construct 1-to-8 line demultiplexer using 1-to-2 line demultiplexer.
Solution:
Let N = 8 (Output lines of DeMUX to be constructed) and M = 2 (Output lines
of available DeMUX).
Number of DeMUX required in Level I: N1= (8/2)

=4
Number of DeMUX required in Level II: N2 = (4/2)
=2
Number of DeMUX required in Level III: N3 = (2/2)
=1
Seven (4 + 2 + 1) 1-to-2 line DeMUX are required and arranged in three levels.

Least significant selection line S0 is connected to DeMUX of level I. Selection line S1 is

given to DeMUX of level II. Most significant selection line S2 is connected to DeMUX of
level III. Outputs of DeMUX of level III are connected to input lines of DeMUX of level II.
Outputs of DeMUX of level II are connected to input lines of DeMUX of level I.
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0
0 0 1 0 I 0 0 0 0 0 0
0 1 0 0 0 I 0 0 0 0 0
0 1 1 0 0 0 I 0 0 0 0
1 0 0 0 0 0 0 I 0 0 0
1 0 1 0 0 0 0 0 I 0 0
1 1 0 0 0 0 0 0 0 I 0
1 1 1 0 0 0 0 0 0 0 I
Block diagram of 1-to-8 line DeMUX using 1-to-2 line DeMUX

Example: Construct 1-to-8 line Demultiplexer using 1-to 4 line Demultiplexer

with enable lines.
Solution: Let N = 8 (Output lines of DeMUX to be constructed) and M = 4 (Output
lines of available DeMUX)
Number of DeMUX required in Level I: N1= (8/4)
=2
N1 is not greater than M, so one level is possible. Two DEMUX are selected using
enable
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0
0 0 1 0 I 0 0 0 0 0 0
0 1 0 0 0 I 0 0 0 0 0
0 1 1 0 0 0 I 0 0 0 0
1 0 0 0 0 0 0 I 0 0 0
1 0 1 0 0 0 0 0 I 0 0
1 1 0 0 0 0 0 0 0 I 0
1 1 1 0 0 0 0 0 0 0 I

Example:
Construct 1-to-8 line Demultiplexer using 1:4 demultiplexer, and 1:2 demultiplexer.
Solution:
Two types of 1:4 demultiplexer and one type of 1:2 demultiplexer are needed.
Most significant selection line S2 is connected to DeMUX-I of level II.

Least significant selection line S1 S0 is given to DeMUX numbered II and III of level I.
Outputs of DeMUX-I of level II are connected to input lines of DeMUX numbered II and III of Level I.

Summary
Implement Logic Functions Using Multiplexer
➢ m-variable function using 2m-1 X 1 MUX. ➢ m-variable function using 2m X 1 MUX.

➢ Connect ( m -1) variables to the selection lines. ➢ Connect the m variables to the selection lines.
➢ Apply the remaining variable, its complement, 0 or 1 to the data inputs ➢ Connect the truth table output values to the data inputs.
Design Higher order Demultiplexer Using Lower Order Demultiplexers

➢ Thomas L. Floyd, “Digital Fundamentals” Pearson Education , 11th

edition , ISBN 10: 1-292-07598-8, 2015.
➢ D. P. Kothari, and J. S. Dhillon “Digital Circuits and Design” Pearson
Education , ISBN 978-93-325-4353-9, 2015.
➢ T. Ndjountche “Digital Electronics 1”, John Wiley & Sons, 1st edition,
ISBN 978-1-84821-984-7, 2016.
➢ Neal S. widmer and Gregory L. Moss “Digital Systems Principles and
Applications” Pearson Education , 12th edition , ISBN 10: 0-13-422013-7,
2017.
➢ Ata Elahi, “Computer Systems”, Springer, ISBN 978-3-319-66774-4, 2018.

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Ministry of Higher Education and Scientific Research

Al-Furat Al-Awsat Technical University

➢ Explain the Operation of a Johnson Counter.

➢ The implementation of the Four-bit Johnson counter is shown in Figure

➢ The complement of the output of the last flip-flop is connected back to

Four-bit Johnson sequence Mod-8

• Prepared by Huda Hussein Abed

Timing sequence for a 4-bit Johnson counter

5-bit Johnson counters.

Five-bit Johnson sequence.

• Prepared by Huda Hussein Abed

The Ring Counter

A 6-bit ring counter

6-bit ring counter sequence.

A 10-bit ring counter

Ten-bit ring counter sequence.

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1. Thomas L. Floyd, “Digital Fundamentals” Pearson Education ,

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➢ Describe the operation of four types of shift registers.

➢ A shift register consists of an arrangement of flip‐flops, each one of

➢ The shift capability of a register permits the movement of data from

1. Serial In /Serial Out Shift Registers (SISO).

2. Serial In/Parallel Out Shift Registers (SIPO).

3. Parallel In/Serial Out Shift Registers (PISO).

4. Parallel In/Parallel Out Shift Registers(PIPO).

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➢ It produces the stored information on its output also in serial form.

4-bit Shift Register implemented with D flip-flops Logic block symbol

➢ This register can store up to four bits of data.

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Note: For serial data, one bit at a time is transferred.

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➢ A shift register made up of JK or SR flip-flops has non-inverting output Q

➢ For the first flip-flop, between J and K ( or S and R) an inverter is

4-bit SISO Shift Register Using J-K Flip-Flop

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A Serial in / Parallel out Shift Register Logic Block Symbol

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The Q outputs 0100 after two clock pulses

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A 4-bit parallel in/serial out shift register Logic Block Symbol

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After three clock pulses, the data outputs are 1001.

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➢ G. K. Kharate, “Digital Electronics” Oxford university press , 7th

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➢ Explain the Basic Operation of a Multiplexer.

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No. of input lines = 2

➢ It can be represented by the symbol given in the figure below .

Data select Output

2-to-1 multiplexer Logic Symbols Function table