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Sequential Logic: Clocks & Flip-Flops

The document discusses sequential logic circuits and their components. It covers topics like clocks, latches, flip-flops, and how they are used to build registers and control sequential circuits. Examples of SR latches and D latches are provided along with their truth tables and timing diagrams.

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Topics covered

  • Combinational Logic,
  • Storage Elements,
  • D Latch,
  • Latches,
  • Output Definitions,
  • Technical Terminology,
  • Common Clock Operation,
  • State Variables,
  • Vending Machine Design,
  • SR Latch
36 views19 pages

Sequential Logic: Clocks & Flip-Flops

The document discusses sequential logic circuits and their components. It covers topics like clocks, latches, flip-flops, and how they are used to build registers and control sequential circuits. Examples of SR latches and D latches are provided along with their truth tables and timing diagrams.

Uploaded by

Phan Tuấn Khôi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Topics covered

  • Combinational Logic,
  • Storage Elements,
  • D Latch,
  • Latches,
  • Output Definitions,
  • Technical Terminology,
  • Common Clock Operation,
  • State Variables,
  • Vending Machine Design,
  • SR Latch

DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 6: Sequential Logic
Clocks, Latches, Flip-Flops
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang


School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

2
COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture


❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
3
CAN YOU DO IT?

A vending machine accepts nickels (5 cents), dimes (10 cents),


and quarters (25 cents) towards the purchase of a can of soda.
When the machine has received 40 cents or more, it dispenses
a can of soda and returns any money over 40 cents. For
example, if someone puts in two quarters, one after another,
the machine returns a can of soda and 10 cents.

Design a digital circuit to control the machine.

4
COMBINATIONAL VS. SEQUENTIAL CIRCUITS

5
SEQUENTIAL CIRCUITS
❑ Outputs depend on inputs and state variables

❑ The state variables embody the past history of the circuit


▪ Storage elements hold the state variables

❑ A clock periodically advances the circuit

6
SEQUENTIAL CIRCUITS
❑ Definitions
▪ Asynchronous sequential circuits: outputs and state change as
soon as an input changes
▪ Synchronous sequential circuits: outputs and state change only
when a special input, the clock, gets a certain value

7
CLOCK
❑ An input to a sequential circuit that changes output and
state values at a predetermined rate

❑ Triggering edge: Transition of the clock that captures


input data
▪ We mostly use the positive rising edge (L -> H) as triggering edge in this class
▪ Clock tick: Occurrence of a triggering edge

8
CLOCK PERIOD AND FREQUENCY
❑ Clock Period (cycle time): Time between successive
transitions in the same direction (e.g., L-> H)
▪ e.g., 1ms, 2ns, 500ps
❑ Clock Frequency: 1/period
▪ e.g., 1kHz, 500MHz, 2GHz

9
SR LATCH (SET-RESET LATCH)

10
SR LATCH (SET-RESET LATCH)

Boolean expression for


Qnext in terms of R, S, Q:

Qnext = (R + QN)’
= (R + (S + Q)’)’
= R’•(S + Q)
= R’•S + R’•Q
11
CAN YOU DO IT?

❑ Suppose the S-R latch is initialized with Q=0, write down the next state given the
following input sequence:

S=1, R=0 -> Q = ?


S=0, R=0 -> Q = ?
S=0, R=1 -> Q = ?

12
SR LATCH (SET-RESET LATCH)

❑ Instability (Avoid SR=11): SR=11 may cause instability of


the internal state
▪ When SR=11 -> Q=QN=0
▪ If inputs subsequently change to SR=00, output may
be undefined

13
D LATCH

❑ When C is enabled, Q output follows D input


❑ When C is disabled, Q output retains last state

14
D LATCH TIMING

❑ D latch is level sensitive


– Captures input D when the latch is open
– Holds the previous state otherwise
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D FLIP-FLOP

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D FLIP-FLOP TIMING

17
REGISTER
❑ Collection of FFs operating off common clock
❑ A single D flip-flop is a 1-bit register

18
BEFORE NEXT CLASS

• Textbook: 3.4- 3.5


• Next time: Finite State Machines

19

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