Professional Documents
Culture Documents
part 2
We will talk about:
• Error handling
• Performance
• CAN physical layer
• CAN hardware
Controller Area Network
Error handling
CAN communication
Every node receive any message
The transmitter listens while transmitting
•Bit error
•Stuff error
•Form error
•CRC error
•Acknowledgement error
1 11 2 18 1 2 4 0 - 64 15 1 1 1 7 3
Active Error
Flag Error Delimiter
Bus Line
6 8 8
Bus Line
error
active Normal mode request
and 128 occurrences of
11 consecutive rec bits
error bus
passive TEC > 255 off
11 consecutive rec bits = ACK delim + EOF + Interm
Error delimiter + Intermission
0 Stuff Bit
But sometimes only 2!
1 Stuff Bit (In case of a stuff bit interpreted as a
data bit and vice versa)
Original sequence
2 Stuffed sequence
3 Disturbed bus
4 Destuffed sequence
Same length and CRC sum, but only 2 false bits!
No error flags - No errors
• A poor bus
– lots of detected errors means means an
undetectable error-combination might slip
through
• A healthy bus
– no detectable errors means a very low
probability for undetectable error-
combinations to occur
Local Errors most common
Bus Line
11 or 29 bits
Arbitration
Envelope
CAN Id
CAN has min. 11 to max. 93 bits
that can be used for data transfer
-29 -19
Std
0 11+n × 8 63 0≤n≤8
-29 -1
0 29+n×8
63
Ext
Compressed Envelope
-29 -24 -1
Identifier Data
-29 -12 -1
Identifier Data
11 or 29 bit 0 - 8 byte
Arbitration
field
CAN Real-time Performance
•Repetition rate 10 ms, time resolution 1 ms
-Rather straight forward
•Repetition rate 1 ms, time resolution 100 µs
-Careful scheduling, careful programming.
-A Global Clock helpful
• Repetition rate 100µs, time resolution 10 µs
-A Global Clock necessary.
-A priori knowledge of process behaviour.
-Cyclic Software.
-Oversampling technique required
• Time resolution 1 µs
- Judged as the ultimate limit (CAN v2.0).
Information that has to be
defined at a node before
transmission takes place:
•Bit length
•Sampling point and SJW
•Higher Layer Protocol
•Physical address
Controller Area Network
CAN physical layer
CAN_H
2.0 - 2.5 - 3.0 V
3.0V
2.0V CAN_L
2.0 - 2.5 - 3.0 VDiff. output
- 500 - 0 - 50 mV
Dominant State Voltages
CAN_H >> CAN_L
Diff. input
0.9 - 5.0 V
1.5V CAN_L
0.5 - 1.5 - 2.25 V
Physical bit representation
Vdiff CAN_H
Vdiff
CAN_L
Recessive DominantRecessive
Time
Always terminate the bus