Analysis and Design of ZVS-PWM Half-Bridge Converter
with Secondary Switches
Kazurou Harada, Yoshiyuki Ishihara and Toshiyuki Todaka
Department of Electronics
Doshisha University
Tanabe, Kyoto 610-03 JAPAN
-
ABSTRACT An improved Zero-Voltage-Switching (ZVS)PWM
half-bridge converter with secondary switches is proposed and
analyzed. The proposed converter is controlled by PWM of main
switches using novel switching sequence with a constant switching
frequency. The main switches operate with zero voltage switching,
and the secondary switches turn on and off with zero voltage and
zero current. A small saturable inductor is added in series of the
secondary switch in order to achieve zero voltage switching easily.
From the analysis, steady state characteristics of the converter
and conditions of the zero voltage switching are derived.
INTRODUCTION
Zero-Voltage-Switching (ZVS) PWM converters[1-51 have
several advantages such as low device stresses and PWM control
with a constant switching frequency in comparison with the
conventional resonant converters. In proposed ZVS-PWM
bridge-type converters that are suitable for high power
applications, the ZVS full-bridge phase shifted converters[4, 51
have been reported frequently because of facility of the output
control by use of phase shift. However, these converters need
circulating current for achieving ZVS, which causes conduction
loss. On the other hand, with regard to ZVS half-bridge
converters, it is difficult to control the output for the reason that
the off interval of both switches is fixed for achieving ZVS.
The auxiliary switches or magnetic amplifiers are needed in
order to control the output of these converters, however, it
causes the switching losses of the auxiliary semiconductor
switches or the core loss of the magnetic amplifiers. In order
to control the output of ZVS half-bridge converters without
increase of loss, we proposed a ZVS-PWM half-bridge converter
with secondary switches[6]. The proposed converter consists of
the conventional half-bridge converter and two added switches
in series of the secondary rectifier diodes. This converter is
controlled by PWM of main switches using novel switching
sequence with a constant switching frequency. The main switches
operate with zero voltage, and the secondary switches turn on
0-7803-2730-6195$4.00Q ISSS IEEE 280
and off with zero voltage and zero current. Therefore, tum-on-loss
and turn-off-loss of the secondary switches are completely
negligible. Voltage and current stress of the switches and other
components are similar to those of the conventional PWM
converter.
This paper presents an improved ZVS-PWM half-bridge
converter with secondary switches. A small saturable inductor
is added in series of the secondary switch in order to achieve
zero voltage switching easily. Characteristics of this converter
becomes clear from the analysis and it is verified by the
experiment.
PRINCIPLE OF OPERATION
The basic configuration of the ZVS-PWM half-bridge
converter with secondary switches is shown in Fig. 1. MOSFETs
are used in this case as the main switches Q1, Q2, and the
secondary switches Q3, Q4 in series of the output rectifiers.
Magnetization inductance and leakage inductance of the
transformer can be used as inductor Lm and L, respectively. A
small saturable inductor is connected in series of the secondary
switch 4 2 in order to realize ZVS of switch Q2 easily. Fig. 2
shows the gate drive voltages Vgsl-4 of switches 41-4, and
ideal waveforms of this converter. Where, Ts is the switching
period and D is the nominal duty ratio. The period DTs in the
figure is "ON period" of the converter where power is delivered
to the output because the secondary switch in series of the
output rectifier is on. On the other hand, the other period in Ts
is "OFFperiod" of the converter because the secondary switch
is off. The switches are driven in the following manner: if one
switching period ends as "ON period", the next switching period
starts as "ON period", and if one switching period ends as
"OFF period", the next switching period starts as "OFF period".
The main switches Q1 and Q2 are driven alternately with a
short interval Td when both the switches are off. The main
switches operate with zero voltage switching because the charges
of the parasitic capacitance of the switch is swept out with the
aid of the inductor L or Lm during the interval Td. In addition,
due to the voltage of the secondary winding of the transformer
and the rectifier Drl and Dr2, the secondary switches 4 3 and
Q4 turn on and off with zero voltage switching and zero current
switching. So selection of the secondary switches is considered
only with regard to low conduction loss.
STEADY STATE CHARACTERISTICS
The proposed converter has 15 operating states during 2Ts
as shown in Fig. 2. The equivalent circuits of these 15 operating
states are shown in Fig.3. In order to simplify the analysis, it is
assumed that the output filter inductor Lo is sufficiently large
to be regarded as a current source and the internal resistance of
this circuit is negligible. In addition, it is assumed that the
unsaturated inductance of the saturable inductor is sufficiently
large and the saturation inductance of that is Ls. Assuming
that the commutating periods (state 1, 2, 5, 6, 9, I I, 12) and
unsaturated period of the saturable inductor (state 13) are
sufficiently short to be negligible, the dc voltage conversion

* Df CO R Eo

Fig. 1 ZVS-PWM half-bridge converter with secondary switches.

where T3 and T14 are the period times of state 3 and 14, which
causes duty cycle loss.
During state 3 and 14, the primary current i varies linearly as
follows:
E,
2L ( t - t2 )
state 3 : i (t) = i (t2) + - (2)

Vgsl nl ! I I I I I
I
I From (2)(3), T3 and TI4 are derived as
vgs2
(4)

2 ( L + N 2 L s ) I, 2(L+N2Ls)
TI4= ( + i itl3)) . -N
Ei
--.
I

E,
(5)

Therefore, the dc voltage conversion ratio is derived as

( 3~ + N ~ L , I,
Ei - 2N N Ei T,
Derived equation shows that the dc voltage conversion ratio
depends on the output current, however, this dependence on the
load can be improved by minimizing the inductance L and the
saturation inductance N’Ls. This duty cycle loss dependent on
the load of this converter is much small than that of ZVS full-
bridge converter which need the inductance for freewheeling
current.

t ZERO-VOLTAGE-SWITCHING CONDITIONS

In this circuit, zero voltage switching is achieved due to the

Fig. 2 Idealized waveforms. sum of the output current Io/N and the magnetizing current im
281
 I I

(a) State 1 U ( f ) State 6 @ (k) State 11 @

(b) State 2 w
Lm
(g) State 7 @ (I) State 12 -kt
L
a - . Im
b
i L

D3
Drl Dr2

(c) State 3 (h) State 8 @ (m) State 13 @

Lm
b
b
L

(d) State 4 %
(i) State 9 (n) State 14 @
1
a L
- &,Q1 b

(e) State 5
t&-l (j)State 10 @ (0)State 15

Fig. 3 Equivalent circuits in 15 operating states.

282
during Tdl and Td2. During Td3 and Td4, ZVS is achieved
with the aid of the magnetizing current im. Assuming that the
commutation period of the switches and state 3, 7, 13, 14 are
sufficiently short to be negligible, variation of the magnetizing
current im during 2Ts is shown as Fig.4. The magnetizing current
im of state 4 and state 8 is expressed as
i, = I,, + -Ei t
( 0 5 t I DT, ) (7)
2Lm
Ei
i, = I, - __ ( t - DTS) (DT, 5 t STs ) (8)
2Lm
where Iml and Im2 are peak values of the magnetizing current
shown in the figure. When the magnetization characteristic of
the transformer isn’t DC biased, the peak values of the
magnetizing current Iml, Im2 and Im3 are derived as
(9)
Since the switches are commutated with the aid of the
magnetizing current Im3 during dead time Td3, and Im2 during
dead time Td4, the following conditions of ZVS are derived.
Td3 : Im3 < 0, Td4 : Im2 > 0 (12)
From (IO), the condition concerning Im2 is satisfied as follows:
With regard to Im3, the following condition of the duty ratio is
derived from (1 1).
1
D < -= 0.7
fi-
There is an upper limit of the duty ratio in order to achieve
ZVS during dead time Td3. However, the switching loss is
small enough to be negligible at the duty ratio over this upper
limit because the switching current is sufficiently small.
Fig. 4 Variation of magnetizing current im
283
During Tdl and Td2, the switches are commutated due to
the sum of the output current -Io/N and the magnetizing current
im, so that the following conditions of ZVS are derived.
Tdl : -Io/N+Iml < 0, Td2 : Io/N+Im2 > 0 (15)
Since Im2>0 from (13), the condition at Td2 is always satisfied.
On the other hand, (9) shows that Iml becomes positive at the
duty ratio D < 1 4/fis 0.3 as follows:
Therefore, there is a lower limit of the output current as (17) in
order to achieve ZVS during dead time Tdl when the duty ratio
is small.
10 EiTs
->- (17)
N 4L,
In order to achieve ZVS, each dead time Td is longer than
commutation time Tc of the switches and then the switch has to
be turned on during conduction period Ta of the body diode of
the switch. In this circuit, Tdl, Td2 and Td3 can be set easily
to achieve ZVS, however, it is a little difficult to set Td4, i.e.,
turn-on-timing of switch Q2 from t = t15. This is because
conduction period Ta of the body diode D2 is very short. So a
saturable inductor is added in series of the secondary switch 42
in order to realize ZVS of switch Q2 easily. The saturable
inductor prevents the load current from flow in the primary
switch in this period, so that the conduction period of the inversely
parallel diode D2 of the switch Q2 gets longer. Therefore, the
turn-on-timing of switch Q2 can be set easily.
RESET MECHANISM OF SATURABLE INDUCTOR
In this converter, the flux of the saturable inductor is reset
with the aid of the secondary diode. The reset mechanism of
the saturable inductor has to be cleared in order to set dead
time Td4 where ZVS is achieved.
The equivalent circuit of secondary circuit including the
saturable inductor in reset period (State 10) is shown in Fig.5.
In the figure, Re is equivalent resistance that represent eddy
current loss of saturable core and Cd is depletion capacitance
of rectifier diode Dr2. From the equivalent circuit, the voltage
V, of the saturable inductor in reset period is derived as follows:
Ei
V, = - 2N exp (-at) (18)
where,
a=--. 1
N3wd
 ””
EnN

i
(SOVIdiv.)
Re

No

T Cd

Fig. 5 Equivalent circuit of saturable inductor in reset period.

The voltage Ei/2N is applied to the saturable inductor during

the gate unsaturated period. Since the flux swings are equal in
the steady state, the unsaturated period Tg is given as
1
Tg=-{ l-exp[-a(l-D)Ts]}. (19)
a
This unsaturated period Tg can be varied by connecting external
capacitance to the diode instead of changing the number of the
winding turns which causes duty cycle loss. t 1 Time (2 U s/div.) 1
EXPERIMENTAL RESULTS Fig. 6 Observed waveforms of switch voltages Vdsl, Vds2, Vds3,
switch currents iQ1, iQ2, iQ3 and primary current i.
In order to verify the operation, we breadboard the proposed
converter. In the experiment, a magnetic snubber is used to
remove the voltage ringing between the inductance L and the
parasitic capacitances of the secondary circuit during state 8
and 10. The parameters of the circuit in the experiment and
calculation are as follows:
L = 3.0pH, Lm = 60pH. Ls = WH,
Tums ratio N = nl/n2 = 1,
Input voltage Ei = IOOV,
Switching frequency fs = Ins = 100kHz.
Fig. 6 shows the observed waveforms of the switch voltages
and currents and the primary current. From the voltage waveforms
Vdsl, Vds2 of the main switches Ql. Q2 and the current i,,, i,,
flowing through the switch Q1, Q2, it is shown that ZVS of the
main switches is achieved. In addition, the voltage and current
Load current [A]
waveforms Vds3 and G3 of the secondary switch Q3 show that
the secondary switch turns on and off with zero voltage and
zero current. Fig. 7 shows load characteristics taking the nominal Fig. 7 Load characteristics.
duty ratio D as a parameter. The output voltage is decreased for
larger load current because of the inductance L and Ls shown
as (6). CaIcuIated results agree well with the experimental results.
The measured efficiency of this converter at 25V output as a
function of a load current is shown in Fig.8. The maximum
efficiency is about 92% in this experiment.
inductor is added in series of the secondary switch in order to
achieve zero voltage switching easily. From the analysis, the
steady state characteristics of the converter and the conditions
of zero voltage switching are derived. It is cleared that the
converter has the maximum duty ratio and the minimum load
current for achieving ZVS under any condition. In addition, the
reset mechanism of the saturable inductor becomes clear from
the analysis. In the experiment, the converter has an efficiency
about 92% at 25V output with lOOkHz operation.

REFERENCES

[ 11 0. D. Patterson, and D. M. Divan, "Pseudo-Resonant Full Bridge

DC/DC Converter," E E E PESC Record, 1987, pp. 424-430.
[2] C. P. Henze, H. C. Martin, and D. W. Parley, "Zero-Voltage
Switching in High-Frequency Power Converters Using Pulse Width
.. .. .. .. .. ..
.
701
0
I
1
'2. .
3 4 5 6
.
I
. .
I
7
Modulation," Proceedings of IEEE APEC, 1988, pp. 33-40.
[3] K. Harada, and H. Sakamoto, "Non-Resonant Converter for
Load current [A] Megahertz Switching," IEEE PESC Record, 1989, pp. 889-984.
[4] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho,
Fig.8 Measured efficiency as a function of load current. "Design Considerations for High-Voltage High-Power Full-Bridge
Zero-Voltage-Switched PWM Converter," Proceedings of IEEE APEC,
1990, pp. 275-284.
[SI R. Redl, N. 0. Sokal, and L. Balogh, "A Novel Soft-Switching
CONCLUSION Full-Bridge DC/DC Converter: Analysis, Design Considerations, and
Experimental Results at 1.5kW. lOOkHz," IEEE PESC Record, 1990,
An improved ZVS-PWM half-bridge converter with pp. 162-172.
[6] K. Harada, Y. Ishihara, and T. Todaka, "A Novel ZVS-PWM
secondary switches has been presented and analyzed. In this
Half-Bridge Converter," Proceedings of IEEE INTELEC, 1994, pp.
converter, the main switches operate with ZVS and the secondary 588-593.
switches turn on and off with ZVS and ZCS. A small saturable

285