Computer Architecture Unit 3

assumed to hold an index number that is relative to the address part of the
instruction.
A base register is assumed to hold a base address and the address field of
the instruction, and gives a displacement relative to this base address. The
base register addressing mode is handy for relocation of programs from one
memory to another as required in multi programming systems.
The address values of instruction must reflect this change of position with a
base register, the displacement values of instructions do not have to
change. Only the value of the base register requires updating to reflect the
beginning of a new memory segment.
Self Assessment Questions
5. ______________ instructions are implied mode instructions.
6. Relative Address Mode is applied often with ___________ instruction.
7. The _______________ is a special CPU register that contains an index
value.

3.5 Operations in the Instruction Sets

A program has a sequence of instructions and it is located in the computer’s
memory unit. The program is implemented by following a cycle for each
instruction. Every instruction cycle is subdivided into a series of sub cycles
or phases. The following describes the parts of an instruction cycle:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an
indirect address.
4. Execute the instruction.
After the completion of step 4, the control goes back to step 1 to fetch,
decode and execute the next instruction. This process continues indefinitely
unless a HALT instruction is encountered. In an improved instruction
execution cycle, we can introduce a third cycle known as the interrupt cycle.
Figure 3.3 illustrate how the interrupt cycle fits into the overall cycle.

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Figure 3.3: Instruction Cycle with Interrupts

3.5.1 Fetch & decode

To bring the instructions from main memory into the instruction register, the
CPU first places the value of PC into memory address register. The PC
always points to the next instruction to be executed. The memory read is
initiated and the instruction from that location gets copied in Instruction
Register (IR). PC is also incremented by one simultaneously so that it points
to the next instruction to be executed. This completes the fetch cycle for an
instruction as shown in figure 3.4.

Figure 3.4: Instructions Cycle

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Decoding means interpretation of the instruction. Each and every instruction

initiates a sequence of steps to be executed by the CPU. Decoding means
deciding which course of action is to be taken for execution of the instruction
and what sequence of control signals must be generated for it. Before
execution, operands, i.e. necessary data is fetched from the memory.
3.5.2 Execution cycle (instruction execution)
As studied in the previous sections, the fundamental task performed by a
computer is the implementation of a program. The program, that is to be
executed, is a set of instructions, and is stored in memory. The task is
completed when instructions of the program are executed by the central
processing unit (CPU). The CPU is mainly responsible for the instruction
execution. Now, lets examine several typical registers some of which are
generally available in the machines.
These registers are:
Memory Address Register (MAR): It identifies the address of memory
location from where the data or instruction is to be accessed (for read
operation) or where the data is to be stored (for write operations).
Memory Buffer Register (MBR): It is a register that temporarily stores the
data that is to be written in the memory (for write operations) or the data
received from the memory (for read operation).
Program Counter (PC): The program counter keeps a record of the
instruction that is to be performed after the instruction in progress.
Instruction Register (IR): Here, loading of the instructions take place
before they are executed.
The model of instruction processing can simply be stated in a two-step
process. Firstly, the CPU reads (fetches) instructions (codes) from the
memory one by one, and executes or performs the operation specified by
this instruction.
The instruction fetch is performed for every instruction. Instruction fetch
involves reading of an instruction from a position, where it is stored, in the
memory to the CPU. The execution of this instruction may entail various
operations as per the nature of the instruction.

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An instruction cycle refers to the processing needed for a single

instruction (fetch and execution). The instruction cycle consist of the fetch
cycle and the execute cycle.
Program execution comes to an end if:
 The electric power supply is stopped or
 Any irrecoverable error occurs, or
 When a program is executed in sequence.
The fetched instruction is in the form of binary code and is loaded into an
instruction register (IR), in the CPU. The CPU interprets the instruction and
takes the required action.
Self Assessment Questions
8. In an improved instruction execution cycle, we can introduce a third
cycle known as the _________________________.
9. Write the full form of:
a. MAR
b. MBR

3.6 Instructions for Control Flow

Memory locations are storage houses for instructions. When processed in
the CPU, the instructions are fetched from consecutive memory locations
and implemented. Each time an instruction is fetched from memory, the
program counter is simultaneously incremented with the address of the next
instruction in sequence. Once a data transfer or data manipulation
instruction is executed, control returns to the fetch cycle with the program
counter containing the address of the instruction next in sequence.
In case of a program control type of instruction, execution of instruction may
change the address value in the program counter and cause the flow of
control to be altered. The conditions for altering the content of the program
counter are specified by program control instruction, and the conditions for
data-processing operations are specified by data transfer and manipulation
instructions.
As a result of execution of a program control instruction, a change in value
of program counter occurs, which causes a break in the sequence of
instruction execution. This is an important feature in digital computers, as it

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provides control over the flow of program execution and a capability for
branching to different program segments. Some typical program control
instructions are listed in table 3.5.
Table 3.5: Typical Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST

The branch and jump instructions are identical in their use but sometimes
they are used to denote different addressing modes. The branch is usually a
one-address instruction. Branch and jump instructions may be conditional or
unconditional.
An unconditional branch instruction, as a name denotes, causes a branch to
the specified address without any conditions. On the contrary the conditional
branch instruction specifies a condition such as branch if positive or branch
if zero. If the condition is met, the program counter is loaded with the branch
address and the next instruction is taken from this address. If the condition
is not met, the program counter remains unaltered and the next instruction
is taken from the next location in sequence.
The skip instruction does not require an address field and is, therefore, a
zero-address instruction. A conditional skip instruction will skip the next
instruction, if the condition is met. This is achieved by incrementing the
program counter during the execute phase in addition to its being
incremented during the fetch phase. If the condition is not met, control
proceeds with the next instruction in sequence where the programmer
inserts an unconditional branch instruction. Thus, a skip-branch pair of
instructions causes a branch if the condition is not met, while a single
conditional branch instruction causes a branch if the condition is met.
The call and return instructions are used in conjunction with subroutines.
The compare instruction performs a subtraction between two operands, but

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