Computer Architecture Unit 5

iteration. PES has hardware resources which contain one path to the
memory, two integer units and one branch unit.

Figure 5.11: Example of PES

You can see that rows are showing the time steps and columns are showing
certain operations performed in time step. In this PES we can see that in
branch unit “ble” is not taken and it is theoretically executing instruction from
predicted path. In this example we have showed renaming values for only
r3 register but others can also be renamed. Various values allotted to
register r3 are bounded to different physical register (R1, R2, R3, R4).
Now you can see numerous ways of arranging instruction issue buffer for
boosting up the complexity.
Single queue method: Renaming is not needed in single queue method
because this method has 1 queue and no out of ordering issue. In this
method the operand availability could be handled through easy reservation
bits allotted to every register. During the instructional modification of register
issues, a register reserved and after the modification finished the register is
cleared.
Multiple queue method: In multiple queue method, all the queues get
instruction issue in order. Due to other queues some queues can be issued
out. With respect to instruction type single queues are organized.
Reservation stations: In reservation stations, the instruction issue does not
follow the FIFO order. As a result for data accessibility, the reservation
stations at the same time have to observe their source operands. The
conventional way of doing this is to reserve the operand data in reservation

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station. As reservation station receive the instruction then available operand

values are firstly read and placed in it.
After that it logically evaluate the difference between the operand
designators of inaccessible data and result designators of finishing
instructions. If there is similarity, then the result value is extracted to
matching reservation station.
Instruction got issued as all the operands are prepared in reservation
station. It can be divided into instruction type for decreasing data paths or
may behave as a single block.
Self Assessment Questions
9. In traditional pipeline implementations, load and store instructions are
processed by the ____________________.
10. The consistency of instruction completion with that of sequential
instruction execution is specified b _______________.
11. Reordering of memory accesses is not allowed by the processor which
endorses weak memory consistency does not allow (True/False).
12. _____________ is not needed in single queue method.
13. In reservation stations, the instruction issue does not follow the FIFO
order. (True/ False).

5.6 Summary
 The design space of pipelines can be sub divided into two aspects:
basic layout of a pipeline and dependency resolution.
 An Instruction pipeline operates on a stream of instructions by
overlapping and decomposing the three phases (fetch, decode and
execute) of the instruction cycle.
 Two basic aspects of the design space are how FX pipelines are laid out
logically and how they are implemented.
 A logical layout of an FX pipeline consists, first, of the specification of
how many stages an FX pipeline has and what tasks are to be
performed in these stages.
 The other key aspect of the design space is how FX pipelines are imple-
mented.

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 In logical layout of FX pipelines, the FX pipelines for RISC and C1SC

processors have to be taken separately, since each type has a slightly
different scope.
 Pipelined processing of loads and stores consist of sequential
consistency of instruction execution and parallel execution.

5.7 Glossary
 CISC: It is an acronym for Complex Instruction Set Computer. The CISC
machines are easy to program and make efficient use of memory.
 CPA: It stands for carry-propagation adder which adds two numbers
and produces an arithmetic sum.
 CSA: It stands for carry-save adder which adds three input numbers
and produces one sum output.
 LMD: Load Memory Data.
 Load/Store bypassing: It defines that either loads can bypasss stores
or vice versa, without violating the memory data dependencies.
 Memory consistency: It is used to find out whether memory access is
performed in the same order as in a sequential processor.
 Processor consistency: It is used to indicate the consistency of
instruction completion with that of sequential instruction execution.
 RISC: It stands for Reduced Instruction Set Computing. RISC
computers reduce chip complexity by using simpler instructions.
 ROB: It stands for Reorder Buffer. ROB is an assurance tool for
sequential consistency execution where multiple EUs operate in parallel.
 Speculative loads: They avoid memory access delay. This delay can
be caused due to the non- computation of required addresses or
clashes among the addresses.
 Tomasulo’s algorithm: It allows the replacement of sequential order by
data-flow order.

5.8 Terminal Questions

1. Name the two sub divisions of design space of pipelines and write short
notes on them.
2. What do you mean by pipeline instruction processing?
3. Explain the concept of pipelined execution of Integer and Boolean
instructions.

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Computer Architecture Unit 5

4. Describe the logical layout of both RISC and CISC computers.

5. Write in brief the process of implementation of FX pipelines.
6. Explain the various subtasks involved in load and store processing
7. Write short notes on:
a. Sequential Consistency of Instruction Execution
b. Instruction Issuing and Parallel Execution

5.9 Answers
Self Assessment Questions
1. Microprocessor without Interlocked Pipeline Stages
2. Dynamically
3. Write Back Operand
4. Opcode, operand specifiers
5. Register operands
6. True
7. Intel 80x86 and Motorola 68K series
8. Carry-propagation adder (CPA)
9. Master pipeline
10. Processor Consistency
11. False
12. Renaming
13. True

Terminal Questions
1. The design space of pipelines can be sub divided into two aspects:
basic layout of a pipeline and dependency resolution. Refer Section 5.2.
2. A pipeline instruction processing technique is used to increase the
instruction throughput. It is used in the design of modern CPUs,
microcontrollers and microprocessors.Refer Section 5.3 for more details.
3. There are two basic aspects of the design space of pipelined execution
of Integer and Boolean instructions: how FX pipelines are laid out
logically and how they are implemented. Refer Section 5.4.
4. While processing operates instructions, RISC pipelines have to cope
only with register operands. By contrast, CISC pipelines must be able to
deal with both register and memory operands as well as destinations.
Refer Section 5.4.

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5. Depending on the function to be implemented, different pipeline stages

in an arithmetic unit require different hardware logic. Refer Section 5.4.
6. The execution of load and store instructions begins with the
determination of the effective memory address (EA) from where data is
to be fetched. This can be broken down into subtasks. Refer
Section 5.5.
7. The overall instruction execution of a processor should mimic sequential
execution, i.e. it should preserve sequential consistency. Refer
Section 5.5. The first step is to create and buffer execution and then
determine which tuples can be issued for parallel execution. Refer
Section 5.5.

References:
 Hwang, K. (1993) Advanced Computer Architecture. McGraw-Hill.
 Godse D. A. & Godse A. P. (2010). Computer Organisation, Technical
Publications. pp. 3–9.
 Hennessy, John L., Patterson, David A. & Goldberg, David (2002)
Computer Architecture: A Quantitative Approach, (3rd edition), Morgan
Kaufmann.
 Sima, Dezsö, Fountain, Terry J. & Kacsuk, Péter (1997) Advanced
computer architectures - a design space approach, Addison-Wesley-
Longman: I-XXIII, 1-766.

E-references:
 http://www.eecg.toronto.edu/~moshovos/ACA06/readings/ieee-
proc.superscalar.pdf
 http://webcache.googleusercontent.com/search?q=cache:yU5nCVnju9
cJ:www.ic.uff.br/~vefr/teaching/lectnotes/AP1-topico3.5.ps.gz+load+
store+sequential+instructions&cd=2&hl=en&ct=clnk&gl=in

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