Somaiya Vidyavihar University

K. J. Somaiya College of Engineering, Mumbai -77

(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

Batch: A1 Roll No.: 16010322019

Experiment No.___04___
DIVAY HEMENDRA GALANI Grade: AA / AB / BB / BC / CC / CD /DD

Signature of the faculty In-charge with date

Experiment No: 4

TITLE: Implementation of D Flip Flop.

AIM:- i. Write VHDL code for D Flip-flop using Process statement.
ii. Verification of code using simulation test bench.

iii. Hardware results usingCPLD/FPGA.

OUTCOME: Student will be able to

CO1: Describe sequential logic circuit using HDL
.CO3: Simulate HDL code.
CO4: Implement designed code on an available CPLD/FPGA.

 VHDL Code:
1. VHDL Code for D-flip flop using process statement.

HDL/ Sem IV/ Jan- May 24

 Somaiya Vidyavihar University
K. J. Somaiya College of Engineering, Mumbai -77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

 RTL Schematic:

 Simulation Waveforms:

HDL/ Sem IV/ Jan- May 24

 Somaiya Vidyavihar University
K. J. Somaiya College of Engineering, Mumbai -77
(A Constituent College of Somaiya Vidyavihar University)
Department of Electronics and Telecommunication Engineering

Post Lab Questions

1. Design J-k flip-flop using process statement.

CONCLUSION:
From the above experiment, we learned to design sequential logic circuits – Flip
Flops using HDL, implemented & executed D flip flop & JK flip flop in software &
hardware.

Signature of faculty in-charge

HDL/ Sem IV/ Jan- May 24