Source synchronous interface timing closure

Babul AnunayAmol Agarwal,Priya Khandelwal, - July 18, 2016

Source synchronous timing protocols play a crucial role in modern high-speed interfaces. This article
deals with the different types of source synchronous protocols from a timing perspective and the
challenges in timing closure they present.

Figure 1: Source synchronous protocol

As shown in the figure in forward source synchronous timing protocols, a clock is sent as a reference
to sample data being sent along. This helps the receiver avoid meta-stability by maintaining skew
between the data and the incoming clock signal.

There are scenarios, however, where the data recipient has to send a clock based on which the data
sender sends the data. The huge roundtrip time does not permit the frequency to rise, which is why
most senders send another clock/strobe along with the data for ease of sampling on the receiver
side. However, there are two ways for the transmitter to send the data, which will be discussed in
detail here.

Transmitter Sending Output delayed data with respect to Clock

 Figure 2 : Delayed data being sampled at next edge

As shown in the figure 2, in this case, the transmitter holds onto the data before sending it. While
this act seems trivial on the part of the transceiver, it actually takes a lot of effort in physical
implementation to hold on to the data in fast process, high voltage and delay-reducing temperature
conditions. It can alternatively use faster clock edges to launch the data after a desired digital phase
shift.

The transmitter starts changing the data after a time usually termed as output hold (tHO). The
transmitter is allowed to change the data until a time usually termed as data valid output (tDVO).
tDVO falls short of the sampling edge of clock after which data is again valid and stable. tDVO – tHO
is usually termed as data invalid window of the transmitter, a part of available phase-shift where it is
allowed to change data. The remaining part of available phase shift is called as data valid window.

It is important to note that by virtue of holding the data, the transmitter has made sure that the
sampling edge lies in the valid window. The part of the valid window before the sampling edge is
used by the receiver to meet the setup time on its capturing/sampling flop and is termed as input
setup time of the receiver. The part of the valid window after the sampling edge helps in meeting the
hold check on the capturing flop and is termed as input hold time of the receiver. The receiver, thus,
has to do minimum maneuvering with the incoming clock and matches skew of the incoming clock
with the incoming data.

Transmitter Sending Output skewed data with respect to Clock

 Figure 3 : Skewed data being sampled at next edge

Let’s consider the other possibility as shown in the figure 3. The transmitter now no longer holds the
data but rather sprays it around the clock it is sending to the receiver. The data is thus skewed on
both sides of the clock edge. Considering a double data rate (also called double toggle rate)
scenario, if the receiver tries to sample this data on the next edge, note that the tHO parameter is
negative so it will have to delay its data by at least x (where x is greater than tHO + hold check) to
send the valid window near the clock edge. This would add a lot of buffers/repeaters and cause an
area overhead. A worse scenario is that for every push by a margin of x provided in delay-reducing
process-voltage-temperature (PVT) conditions, there is a 3x-4x push in delay-increasing PVT
conditions, which might take the valid data away from the sampling edge again.

Figure 4: Skewed data being sampled at same edge

Now let us observe what happens if the receiver tries to sample data on the same edge itself as
shown in the figure 4. In this case there is sufficient hold time for the receiver to meet its hold
check. However, tDVO is now beyond the setup check so setup violation will occur leading to meta-
stability.

Figure 5 : Skewed data being sampled at same shifted edge

The receiver has to now come up with a strategy to delay/shift the clock more than the data to push
the clock inside the valid window so that sufficient margin is left on both sides of the shifted clock to
meet both setup and hold as shown in figure 5. There are two ways to do this:

1. Architectural Shift Solution

A normal solution would be to 90 degree phase shift the clock to push it in the middle of the
available phase shift and helps attain the receiver a positive input setup time and hold time.
However, this is easier said than done because the incoming clock has no phase relationship with
other clocks in the design and synchronization structures would have to be put in place to absorb
the meta-stability. There is also the requirement of a clock with double the frequency to get the
90 degree phase shift. Shifting by other phase shift margins such as 45 degree or 135 degree can
be explored based on data valid window deviation from clock but that would require even higher
frequency clocks.

2. Physical Shift Solution

Alternatively, the clock can also be used using physical artefacts by placing more
buffers/repeaters in the clock path. However, this is even trickier than the architectural solution
since the amount of minimum shift required is same in all process, voltage and temperature
conditions. Again, for any shift x provided in delay-reducing process-voltage-temperature (PVT),
there is a 3x-4x shift in delay-increasing PVT which might take the clock edge again into the
invalid window if the data valid window is small, which it is likely to be if higher frequencies are
targeted.

Thus the receiver has to choose the lesser of two evils to sample the edge skewed data. None of this
would have been necessary if the transmitter had held onto the data for a while but in that case the
transmitter had to face the hardship of keeping data valid for a declared period of time even in
delay-reducing PVT. The problem is severe when the transmitter device is not fixed and the receiver
needs to plan for handling both the Output delayed data and edge skewed data. Interfacing of SoCs
with various flash devices is a common example for this situation as both types of flashes are
available in the market. Standardization of specifications through recognized bodies or consortia (of
vendors) would help narrow down the problem so that increased frequencies can be achieved to
scale new heights in performance.

—The authors are with Freescale India (NXP)