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PCB Thermal Via Optimization using DOE

PCB Thermal Via Optimization using Design of Experiments

Tony A. Asghari
Motorola
21440 W. Lake Cook Rd.
Deer Park, IL 60010 USA

480-200-3448

ABSTRACT INTRODUCTION

In order to achieve a low thermal resistance path directly beneath
high power dissipating transistors, a thermal via and printed circuit
board (PCB) optimization study was performed. The thermal
resistance normal to the PCB surface served as the primary
reference output, while the calculation parameterization was varied
to minimize this thermal resistance.
A fractional factorial designed experiment (DOE) was developed
using MINITABTM statistical software for the following thermal via
and PCB factors, evaluated at two levels: via diameter, pitch, and
barrel thickness as well as PCB top Cu pad area and number of
metalized layers.
The results for each DOE treatment combination were simulated as
a parametric run using a finite volume computational fluid dynamics
(CFD) software tool – Icepak®. Steady-state thermal resistance
values, from a power source on top of PCB to the bottom of board,
were determined.
This demonstrates a methodology of coupling statistical DOE with
thermal CFD to efficiently optimize the thermal performance during
the early design process.
A statistical factorial design of experiments is an efficient means to
simultaneously study several input factors' effects on an output
response and determine optimal settings for them. In addition, any
potential interactions between the factors can be evaluated. By
varying the levels of the factors, simultaneously, the calculation is
extremely cost-effective, as fewer computer thermal simulation
models need to be run in order to determine the optimal response
output.
Factorial designs answer questions such as:
• Which variables exercise the most influence on
the output response?
• What factor settings will optimize the results?
Previous work includes coupling DOE and CFD to linearly optimize
various aspects of thermal performance at the system-level of a
network server [1]. Advantages of using DOE to reduce process
variation and improve quality have been demonstrated [2].
Response Surface Methodology takes the study one step further by
using central composite designs to determine an optimal point on a
non-linear curve between the end point levels [3].

KEY WORDS

Design of Experiments, Factorial Design, The purpose of this optimization study is to select the factors (via
MINITABTM, Icepak® CFD, PCB, Thermal diameter, pitch, top copper (Cu) pad thickness, via barrel thickness,
Resistance, Thermal Via, Optimization and number of Cu layers) and select values for them that will result
in reducing the overall thermal resistance of a PCB.
NOMENCLATURE
DIAM = thermal via diameter
This paper shows a technique of combining statistical DOE with
PITCH = adjacent thermal via center to center distance thermal CFD to efficiently optimize the thermal resistance of a PCB
during the early design process.
TOP_CU = PCB top copper thickness
BARREL = thermal via copper barrel thickness
LAYERS = PCB metalized copper layers

0-7803-9524-7/06/$20.00/©2006 IEEE 224

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PROCEDURE
MINITABTM
• MINITABTM release 14 statistical software was used to create
and analyze a designed experiment (DOE), in order to
measure the effects of the following factors (shown in
Table 1) on FR4 board overall thermal resistance:
Table 1: DOE Factors at 2 levels. Note, 1 mil = 0.001 inch.
• 5 factors were each analyzed at 2 levels using a ½ fraction
factorial 25-1 Resolution V design resulting in 16 Icepak®
runs. • The 2 levels were chosen based on PCB
supplier capability and thermal engineering design experience as
well as PCB electrical functionality. • 16 computer simulations
were performed in Icepak® & subsequent thermal resistance
values were
obtained, for each of the 16 treatment combinations (see Table
2). • Resolution V design provides main effects and 2-way
interactions. 3rd & 4th Order Interactions, which are typically
not important, are ignored.
• No replications were performed since the output results (thermal
resistance) were obtained using computer simulation, which
means subsequent replications would yield identical results.
• Center points were not included as part of this study. • An
Analysis of Variance
(ANOVA) of the significant factors was run to determine the
relative
importance of each factor to the overall PCB thermal resistance.
Icepak® CFD Model Assumptions:
• To reduce computation time while maintaining solution accuracy,
a ¼ symmetry thermal model was developed and executed
using Icepack CFD software. • Thermal resistance from a
power source, measuring 4mm x 6 mm (1/4 of this size
was sampled) on a Cu slug placed on top of
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PCB Thermal Via Optimization using DOE
the PCB, to the bottom of the board was calculated using
Icepack 4.1 CFD software. • A lower PCB thermal
resistance was desired.
• Total PCB thickness (including all 6 layers of Cu) is 62 mil. •
PCB raw material
(with no metalization) thermal conductivity value = 0.2 W/mK. •
The power source and Cu slug were placed directly
above the PCB thermal vias. • The entire via pad area size = 10
mm x 10 mm (1/4 of this area was modeled). •
Total Power = 1.0 Watt (1/4 Symmetry assumed, therefore, only
applied 0.25 Watt to the power source for this
model). • Obtained the difference in temperature from top to
bottom of PCB and divided by the total power of 1.0 Watt,
and then determined thermal Resistance.
• Modes of Heat Transfer = Conduction only; therefore, solved
only for the energy balance equation.
• Interested in determining steady-state temperature values. •
Ambient Temperature was
set to 0 oC.
• PCB inner metalized layers of Cu are in contact with the thermal
via barrels.
• Thermal via barrels are assumed to be Cu
material. material.
• For model mesh simplicity, the thermal vias were modeled as
prismatic objects. • Thermal vias are assumed
to be 100% filled with air. • Assumed the middle Cu layers of the
PCB
are 2.8 mil in thickness.
PCB Cross Section
PITCH
TOP_CU BARREL THICKNESS
LAYERS
THERMAL
THERMAL
VIA
VIA
DIAM
Figure 1: Cross section normal view to PCB stack, showing thermal
via, via Diameter, Pitch, Barrel Thickness as well as PCB Top Cu Pad
thickness and Number of Cu Layers. This sketch is not drawn to scale.
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PCB Thermal Via Optimization using DOE

and TOP_CU were found to be significant with 90% confidence. The 2-

way interactions and main factor, DIAM, were not significant to the
overall thermal resistance.

Once the significant factors have been determined, an

Analysis of Variance (ANOVA) of these factors is run
using MINITABTM software's General Linear Model
(GLM) tool to determine the relative significance of each
factor to PCB thermal resistance.

ANOVA

Figure 2: Icepak® ¼ Symmetry Isometric view of model Factor Type Levels Values
showing temperature gradient from source thru PCB as PITCH fixed 2 25.35
well as thermal via configuration. BARREL fixed 2 1, 1.4
LAYERS fixed 2 forty six

RESULTS & DISCUSSION TOP_CU fixed 2 2, 2.5

Analysis of Variance for Thermal Resistance (C/W)

Source DF Seq SS
PITCH first 0.4489
BARREL first 0.44223
LAYERS 0.2304
TOP_CU 11 0.0576
Error 11 0.13467
Total 15 1.3138

R-Sq = 89.75%
Table 3: ANOVA Results

Looking at the Sequential Sum of Squares (Seq SS)

from Table 3, the relative sensitivity of each of the
parameters can be determined.
Table 2: DOE Trials & Results.
Pitch = (0.4489/1.3138) x 100% = 34.2%
barrel = (0.44223/1.3138) x 100% = 33.7%
Pareto Chart of the Effects layers = (0.2304/1.3138) x 100% = 17.5%
(response is Thermal Resistance (C/W), Alpha = .10)
Top_Cu = (0.0576/1.3138) x 100% = 4.4%
0.1171
B Factor
A
Name
DIAM
Error = (0.13467/1.3138) x 100% = 10.2%
D
B PITCH
E C TOP_CU
C D BARREL

BD E LAYERS The Error term is the variation that is not explained by

BC
CD the model.
Term AB
AE
BEIGE

CE The R-square (R-sq) term indicates that the 4 main

AD
DE factors: PITCH, BARREL, LAYERS, TOP_CU
AC
A explain 89.75% of the variation in the PCB thermal
0.00 0.05 0.10 0.15 0.20 Effect 0.25 0.30 0.35 resistance output. Note the Error term is not
Lenth's PSE = 0.058125 included in the R-sq value.
Figure 3: Pareto Chart showing Significant Effects.

Figure 3 shows an example of a Pareto Chart. The

following main factors: PITCH, BARREL, LAYERS,

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PCB Thermal Via Optimization using DOE

Normal Probability Plot of the Effects Interaction Plot (data means) for Thermal Resistance (C/W)
(response is Thermal Resistance (C/W), Alpha = .10) 25 35 2 2.5 first 1.4 4 6
99
2.4
DIAM
Effect Type
14
Not Significant 2.2
B DIAM 16
95 Significant
2.0
90 Factor Name
A DIAM PITCH
2.4
80 B PITCH 25
C 2.2
70 TOP_CU PITCH 35
60 D BARREL 2.0
E LAYERS
50
40 2.4 TOP_CU
Percent 2
30 2.2
TOP_CU 2.5
20
C 2.0

ten E
2.4
BARREL
5 D first

2.2
BARREL 1.4
2.0
first

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4

Effect
LAYERS
Lenth's PSE = 0.058125

Figure 4: Normal Probability Plot of the Effects, showing

Figure 6: Interaction Plot. If lines are parallel, there is no
Factors – Pitch, Barrel Thickness, Number of Inner Layers
interaction. If lines are not parallel, then interaction is
Cu, and Top Cu Pad Thickness – were Significant.
present.

DIAM PITCH TOP_CU BARREL LAYERS

Optimal
Hi 16.0 35.0 2.50 1.40 6.0
Figure 4 indicates that the thermal via Pitch is significant D
Lo 0.83846
Cur [14.0]
14.0
[25.0]
25.0
[2.50]
2.0
[1.40]
1.0
[6.0]
4.0

and has a positive effect on the thermal resistance, as the Thermal

pitch increases, the output thermal resistance will increase, Minimum

y = 1.7100
which is not desirable. d = 0.83846

Figure 4 also shows that via Barrel thickness, Number of

PCB inner Cu Layers, and Top Cu Pad thickness are
significant and have a negative effect on the thermal
resistance, which means that as these factors increase,
the PCB thermal resistance will decrease, which is
desirable.

Main Effects Plot (data means) for Thermal Resistance (C/W)

DIAM PITCH TOP_CU Figure 7: Optimizer Chart was set to minimize the thermal
2.3

resistance, with a target value of 1.5 oC/W,

2.2
and an upper boundary of 2.8 oC/W.
2.1

2.0
The d in the y-axis of the optimizer chart is the level of
14
BARREL
16 25
LAYERS
35 2 2.5
desirability. This desirability value is between zero (low)
2.3
and one (high). For this study, the desirability value was
2.2
0.838, resulting in the lowest thermal resistance output
2.1
Mean
value of 1.71 oC/W.
2.0 The optimization performed for this analysis was linear
first 1.4 4 6 (analyzed at 2 end points for each factor). This study
could be taken one step further to include center-points
Figure 5: Main Effects Plot Figure
for each of the factors, allowing one to determine the
5 shows a main effects plot. A more extreme slope indicates a more
optimal point on a non-linear curve (Response Surface
significant effect on PCB thermal resistance. Note the thermal via
Diameter factor has a horizontal slope; Therefore, it is not as Methodology).
Figure 8 is a cube plot showing PCB thermal resistance values as a
significant.
function of the various factors.
The lowest thermal resistance value of 1.71 oC/W
Figure 5, also, shows the effect on PCB thermal resistance
occurs with a 14mil via Diameter on a 25mil Pitch, with
for each factor at the corresponding high
& low levels. 2.5mil top Cu Pad thickness, with a via Barrel thickness
of 1.4mil, and a 6 layer Cu thick PCB.
Figure 8, is a good representation of a fractional factorial,
where all corners of the Cube Plot do not

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PCB Thermal Via Optimization using DOE

have output trial results. A full factorial would have output
results on all corners of the Cube Plot.
CONCLUSIONS
This study demonstrates how to use MINITABTM
statistical software to perform a DOE study to optimize a
PCB normal direction thermal resistance.
The study indicates that in order to achieve a desired lower
PCB thermal resistance, the design engineer needs to:
REFERENCES
[1] T. Stewart and DW Stiver, “Thermal Optimization of
Electronic Systems using Design of Experiments Based on
Numerical Inputs”, presented at the 20th IEEE SEMI-
THERM Symposium, 2004.
[2] A. Zargari and W.R. Grise, “A Comparison of Traditional Methods
of Setting-Up the Experiments with the Utilization of Computer-
Based DOE Software: Validation of a Scientific Experiment”,
Electrical Insulation Conference & Electrical Manufacturing & Coil
Winding Conference, 1999.

1) Decrease thermal via pitch size. [3] BA Zahn, “Steady State Thermal Characterization and
2) Increase via Cu barrel thickness. Junction Temperature Estimation of Multi-Chip Module
3) Increase number of PCB metalized Cu layers. Packages Using the Response Surface Method”, IEEE
Transactions on Components & Packaging Technologies,
Vol. 23, No. 1, March 2000.
Using ANOVA methodology, the relative sensitivity of PCB
thermal resistance to each of these significant parameters [4] DC Montgomery, Design & Analysis of Experiments.
was determined. New York: John Wiley & Sons, Inc.,
The design engineer, early in the program, can work with 2001.
PCB suppliers to achieve a balance between thermal [5] FP Incropera and DP DeWitt, Fundamentals of Heat
performance, PCB cost, and supplier capability. and Mass Transfer. New York: John Wiley & Sons, Inc.,
1996.
This methodology can be used to optimize any similar [6] B. Ryan and BL Joiner, MINITABTM Handbook,
system. 4th Edition. Pacific Grove, CA: Duxbury, Thomson Learning,
2001.
[7] Icepak® 4.1 Users Guide. Fluent© Inc, 2005.

Cube Plot (data means) for Thermal Resistance (C/W)

2.38 1.81

2.35 2.12

1.99 1.71

1.95 1.81
6

LA YERS
2.58 2.03
4

2.79 2.36
35

PITCH 2.16 1.94

2.5
TO P_C U
2.21 1.97
25 2

14 16
DIAM
first 1.4
BARREL

Figure 8: Cube Plot

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