AN5165K

ICs for TV
AN5165K
A Single Chip IC for NTSC Color-TV
■ Overview Unit: mm
The AN5165K is an IC in which all of the NTSC
0.5±0.1
1.0±0.25
1 52
system color television signal processing circuits are in-
tegrated on a single chip. The rationalization of set pro-
ue e/
duction line can be realized by this IC incorporating I2C
1.778
bus interface.
47.7±0.3
tin nc
■ Features
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• Built-in video IF circuit, sound IF circuit, video signal
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processing circuit, color signal processing circuit, de-
flection correction circuit and sync. signal processing
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13.7±0.3 (0.7)
• Built-in I2C bus interface
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3.85±0.3 (3.3)
+0.2
ct
0.25 -0.05
■ Applications
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3° to 15° (15.24)
mi UR ue ued pe pe Pro
• TVs SDIP052-P-0600A
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Note) The package of this product will be changed

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to lead-free type (SDIP052-P-0600F). See the
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new package dimensions section later of this

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Publication date: December 2001 SDB00001BEB 1

2
M AN5165K
V Out1
CW Out
H Out
X-ray
HOSC
AFC1
6.3 V
FBP In
VCJ GND
C In
V/C/J/5 V
H Sync.
V Clamp
V Sync. Y In
BLDET
IF 9 V
VCO2
VCO1
APC
DET Out
Int.V
AFT Out
Video Out
IF AGC
SIF In
Ext.Audio
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■ Block Diagram
to Video
S.SW Hor. DC
CV Clamp
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HVCO HBLK Sync. Sep.
SW HBLK
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DAC 4-bit
Ver. Out X-ray VAMP VSW
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SIF
H.EQP VCO
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SW
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32fH AFC1 Lock DET /D Ver.
Sync. Sep. VCO V SW
Hosc1
Ver. 2fH DL Trap CTRL VA
H Pluse PT
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CountDown SW
Hor. Hosc2 RAMP
on
H Out1
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CountDown AFC2
VBLK H Out2
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CCP (Hosc4) B.G.P
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Trig1 SW
to Video Trig2 APC NI IF
RGB 3-bit L.P.F. AGC PLL
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A Trig
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P.EQP H Center DAC
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Sharpness
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to Chroma Y.N.R
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DAC 5-bit
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SW DAC
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ACC1 On/Off SW7-bit 6-bit AFT DEMP
ACC DET
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B.P.F.1
Killer Off SW SW DAC DAC
Y Contrast
SDB00001BEB
BPF SW 9-bit 5-bit
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SW ACC2 IF
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SW DET
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Killer B.P.F.2 DAC
ABL SW
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L.P.F. VOL
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CW Out Contrast Y Clamp
Bright
DAC
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Color DAC 8-bit
DC DAC 7-bit
7-bit Black
VIF RF ASW
Tint Expamsion Amp. AGC
DEM C Filter
DAC
APC 8-bit 7-bit
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7-bit
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Cut Off Drive RGB Limit γ
Gain Control 3-bit
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DAC DAC
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d SW γ On/Off SW
Cut off DAC
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VCO YS&YM as lat
Cut Off B SW
SW
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d Drive
Cut Off R SW
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R
B
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9V
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R In
B In
G In
SCL
APC
APC
SDA
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18 IF 5 V
YS&YM
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GND (IF)
V/C/J 9 V
Ext.Video
.
Lock DET
Audio Out
Decoupling
ACL/NECK
GND (RGB)
RF AGC Out
Chroma VCO
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BLK In (SCP)
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AN5165K
■ Pin Description
Pin No. Description Pin No. Description
1 Chroma VCO (3.58 MHz) 28 SIF Input/White Expand-Level
2 Chroma APC Filter 29 IF AGC Filter
3 YS & YM Input 30 Video Output
4 External R Input 31 AFT Output
5 External G Input 32 Internal Video Input
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6 External B Input 33 VIF Detect Output
7 VCC1-1 9 V (VCJ) 34 VIF APC Filter
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8 R Output 35 VIF VCO (1)
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9 G Output 36 VIF VCO (2)
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10 B Output 37 VCC1-2 9 V
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11 Hor. Lock Detect 38 Black Detect
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12 GND (RGB/I2C/ DAC) 39 Y/Ver. Sync. Input
ct
13 ACL/NECK Protect 40 Ver. Sync. Clamp
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14 SDA 41 Hor. Sync. Input
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15 SCL 42 VCC2-2 5 V (Chroma/jungle/DAC)

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16 BLK Pulse Input/HSYNC2 Output 43 Chroma Input/Black Expansion Start
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17 White Detect 44 GND (Video/Chroma/Jungle)
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18 VCC2-1 5 V (VIF/SIF) 45 FBP Inputd
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19 VIF Input (1) 46 VCC3 6.2 V
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20 VIF Input (2) 47 ic. t in

AFC1 Filter
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21 GND (VIF/SIF) 48 Hor. VCO (32 fH)
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22 RF AGC Output 49 X-ray Protection Input

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23 SIF APC Filter 50 Hor. Pulse Output

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24 Audio Output 51 CW Output/Spot KILLER Off Input/

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X-ray Protection Output

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25 External Video Input

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26 DC Decoupling Filter 52 Ver. Pulse Output

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27 External Audio Input

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■ Absolute Maximum Ratings

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Parameter Symbol Rating Unit

Supply voltage VCC VCC1 (7·37) 10.5 V
VCC2 (18·42) 6.0
VCC3 (46) 6.5
Supply current ICC I7+37 117 mA
I18+42 68
I46 6.3
SDB00001BEB 3
AN5165K
■ Absolute Maximum Ratings (continued)

Parameter Symbol Rating Unit
Power dissipation *2 PD 1 481 mW
Operating ambient temperature *1 Topr −20 to +70 °C
Storage temperature *1 Tstg −55 to +150 °C
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
*2: The power dissipation shown is the value for Ta = 70°C
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■ Recommended Operating Range
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Parameter Symbol Range Unit
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Supply voltage VCC1 8.1 to 9.9 V
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VCC2 4.5 to 5.5
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VCC3 6.05 to 6.35
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■ Electrical Characteristics at Ta = 25°C
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Parameter Symbol Conditions Min Typ Max Unit
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Power supply .se ng ntin tin ty e ty ur

Current at V7 = 9 V, current at
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Supply current 1 I7+I37 68 85 100.5 mA
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V37 = 9 V
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Supply current 2 I18+I42 Current at V18 = 5 V, current at 38 48 57 mA
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V42 = 5 V
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Supply current 3 I46

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Current, when V46 = 6.2 V 2 5 6 mA
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Supply current 4 I46 Current at V46 = 6.2 V. However 5 7 9 mA

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all other power supplies are off state

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VIF circuit (Typical input fP = 45.75 MHz, VIN = 90 dBµ)

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Video detection output (typ.) VPO Modulation factor m = 87.5% 1.75 2.1 2.5 V[p-p]
isc
Data 0D = 88
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Video detection output (max.) VPOmax Data 0D = F8 2.15 2.6 3.3 V[p-p]
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Video detection output (min.) VPOmin Data 0D = 08 1.1 1.6 2.0 V[p-p]
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Video detection output f characteristics fPC Frequency of output −3 dB for 1 MHz 5.5 8 12 MHz
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Synchronous peak value voltage VSP Voltage in VPO measurement 1.6 2.0 2.4 V
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APC pull-in range (Hu) fPPHU High band side pull-in range 1.0 1.5  MHz
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(Difference from fP = 45.75 MHz)

APC pull-in range (Lu) fPPLU Low band side pull-in range  −1.5 −1.0 MHz
RF AGC delay point adjustment DVRFDP Input to become delay point 75  95 dBm
range (V22 = approx. 6.5 V), when Data
0C = 00 to 7F
RF AGC maximum sink current IRFmax Maximum current IC can sink when 1.5 3.0  mA
pin 22 is low
4 SDB00001BEB
AN5165K
■ Electrical Characteristics at Ta = 25°C (continued)

VIF Circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
RF AGC minimum sink current IRFmin Leak current of IC, when pin 22 is −50 0 50 mA
high
AFT discrimination sensitivity µAFT Df = ±25 kHz 40 57 75 mV/kHz
AFT center voltage VAFT V31 without VIN 4.0 4.5 5.0 V
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AFT maximum output voltage VAFTmax V31 at f = fP−500 kHz 7.8 8.1 8.7 V
AFT minimum output voltage VAFTmin V31 at f = fP+500 kHz 0.3 0.8 1.0 V
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SIF circuit (Typical input fS = 4.5 MHz, fM = 400 Hz, VIN = 90 dBµ)
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Audio detection output VSO Df = ±25 kHz, 0A = 10 250 350 450 mV[rms]
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Audio detection output (max.) VSOmax Data 0A = 1F 300 390 480 mV[rms]
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Audio detection output (min.) VSOmin Data 0A = 00 150 256 350 mV[rms]
life
SIF pull-in range fSP 3.3  5.7 MHz
ct
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AV SW circuit
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Video SW voltage gain GVSW f = 1 MHz, VIN = 1 V[p-p]

.se ng ntin tin ty e ty ur 6.2 7.2 8.2 dB
Video SW frequency characteristics fVSW Frequency of output −3 dB from 1 MHz 10   MHz
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Data 0 F−D5 = 1 (external) −3 −1

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Audio SW voltage gain GASW 1 dB
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f = 400 Hz, VIN = 1 V[p-p]
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Video signal processing circuit (In the following test conditions, the measurements are made withinput: 2.0 V[p-p]
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(VWB = 1.43 V[0-p]stair-step) at GOUT.)

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Video output (typ.) VYO Data 03 = 40 (typ.) (Contrast) 1.9 2.4 2.9 V[0-p]
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Video output (max.) VYOmax Data 03 = 7 F (max.) 3.8 4.8 5.8 V[0-p]
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Video output (min.) VYOmin Data 03 = 00 (min.) 0.07 0.3 0.6 V[0-p]
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Contrast variable range YCmax/min 03 = 7F 19 22 26 dB

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03 = 00
/D
Video frequency characteristics fYC Data 0F−D7 = 0 (Trap Off) 6.0 8.0 10.0 MHz
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Data 04 = 00 (Sharpness)
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Frequency to become −3 dB from

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Sharpness variable range YSmax/min 04 = 3F f = 3.8 MHz 7 10.5 14 dB

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04 = 00 Data 0F − D7 = 0
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Pedestal level (typical) VPED Data 02 = 80 (typ.) (Brightness) 2.4 3.0 3.6 V
Pedestal variable width ∆VPED Difference between Data 02 = 00 2.2 2.6 3.0 V
and FF
Brightness control sensitivity ∆VBRT Average amount of change per 1 step, 9.5 12.5 15.5 mV/Step
when Data 02 = 60 and A0
ACL sensitivity ACL Change of YOUT from V13 = 3.0 V to 3.5 V 2.3 2.9 3.6 V/V
Blanking level VYBL DC voltage of blanking pulse 0.9 1.4 1.9 V
SDB00001BEB 5
AN5165K

Video signal processing circuit (continued) (In the following test conditions, the measurements are made with
input: 2.0 V[p-p] (VWB = 1.43 V[0-p] stair-step) at GOUT.)
Video input clamp current IYCLP DC measurement: Sink current inside IC 5 10 15 µA
ACL start point VACL V13 voltage at which output amplitude 3.5 4.0 4.5 V
becomes 90% when ACL pin (V13)
ue e/
is being decreased from 5 V.
Color signal processing circuit (In the following test conditions, burst = 300 mV[p-p], reference is BOUT)
Color difference output (typ.) VCO Input: Color bar 2.8 3.5 4.2 V[p-p]
tin nc Data 00 = 40 (typ.), 03 = 40 (typ.)
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Data 00 = 7 F one side amplitude 
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Color difference output (max.) VCOmax 2.3 3.4 V[0-p]
Data 03 = 40
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Data 00 = 00, Data 03 = 40 
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Color difference output (min.) VCOmin 0 100 mV[p-p]
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Contrast variable range CCmax/min 03 = FF Data 00 = 40 15 20 25 dB
ct
03 = 00
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ACC characteristics 1 ACC1 Burst 300 mV[p-p]→600 mV[p-p] 0.8 1.0 1.2 Time
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Input: Color bar

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ACC characteristics 2 ACC2 Burst 300 mV[p-p]→60 mV[p-p] 0.7 1.0 1.2 Time
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Input: Color bar
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∆θC Difference (Tint) between Data 01 = 40 −13
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Tint center d 0 13 STEP
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Tint variable range 1 ∆θ1 Data 01 = 7F

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∆θ2 Data 01 = 00 −60 −45 −30

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Tint variable range 2 deg

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Demodulation output ratio (R) R/B Input: Rainbow 0.81 0.95 1.09 Time
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Demodulation output ratio (G) G/B Input: Rainbow 0.3 0.36 0.42 Time
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Demodulation output angle (R) ∠R Input: Rainbow 92 104 116 deg

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/D
Demodulation output angle (G) ∠G Input: Rainbow 223 235 237 deg
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APC pull-in range (H) fCPH 450 900  Hz

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APC pull-in range (L) fCPL  −900 −450 Hz

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RGB processing circuit

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Pedestal difference voltage ∆VIPL Difference voltage of RGB out pedestal − 0.3  0.3 V
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Brightness voltage tracking ∆TBL Ratio of R, G, B out fluctuation level 0.9 1.0 1.1 Time
for Data 02 (Bright) 02 = 40 to C0
Video voltage gain relative ratio ∆GYC Output ratio of R, B out to GOUT 0.8 1.0 1.2 Time
Video voltage gain tracking ∆TCONT Gain ratio of R, G, B out for Data 0.9 1.0 1.1 Time/
03 (Contrast) 03 = 20 to 60 Time
Drive adjustment range GDV AC change amount of R, B out between 5.9 7.1 8.3 dB
drive adjustment max. and min.
6 SDB00001BEB
AN5165K

RGB processing circuit (continued)
Cutoff adjustment range VCUTOFF DC change amount of R, G, B out 1.8 2.4 3.0 V
between drive adjustment max. and min.
YS threshold voltage VYS Minimum DC voltage at which YS 2.7 3.1 3.6 V
turns on
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YM threshold voltage VYM Minimum DC voltage at which YM 0.7 1.0 1.3 V
turns on
YM operating voltage gain ∆GYM YM on/off gain difference −12 −9 −6 dB
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External RGB pedestal voltage VEPL YS is on 2.1 2.7 3.3 V
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External RGB pedestal difference ∆VEPL YS is on, R−G, G−B −250  250 mV
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voltage
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Internal/external pedestal difference ∆VPL/IE Internal−external −100 200 500 mV
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voltage
ct
Input 3 V[p-p], contrast 03 =7 F
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External RGB output voltage VERGB 1.2 1.7 2.2 V[0-p]
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External RGB output difference ∆VERGB Input 3 V[p-p], contrast 03 = 7F − 0.6 0 0.6 V
voltage
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External RGB contrast variable range ECmax/min 03 = 7F 5 8 11 dB
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03 = 00
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Input 0.2 V[p-p], DC = 1 V d 
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External RGB frequency characteristics fRGBC 8 12 MHz
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Synchronizing signal processing circuit

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Horizontal free-running oscillation fHO Without sync. signal input 15.4 15.75 16 kHz
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frequency
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Difference from fH = 15.75 kHz ±500 ±650 

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Horizontal pull-in range fHP Hz

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Vertical free-running oscillation fVO-N Without sync. signal input 58 60 62 Hz

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frequency
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Vertical output pulse width τVO 5.5 6.5 7.5 1/fH

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Picture center variable range ∆THC Change amount of phase difference 5.9 7.3 9.1 µs
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0E: 00 to 1F
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I2C interface
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SCL, SDA signal input high level VIHI 3.1  5.0 V

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SCL, SDA signal input low level VILO 0  0.9 V

Allowable maximum input frequency fImax 100   kbit/s
• Design reference data

Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
VIF Circuit (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
Input sensitivity VPS Input level to become VPO = −3 dB  52 60 dBµ
SDB00001BEB 7
AN5165K

• Design reference data (continued)
VIF circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
Maximum allowable input VPmax Input level to become VPO = +1 dB 104 110  dBµ
SN ratio SNP 50 53  dB
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Differential gain DGP 0 3 5 %
Differential phase DPP 0 3 5 deg
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Black noise detection level ∆VBN Difference from sync. peak value −55 −45 −35 IRE
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Black noise clamp level ∆VBNC Difference from sync. peak value 35 45 55 IRE
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RF AGC operation sensitivity GRF Input level difference to become 0.5 1.5 3.0 dB
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V22 = 1 V→7 V
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∆fPD  
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VCO switch on drift Frequency drift from 5 seconds 70 kHz
after SW On to 5 mins. after
ct
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Intermodulation IM VFC−VFP = −2 dB, VFS−VFP = −12 dB 46 52  dB
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RF AGC adjustment sensitivity SRF Average amount of change of output

.se ng ntin tin ty e ty ur 1.0 1.7 2.5 V/Step
voltage V22 for Data 1Step
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AFT offset adjustment sensitivity SAFT Average amount of change of output 0.15 0.2 0.25 V/Step
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voltage V31 for Data 1Step
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Video detection output fluctuation ∆VP/V VCC = ±10%  ±10 ±15 %
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Video detection output-temperature ∆VP/T Ta = −20°C to +70°C  ±5 ±10 %

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characteristics
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Input resistance (pin 19, 20) RI19,20 f = 45.75 MHz  1.2  kΩ

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Input capacitance (pin 19, 20) CI19,20 f = 45.75 MHz  4.0  pF

on
isc
Sound IF output level VSIF fS = 45.75 MHz−4.50 MHz, 94 100 106 dBm
/D
P/S = 20 dB
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VCO control sensitivity 1 βPU DV34 = 2.0 V−3.8 V, f = 45.75 MHz 1.3 2.2 3.1 kHz/mV
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VCO control sensitivity 2 βPJ DV34 = 2.0 V−3.8 V, f = 58.75 MHz 1.3 2.2 3.1 kHz/mV
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∆VDP/T Ta = −20°C to +70°C

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RF AGC delay point 0 3 5 dB

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-temperature characteristics
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VCO free-running frequency ∆fP/T Ta = −20°C to +70°C  300  kHz

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AFT center frequency ∆fAFT/T Ta = −20°C to +70°C  300  kHz
-temperature characteristics Input frequency at which AFT output
voltage becomes 4.5 V
VCO free-run adjustment VAFTADJ AFT center voltage adjustment  4.5  V
VCO free-running frequency 1 ∆fP1 Dispersion without VIN. −300 0 300 kHz
V29 (IF AGC) = 0 V (Difference
from 45.75 MHz is measured)
8 SDB00001BEB
AN5165K

VIF circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBµ)
VCO free-running frequency 2 ∆fP2 Dispersion without VIN. −300 0 300 kHz
V29 (IF AGC) = 0 V (Difference
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from 58.75 MHz is measured)
APC pull-in range (Hj) fPPHJ High band side pull-in range 1.0 1.5  MHz
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APC pull-in range (Lj) fPPLJ Low band side pull-in range  −1.5 −1.0 MHz
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Detection output resistance RO33 DC measurement 70 120 170 Ω
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SIF circuit (Typical input fS = 4.5 MHz, fM = 400 Hz, VIN = 90 dBµ)
cy
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Input limiting level VLIM Input level to become VSOP = −3 dB  44 50 dBµ
ct
AM rejection ratio AMR AM = 30% 60 70  dB
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Df = ±50 kHz
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Total harmonic distortion THD 0 0.3 0.5 %


SN ratio SNA
.se ng ntin tin ty e ty ur 50 55 dB
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Audio detection output linearity ∆VSOP Ratio of ∆f = ±50 kHz to 5 6 7 dB
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∆f = ±25 kHz
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∆VS/V VCC = ±10%  ±3 ±6
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Audio output fluctuation with VCC %

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∆VS/T Ta = −20°C to +70°C  ±5 ±10

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Audio output-temperature %
characteristics
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Audio output-frequency fSOP1 APC pin C = 100 pF 100   kHz

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characteristics 1
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APC pin C = 5600 pF  

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Audio output-frequency fSOP2 2.2 kHz

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characteristics 2
isc
AV SW circuit
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Video SW crosstalk CTVSW f = 1 MHz, VIN = 1 V[p-p],  −60 −50 dB

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Video SW external input terminal V25 DC measurement 1.3 1.6 1.9 V

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voltage
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Video SW internal input terminal V32 DC measurement 1.3 1.6 1.9 V

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voltage
Video SW internal output DC voltage V30I DC measurement Data 04−D6 = 0 3.4 4.2 5.0 V
Video SW external output DC voltage V30E DC measurement Data 0F−D5 = 1 3.4 4.2 5.0 V
Video SW input resistance RI25, 32 DC measurement  524  Ω
Video SW output resistance RO30 DC measurement 20 50 100 Ω
SDB00001BEB 9
AN5165K

AV SW circuit (continued)
Audio SW crosstalk CTAIE fS = 4.5 MHz, fM = 400 Hz,  −73 −67 dB
(Internal→External) No external input
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Audio SW crosstalk CTAEI fS = 4.5 MHz, fM = 0 Hz, External  −73 −67 dB
(External→Internal) f = 400 Hz, VIN = 600 mV[rms]
Audio SW input terminal voltage V27 DC measurement 3.7 4.2 4.7 V
tin nc
d
Audio SW internal output DC voltage V24I DC measurement 3.7 4.2 4.7 V
.
ge
sta
Audio SW external output DC voltage V24E DC measurement 3.7 4.2 4.7 V
∆V24 −300
cle
Audio SW internal/external DC DC measurement 0 300 mV
on na
cy
difference voltage
life
Audio SW input resistance RI27 DC measurement 61 72 83 kΩ
ct
Ω
du
Audio SW output resistance RO24 DC measurement 200 400 600
sc te
Video signal processing circuit (In the following test conditions, the measurements are made with input 2.0 V[p-p]
(VWB = 1.43 V[0-p]) GOUT)
ww wi co on ce c fo
Y signal delay time 1 TDL1 Phase difference from Y-input 620 690 760 ns
n.
Di ain
o
(For both trap on/off)
i
/en at
d te t o
.jp rm
 
ne ain ain foll
Y signal delay time 2 TDL2 Phase difference from Y-input 200 ns

n.p bo yp pe
co fo
(Trap through)
/
co L a d t ty
pla m d m des
Black level extension 1 VBL1 ic. t in

Input: Total black, difference between −100 0 100 mV
on es
an ut e
lan nclu
M
pin 38 of 9 V and open (With RC filter)

as lat
di
e
Black level extension 2 VBL2 Input: Total black, pin 38 GND and 700 900 1 300 mV
ue
black slice potential V43 = 2.5 V

tin
p
on
Black level extension 3 VBL3 Voltage difference between pin 38 400 600 800 mV
isc
open and 9V. Black slice potential

/D
V43 = 2.5 V
ce
an
Contrast variation with sharpness DVCS YOUT output level difference between −300 0 300 mV
p:/ fo
en
sharpness max. and min.

htt visit
int
Contrast variation with sharpness DVBS Pedestal level DC difference between −250 0 250 mV
Ma
se
sharpness max. and min.

ea
Input dynamic range VImax Contrast 03 = 40 2.8   V[p-p]

Pl
Y signal SN ratio SNY Contrast 03 = 7F 51 56  dB

Black level extension start point VBLS Start point when V43 = 4.5 V 50 57 64 IRE
Trap on/off through-gain difference DGTRAP Trap on/off/through −1 0 1 dB
Trap frequency error DfTRAP Trap center frequency at chroma −70 0 70 kHz
input 3.58 MHz
Trap attenuation amount AttTRAP 3.58 MHz component attenuation 26 30  dB
amount at chroma input 3.58 MHz
10 SDB00001BEB
AN5165K

Video Signal Processing Circuit (continued) (In the following test conditions, the measurements are made with
input 2.0 V[p-p] (VWB = 1.43 V[0-p]) GOUT)
Trap automatic adjustment range fTRAP VCO frequency of ∆fTRAP ≤ 70 kHz 3  4 MHz
ue e/
Video output fluctuation with VCC ∆VY/V VCC1 = 9 V (allowance: ±10%) 0 100 250 mV/V
Video output-temperature characteristics ∆VY/T Ta = −20°C to +70°C 0 5 10 %
YNR operation I SNYNR S/N, when YNR: min.→max. and  −4  dB
tin nc sharpness max.
d
.
ge
 −1.5 
sta
YNR operation II SNYNR Sharpness max., YNR: max. dB
(IFAGC) S/N at IF AGC 2 V→4 V
cle
on na
01−D7 = 1, when V13 = 1.5 V→3.5 V
cy
ABL sensitivity ABL 0.3 0.5 0.7 V/V
life
Pedestal level fluctuation
ct
White gradation correction 1 γ1 White detection pin V17 = 4.5 V 120 125 130 %
du
Difference of amplitude between
sc te
GOUT gamma on/off

γ2 White detection pin V17 = 2.0 V
ww wi co on ce c fo
White gradation correction 2 70 75 80 %
n.
Difference of amplitude between

Di ain
i o
GOUT gamma on/off
/en at
d te t o
.jp rm
ne ain ain foll
n.p bo yp pe
Neck protector threshold voltage VNP 0.3 0.5 1.0 V
co fo
/
co L a d t ty
pla m d m des
DC restoration ratio TDC APL 10% to 90%

ic. t in 90 100 110 %
on es
∆AC−∆DC
an ut e
lan nclu
TDC = × 100
M
as lat
∆AC
di
e
ue
Color signal processing circuit (Burst 300 mV[p-p], reference is BOUT)

tin
p
Demodulation output residual carrier VCAR fSC level of pin 8, 9, 10 0  50 mV[p-p]

on
isc
VCO free running frequency fCN Difference from f = 3.579545 MHz −300 0 300 Hz
/D
fCO fluctuation with VCC ∆VC/V VCC1 = 9 V (allowance: ±10%) −300 0 300 Hz
ce
an
Static phase error ∆θN Tint shift at  1 3 deg/100 Hz

p:/ fo
en
∆fC = −300 to +300 Hz change

htt visit
int
Band to become −3 dB
Ma
Demodulation output bandwidth fCC 400 600 800 kHz

se
Demodulation output fluctuation ∆VC/V VCC1 = 9 V (allowance: ±10%)  ±4  %

ea
with VCC
Pl
Demodulation output ∆VC/T Ta = −20°C to +70°C  ±10 ±20 %

Brightness variation with color VBC Pedestal level DC difference between −250 0 250 mV
color max. and min.
Brightness variation difference ∆VBC R, G, B Out variation voltage 0  20 mV
voltage with color difference
SDB00001BEB 11
AN5165K

Color signal processing circuit (continued) (Burst 300 mV[p-p], reference is BOUT)
Color killer allowance 1 VKILL1 0 dB = 300 mV[p-p], 00−D7 = 0 −53 −46 −39 dB
Color killer allowance 2 VKILL2 0 dB = 300 mV[p-p], 00−D7 = 1 −50 −43 −36 dB
ue e/
CW output level (3.58 MHz) VCW AC component of (3.58 MHz) 0.6 1.1 1.4 V[p-p]
B.P.F. (Symmetrical) frequency fB.P.F. Band to become 400 600 800 kHz
characteristics −3 dB from 3.58 MHz
tin nc
d
.
Slant of 3.58 MHz ±500 kHz  
ge
B.P.F. (Asymmetrical) slant VB.P.F./f 9.0 dB/MHz
sta
RGB processing circuit
cle
(C−Y)/Y RC/Y Color bar input, BOUT 0.9 1.2 1.5 V[0-p]/
on na
cy
Contrast typ. color Data 00 = 60 V[p-p]
life
(C−Y), Y delay difference ∆TC/Y Color bar input, BOUT −100 0 100 ns
ct
du
Phase of green→magenta
sc te
YS changeover speed fYS fYS, when external input is 3 V, 7 11  MHz

output level −3 dB
ww wi co on ce c fo
External RGB input dynamic range VDEXT Contrast max. Data 03 = 7F 6.5 7.0  V[0-p]
n.
Di ain
o
Leakage when f = 1 MHz, 1 V[p-p],  −60 −50
i
Internal/external crosstalk CTRGB dB
/en at
d te t o
.jp rm
YS = 5 V
ne ain ain foll
n.p bo yp pe
co fo
/
co L a d t ty
pla m d m des
Spot killer operation VSPK V9 at which spot killer turns on by 7.3 7.7 8.0 V
decreasing V9 from 9 Vic. t in
on es
an ut e
lan nclu
M
as lat
Brightness variation with contrast VBAC Pedestal level DC difference between −250 0 250 mV
di
e
contrast max. and min.

ue
tin
Brightness variation difference DVBAC R, G, B Out variation voltage 0  20 mV

p
on
voltage with contrast difference

isc
Color /B&W DC difference voltage DVCBW Pedestal level voltage difference −60 0 60 mV
/D
ce
between with and without burst signal

an
Pedestal level fluctuation with VCC DVPL/V VCC1 = 9 V (allowance: ±10%) 0 200 400 mV/V
p:/ fo
en
htt visit
Ta = −20°C to +70°C  − 0.6 

int
Pedestal level-temperature characteristics DVPL/T mV/°C

Ma
Pedestal level difference voltage DVPD/V VCC1 = 9 V (allowance: ±10%)  0  mV/V

se
ea
fluctuation with VCC R−G, B−G

Pl
External RGB output blanking voltage VBLK Burst input only 0.8 1.3 1.8 V
RGB limiter control range 1 VBEAM1 Input 2 V[p-p], contrast max. 6.4 6.7 7.0 V
RGB limiter 0E = 70
RGB limiter control range 2 VBEAM2 Input 2 V[p-p], contrast max. 5.6 6.0 6.4 V
RGB limiter 0E = F0
12 SDB00001BEB
AN5165K

Synchronizing signal processing circuit
Horizontal output start voltage VfHS Minimum V46, when H osc. output is 3.9 4.4 4.9 V
1 V[p-p] or more and fO becomes >10 kHz
ue e/
Lock detection output voltage 1 VLD1 V11, when horizontal AFC is locked 3.8 4.3 4.8 V
Lock detection output voltage 2 VLD2 V11, when horizontal AFC is unlocked. 0 0.1 0.5 V
Lock detection charge and discharge ILD DC measurement ±0.5 ±0.7 ±1.1 mA
tin nc
current
d
.
ge
sta
EBP (BLK) slice level VFBP Minimum voltage of pin 45, when 0.3 0.66 1.0 V
blanking is applied to RGB output
cle
on na
cy
EBP (AFC2) slice level VFBPH Minimum voltage of pin 45, when 1.45 1.85 2.25 V
life
AFC2 operates
ct
Horizontal AFC µ µH DC measurement 26 33 40 µA/µs
du
Horizontal VCO β βH β curve gradient near f = 15.75 kHz 1.4 1.8 2.2 Hz/mV
sc te
µs
Burst gate pulse position PBGP
Delay from HSYNC rise 0.2 0.4 0.6
ww wi co on ce c fo
Burst gate pulse width WBGPN 2.5 3.0 3.5 µs
n.
Di ain
o
Pulse width, when fH = 15.75 kHz
i
V blanking pulse width WVN 1.04 1.14 1.24 ms
/en at
d te t o
.jp rm
ne ain ain foll
n.p bo yp pe
EBP allowable range TFBP Time from HOUT rise to FBP center 12  19 µs
co fo
/
co L a d t ty
pla m d m des
Overvoltage protective operation VXRAY

ic. t in
Dispersion from the minimum voltage −60  60 mV
on es
an ut e
lan nclu
voltage at which H osc. comes to be out of

M
as lat
synchronization
di
e
ue
Black-out operation voltage VBLOUT Difference voltage from hold-down 10 110 160 mV
tin
to black out
p
on
HSYNC2 output level VSCP HSYNC2 output DC level 8.0 8.2 8.4 V
isc
/D
HSYNC2 output width WSCP HSYNC2 output pulse width  2  µs

ce
  µs
an
HSYNC2 output position PSCP The period of time from HSYNC 3

p:/ fo
en
center to HSYNC2 rise

htt visit
int
Horizontal output pulse duty cycle tHO Upward going pulse duty cycle 32 38 44 %
Ma
se
Horizontal output voltage (high) V50H High level DC voltage 2.8 3.1 3.4 V
ea

Pl
Horizontal output voltage (low) V50L Low level DC voltage 0 0.3 V

Vertical output voltage (high) V52H High level DC voltage 3.9 4.2 4.5 V
Vertical output voltage (low) V52L Low level DC voltage 0  0.3 V
Synchronizing signal clamp voltage (Ver.) V39 V39 clamp voltage 3.2 3.6 4.0 V
Synchronizing signal clamp voltage (Hor.) V41 V41 clamp voltage 3.2 3.6 4.0 V
External blanking input threshold level V16I 0.4 0.75 1.1 V
Vertical pull-in range fVP-N fH = 15.75 kHz 56  64 Hz
SDB00001BEB 13
AN5165K

I2C interface
Sink current when ACK IACK Maximum value of sink current 1.8 2.5 5.0 mA
for pin 14 at ACK
ue e/
Bus free before start tBUF 4.0   µs
Start condition set-up time tSU, STA 4.0   µs
Start condition hold time tHD, STA 4.0   µs
tin nc
d
.
  µs
ge
Low period SCL,SDA tLOW 4.0
sta
High period SCL tHIGH 4.0   µs
cle
Rise time SCL,SDA tR   1.0 µs
on na
cy
  µs
life
Fall time SCL,SDA tF 0.35
ct
Data set-up time(write) tSU, DAT 0.25   µs
du
  µs
Data hold time(write) tHD, DAT 0
sc te
Acknowledge set-up time tSU, ACK .se ng ntin tin ty e ty ur   3.5 µs

ww wi co on ce c fo
Acknowledge hold time tHD, ACK 0   µs
n.
Di ain
o
Stop condition set-up time tSU, STO 4.0   µs
i
/en at
d te t o
.jp rm
ne ain ain foll
n.p bo yp pe
DAC
co fo
/
co L a d t ty
pla m d m des
L3, 4, 5, 6, 7 1LSB = {Data (max.)−Data (00)}

ic. t in
3, 4, 5, 6, 7-bit DAC DNLE on es 0.1 1.0 1.9 LSB
an ut e
lan nclu
/7, 15, 31, 63, 127 Step

M
as lat
8-bit DAC DNLE L8 1LSB = {Data (FF)−Data (00)}/255 0.1 1.0 1.9 LSB
di
e
ue
Step
tin
p
Cut-Off DAC overlap DSTEP Overlap of 8-bit 2-stage changeover 27 32 37 Step

on
of R, B cut-off (Same for AFT)

isc
/D
ce
• Standard conditions when testing

an
1. Input signal
p:/ fo
en
: fP = 45.75 MHz, VIN = 90 dBµ, at video modulation: Modulation signal is 10-staircase

htt visit
1) VIF
int
Modulation m = 87.5%, pin 19 input level 84 dBµ when VIN = 90 dBµ

Ma
se
2) SIF : fS = 4.5 MHz, VIN = 90 dBµ, modulation signal fM = 400 Hz, deviation: NTSC ±25 kHz
ea
3) Video : 10-staircase 2 V[p-p] (VBW = 1.43 V[0-p])

Pl
4) Chroma : Color bar signal: Burst level 300 mV[p-p]

Rainbow signal : Burst level 300 mV[p-p]
5) Sync. signal: Video signal 1.5 V[p-p] to 2.5 V[p-p] for both horizontal and vertical sync. signal input
14 SDB00001BEB
AN5165K
• Standard conditions when testing (continued)
2. I2C BUS condition
Sub Address Data (H) Sub Address Data (H)
00 Color 40 08 Drive R 40
01 Tint 40 09 Drive B 40
02 Bright 80 0A Audio Adj, YNR 10
03 Contrast 40 0B AFT 10
ue e/
04 Sharpness 00 0C RFAGC 40
05 Cut-off R 80 0D Video Adj 08
06 Cut-off G 40 0E H center, RGB limiter 10
tin nc
07 Cut-off B 80
d
.
ge
sta
cle
on na
cy
life
■ Terminal Equivalent Circuits
ct
Pin No. Equivalent circuit Description I/O
du
1 Chroma oscillation pin (3.58 MHz) AC
sc te
100 Ω 3.58 MHz • Pin for chroma oscillation of 3.58 MHz.

.se ng ntin tin ty e ty ur f = fC
1
• The pattern between pin and oscillator approx.
ww wi co on ce c fo
1.5 kΩ
n.
should be made as short as possible. 0.3 V[p-p]

Di ain
C8
i o
15 pF
/en at
IN2 IN1
d te t o
.jp rm
ne ain ain foll
Temperature characteristic
n.p bo yp pe
200 µA 200 µA 500 µA product should be used for C8
co fo
/
co L a d t ty
(−750 ppm/°C)
pla m d m des
2 ic. t in
APC filter pin DC
on es
an ut e
lan nclu
• Filter pin for APC detection circuit approx.

M
as lat
25 µA
6.3 V
di
(Operates for BGP period) 5.6 V

e
200 Ω
ue
270 Ω • Detection sensitivity becomes high when

84 kΩ
tin
p
270 Ω external R→Large (Tends to be easily

on
2
pulled in and β curve
isc
1.0 µF 50 µA
afffected
/D
3 300 pF
ce
by noise.) f
R C
an
3.3 kΩ
p:/ fo
1 000 µA
en
htt visit
int
V2
Ma
se
3 9 V (VCC1-1) YS/YM input pin AC

ea
5V 25 µA 3 V • Fast blanking pulse input pin for OSD (Pulse)

25 µA
Pl
16 kΩ
25 µA 25 µA • YM On (Half-tone) at 1.0 V[0-p] or
YS
higher
3V 1V
• YS ON(OSD input) at 3.0 V[0-p] or YM
270 Ω 1 kΩ
3 higher
• Recommended use range: 0 V to 6 V
50 kΩ
25 µA 25 µA
SDB00001BEB 15
AN5165K
■ Terminal Equivalent Circuits (continued)

9 V (VCC1-1)
4 External R input pin AC
5 External G input pin (Pulse)
6 50 µA External B input pin 5.0 V
to RGB Output • External input pin for OSD
Circuit 0
• Output linearly changes according to
pin4, 5, 6 200 Ω
input level
ue e/
50 kΩ
5.0 V • Recommended use range: 0 V to 6 V
50 kΩ
0
from
µ-COM
tin nc
7  VCC1-1 (typ.9 V) DC
d
.
ge
• Video circuit 9V
sta
• Chroma circuit
cle
• RGB circuit
on na
cy
• Sync. circuit
life
• DAC circuit
ct
8 9 V (VCC1-1) R Out pin AC
du
9 G Out pin
sc te
100 µA
10 B Out pin
50 Ω Pin 8 • BLK level approx. 1.5 V
ww wi co on ce c fo
9
n.
10 • Black (Pedestal) level approx. 3.0 V

Di ain
o
• Recommended use range: −2.4 mA to
i
/en at
100 µA
d te t o
+4.8 mA d
.jp rm
ne ain ain foll
n.p bo yp pe
co fo
/
co L a d t ty
11 Horizontal sync. detection pin DC

pla m d m des
5V
(VCC2-2) ic. t in
• Phase of horizontal synchronizing signal when
on es
an ut e
lan nclu
and horizontal output pulse are detected synchronized

M
as lat
to
Chroma
di
10 kΩ Circuit and outputted 4.5 V

e
ue
12 kΩ 2.8 V • Pin 11 becomes low at out of when

I1
tin
800 µA 12 kΩ
p
synchronization asynchronous
on
3.7 V • Color control becomes min. and chroma 0.1 V

isc
I2
800 µA output disappears and VOUT goes into free-
/D
ce
running state in a asynchronous condition

50 µA
an
• Pay attention to impedance when pin 11

p:/ fo
en
270 Ω 8 µA voltage is used for microcomputer

htt visit
int
(ZO ≥ 680 kΩ required)

Ma
11 ZO
se
pin 50
ea
0.082 µF ZO≥680 kΩ H Out

Pl
pin 41
HSYNC In
• HSYNC period, when pin 50
at high: I1 ON
at low: I2 ON
12  GND DC
• RGB circuit
• DAC. I2C circuit
• VIF (VCO) circuit
16 SDB00001BEB
AN5165K

9V
13 (VCC1-1) ACL/ABL pin DC
• RGB output is blacked out when DC voltage approx. 3.5 V
5.9 V
of pin 13 is decreased from the outside.
140kΩ
60 kΩ 60 kΩ However, it is not blacked out when service
Neck
switch has been turned on.
6.9 kΩ
2.7 V (Service switch priority)
ue e/
7.1 kΩ
6.9 kΩ
• When 01−D7 = 1, ABL functions, and brightness
7.1 kΩ
5 kΩ ABL decreases by lowering DC voltage of pin 13
2.7 V 6.9 kΩ • When pin 13 is grounded, ACC gain becomes
tin nc
13
min. and it is possible to measure chroma
d
.
ge
free-running frequency. Measuring point is
sta
pin 51.
cle
When neck protect time high • Recommended use range: 0 V to V
CC1
on na
cy
14 5V I2C BUS Data input pin AC
life
5V (VCC2-2)
• Input low level: 0.9 V or less (Pulse)
ct
3.25 V • Input high level: 3.1 V or more
20 µA 50 µA
du
2.7 kΩ
10 kΩ • ACK sink capability: 1.8 mA 5.0 V
Data 14 1 kΩ
sc te
14 51 kΩ • Recommended use range: 0 V to VCC2 0

100 Ω 2 kΩ
ww wi co on ce c fo
from
µ-com
n.
to Logic
Di ain
o
Circuit
ACK
i
/en at
d te t o
30 kΩ 30 kΩ d
.jp rm
ne ain ain foll
n.p bo yp pe
co fo
/
co L a d t ty
pla m d m des
15 5V
ic. t in
I2C clock input pin AC
on es
an ut e
lan nclu
5V (VCC2-2)
• Input low level: 0.9 V or less (Pulse)
M
as lat
di
3.25 V • Input high level: 3.1 V or more

2.7 kΩ 20 µA 50 µA
e
ue
1 kΩ 10 kΩ • Recommended use range: 0 V to VCC2 5.0 V

Clock
tin
p
15 51 kΩ 0
on
100 Ω 2 kΩ
isc
from
µ-com
/D
to Logic
Circuit
ce
ACK
an
30 kΩ 30 kΩ
p:/ fo
en
htt visit
int
16 External blanking input pin AC

Ma
9V
(VCC1-1)
se
50 µA 50 µA
10 kΩ • RGB out blanking is applied when a voltage (Pulse)
H Sync.2
ea
of 0.8 V or more is applied

10 kΩ
Pl
8.2 V
0.7 V 3.9 kΩ • HSCP pulse output pin
16
2.7 kΩ 270 Ω 5.6 kΩ Horizontally synchronized 2 µs pulse is 5V
100 kΩ outputted. 0V
40 kΩ
• Recommended use range: − 0.8 mA to
0.2 mA, 0 V to 5.0 V
SDB00001BEB 17
AN5165K

17 9V White Peak Detect Filter input pin DC
10 µA 40 µA (VCC1-1)
9V 20 µA • White gradation correction response
YOUT characteristic is determined.
4.7 µF
270 Ω When there is screen sag, make C→larger
17
When screen response is slow, make
C→smaller
ue e/
375 Ω 50 kΩ
6 kΩ
40 µA
50 µA
tin nc
18  VCC2-1 (typ.5 V) DC
d
.
ge
• VIF, SIF circuit 5V
sta
19 5V VIF input pin 1 AC
cle
(VCC2-1)
20 VIF input pin 2 f = fP
on na
3.5 V
cy
• VIF amp. input with balanced input DC level
life
27 kΩ
• Input max.120 dBµ approx. 2.7 V
1.2 kΩ
ct
1.2 kΩ Input resistance: 1.2 kΩ (45.75 MHz)
du
20
Input capacitance: 4.0 pF (45.75 MHz)
sc te
SAW 0.68 µH
19 .se ng ntin tin ty e ty ur
0.022 µF
ww wi co on ce c fo
n.
Di ain
o
150 µA 150 µA
i
/en at
d te t o
.jp rm
ne ain ain foll
21  GND DC
n.p bo yp pe
co fo
/
• For VIF and SIF circuit
co L a d t ty
pla m d m des
22 5V ic. t in
RF AGC output pin DC
on es
an ut e
lan nclu
3 kΩ 6 kΩ (VCC2-1)
M
as lat
• Collector open output
di
100 µA • Recommended use range: 0 V to VCC1 (9 V)

e
ue
10 kΩ
IF AGC
Bias Maximum sink current min.: 1.5 mA
tin
22
p
on
to Tuner
270 Ω RF AGC
isc
33 kΩ Control
Bias
/D
40 kΩ
ce
1 kΩ 1 kΩ
an
p:/ fo
en
23 SIF APC filter pin DC

htt visit
int
9V
• Filter pin for APC circuit of SIF. approx. 2.5 V
Ma
(VCC1-2)
se
• Deemphasis characteristic is changeable

ea
by the capacitor between pin and GND

Pl
12.2 kΩ 7.5 kΩ
1.5 V
270 Ω 875 Ω
57 kΩ
23
4 pF 100 pF
18 SDB00001BEB
AN5165K

24 9V Audio output pin AC
(VCC1-2)
• DC fluctuates by internal/external changeover 0 kHz to 20 kHz
• Recommended use range: − 0.8 mA to DC
24
270 Ω + 0.8 mA approx. 3.9 V
150 µA 800 µA
ue e/
25 9V
External video input pin AC
(VCC1-1) • Input pin for external video signal and DC 1 V[p-p]
50 µA (VCC1-2)
50 µA
Int. Video cut input (Composite)
tin nc • Typical: 1 V[p-p] (max. 1.5 V[p-p])
d
.
1.6 V
ge
to
Video SW 4.7 µF • ZO is 100 Ω or less
sta
25
ZO<100 Ω
500 Ω
cle
7 µA
DC
on na
cy
approx. 1.6 V
life
26 9V Decoupling pin DC
ct
(VCC1-2)
• S-curve in IC is wideband, but DC feedback is
du
10 kΩ
applied so that DC voltage of output signal
sc te
becomes constant.
270 Ω
1.7 kΩ 26 • DC level (typ. 4.5 V), fS→high: V26→low
ww wi co on ce c fo
typ. 4.5 V C
4.7 µF
• If C (4.7 µF) is too small, sound distortion
n.
Di ain
270 Ω
o
3 kΩ 3 kΩ
i
tends to become larger at low frequency.
/en at
d te t o
.jp rm
ne ain ain foll
n.p bo yp pe
20 kΩ
co fo
/
co L a d t ty
pla m d m des
100 µA 13 µA
ic. t in
on es
an ut e
lan nclu
M
27 External audio input pin AC

as lat
9V
di
(VCC1-2)
• Input pin for external audio signal. DC cut 0 kHz to 20 kHz
e
5.4 V
ue
50 µA
input.
tin
p
• Adjust typical input level to internal sound

on
to
Audio SW 65 kΩ 270 Ω
level.
isc
27
10 µF
270 Ω • Input max. 7 V[p-p]
/D
ce
an
150 µA
p:/ fo
en
28 SIF signal input pin AC

htt visit
9V
int
(VCC1-2)
3 kΩ • Input max. 110 dBµ f = fS
Ma
3 kΩ
0.01 µF 270 Ω
se
28 Blooming DC adjusting pin

ea
1.5 kΩ 128 kΩ • White gradation correction curve and bias DC

Pl
Blooming to SIF
DC Limitter Amp. to determine absolute clip point are provided. approx. 2.3 V
80 pF
(2.0 V to 4.5 V)
100 µA • Recommended use range: 0 V to VCC1 (9 V)
25 µA
SDB00001BEB 19
AN5165K

29 5V IF AGC filter pin DC
(VCC2-1)
• Pin for IF AGC filter. The current obtained approx. 2 V
from peak AGC circuit is smoothed by
270 Ω 270 Ω external capacitor.
to IF Amp. • Since response becomes faster when C goes
30 µA 29 smaller, hum characteristic will be improved.
ue e/
However, sag tends to appear easily.
0.47 µF
30 Video output pin AC
tin nc
9V
(VCC1-2) • INT.Video or EXT.Video selected by AV 2 V[p-p]
d
.
ge
100 µA
500 Ω
SW is outputted.
sta
50 Ω • Recommended use range −3.2 mA to
30
cle
+0.4 mA DC level
on na
cy
approx. 4.2 V
life
400 µA
ct
31 AFT output pin DC
du
9V
(VCC1-2) • Offset of center voltage is adjusted by bus
sc te
1.1 kΩ 1.1 kΩ
9V
• When AFT defeat SW is turned on (0B = 00),
33 kΩ
V31 becomes a value determined by external
ww wi co on ce c fo
n.
to Tuner
31 resistance-divider.
Di ain
270 Ω
o
• µ of AFT is variable by impedance of
i
0.01 µF
/en at
33 kΩ
d te t o
.jp rm
externally attached resistor.
ne ain ain foll
n.p bo yp pe
1.1 kΩ 40 kΩ 1.1 kΩ
co fo
/
co L a d t ty
pla m d m des
max. 350 µF
ic. t in
on es
an ut e
lan nclu
32 Internal video input pin AC

M
as lat
9V
di
(VCC1-1)
50 µA • Input pin for signal detected by VIF circuit 1 V[p-p]
e
(VCC1-2)
ue
50 µA Int. Video (Internal video signal). (Composite)

tin
p
1.6 V • DC cut input

on
to
Video SW 4.7 µF
Typical input: 1 V[p-p] (max. 1.5 V[p-p])
isc
32
ZO
ZO ≅ 280 Ω
/D
500 Ω
7 µA
ce
DC level
an
approx. 1.6 V
p:/ fo
en
33 VIF detection output pin AC

htt visit
int
9V
(VCC1-2)
• Adjusted to center value by I2C bus approx.
Ma
150 µA
se
(Using upper 4-bit of 0 A) 2.1 V[p-p]

ea
50 Ω DC voltage becomes approx. 1 V at

Pl
33
external video mode (04−D6 = 1)
Recommended use range: −1.6 mA to
800 µA + 0.8 mA
20 SDB00001BEB
AN5165K

34 5V APC filter pin DC
(VCC2-1)
50 µA • Filter pin for VIF APC circuit. approx. 2.5 V
SW • Lock detection circuit for VCO is built
1
0 in the IC inside to changeover the time
constant for APC filter.
500 Ω 270 Ω
ue e/
10 kΩ
3.25 V
to
220 pF to1800 pF
34
VOC
0.47 µF
tin nc
75 µA
75 Ω
d
.
ge
25 µA
sta
35 5V
VIF oscillation pin AC
cle
(VCC2-1)
36 • Oscillation coil is changed according to approx.
on na
1.5 kΩ 1.5 kΩ
cy
35 36 VIF frequency. 0.3 V[p-p]
life
• Allowable value of dispersion for coil DC level
ct
resonance point is within 1%. approx. 3.9 V
du
sc te
2.5V .se ng ntin tin ty e ty ur

ww wi co on ce c fo
n.
Di ain
1 200 µA
o
1 200 µA 300 µA 300 µA
i
/en at
d te t o
.jp rm

ne ain ain foll
37 VCC1-2 (typ.9 V) DC
n.p bo yp pe
co fo
IF circuit 9V
/
co L a d t ty
pla m d m des
38 ic. t in
Black level detection pin DC
on es
an ut e
lan nclu
9 V (VCC1-1)
• Black level detection pin for black extension approx. 5.1 V
M
as lat
2.5 2.5 kΩ
di
2.5 kΩ
kΩ circuit
e
−Y
ue
• The most black Y-level except for blanking

tin
p
circuit is held.
on
6.6 kΩ 6.6 kΩ
Black detection sensitivity drops when
isc
ZO is made smaller, so that black detection

/D
18 pF
270 Ω
ce
100 µA 50 µA
becomes impossible unless a large black
an
38 area.
p:/ fo
en
htt visit
ZO
int
4.7 µF
Ma
10 kΩ
se
ea
9V
39 (VCC1-1) Vertical sync. separation input pin AC
Pl
Video input pin 2.0 V[p-p]

50 µA 16 kΩ 16 kΩ
• Video signal input pin
Video (Also composite video input)
5V
• Typical input: 2.0 V[p-p]
220 kΩ
2.2 µF
• Sync. Top is clamped at 3.5 V
2.4 kΩ
39 • Video signal should be inputted at low
3.5 V
1 kΩ
41 impedance. (under 100 Ω)
0.015 µF
470 pF 60 pF 10 µA 8 µA
SDB00001BEB 21
AN5165K

40 5V Vertical synchronizing signal clamp pin AC
(VCC2-2)
4.3 V 3 kΩ • Peak clamp pin for separating vertical sync. f = fV
30 kΩ
signal.
10 kΩ
• Integral amount of vertical sync signal
10 kΩ to Ver.
Count Down itself has been determined by internal time
270 Ω 50 kΩ constant. However, trigger application timing
4 µA
ue e/
29
is determined by the selection of external
200 Ω C1 220
2.2 µF constant C1.
tin nc
41  Horizontal sync separation input pin AC
d
.
ge
• Internal circuit of pin 39 and 41 are the same. 2 V[p-p]
sta
• When R→large, slice level becomes deeper
cle
(Weak to Sync compression). When R→
on na
cy
small, slice level becomes shallower
life
(Weak to fluctuation such as Ver. Sag).
ct
• Sync. Top is clamped at 3.5 V.
du

42 VCC2-2 (typ.5 V) DC
sc te
For chroma, jungle circuit

.se ng ntin tin ty e ty ur 5V
ww wi co on ce c fo
43 9 V (VCC1-1) Chroma signal input pin AC+DC
n.
Black extension start point adjusting pin Burst typ.

Di ain
39 kΩ Chroma
o
200 Ω
i
attenuator
/en at
39 kΩ circuit • Pin 43 is chroma signal input pin, and black 300 mV[p-p]
d te t o
.jp rm
ne ain ain foll
extension start point is adjusted by externally

n.p bo yp pe
43
co fo
128 kΩ
/
270 Ω
co L a d t ty
applied DC voltage. DC typ.

pla m d m des
68 pF 100 µA
60 pF
ic. t in
DC level: high ↔ low 4.5 V
on es
an ut e
lan nclu
Blstart
Black extension DC Start point: Shallow ↔ Deep
M
as lat
di
100 µA 25 µA Black extension effect: Small ↔ Large

e
ue
• Recommended use range: 0 V to VCC1 (9 V)

tin
p
44  GND DC
on
• For video, chroma, jungle circuit 0V

isc
/D
45 5 V (VCC2-2) FBP input pin AC

ce
100 µA 50 µA • FBP input pin for horizontal blanking and FBP

an
100 µA 50 µA AFC circuit

p:/ fo
en
• Threshold level
htt visit
int
Ma
2.7 kΩ HBLK: 0.7 V

1.9 V
se
24 kΩ
to AFC: 1.9 V
ea
AFC
to 2.7 kΩ 270 Ω • A voltage input of 0 V or less is inhibited.
Pl
0.7 V
HBLK 45
60 kΩ • Recommended use range: 0 V to VCC2 (5 V)
100 kΩ
40 kΩ
50 µA
46  Horizontal stabilized power supply pin. DC

6.2 V
22 SDB00001BEB
AN5165K

47 Horizontal AFC1 filter pin DC
6.2 V
4.3 V
(VCC3) • The capacitor connected to pin 47 is charged typ. 4.3 V
and discharged after comparing the phase
27 kΩ
AFC1 R1 27 kΩ of horizontal synchronizing signal and pulse
Detecter
inside the IC.
1.5 V
• R1, R2, C1 and C2 are lag lead filter for
ue e/
47 AFC1. Horizontal β curve
1 µF fH
Hor. Sync. C2 Hor.
OSC
tin nc
0.033 µF
C1
d
200 µA
.
R2
ge
1 000 µA 1.8 kΩ V53
sta
48 6.2 V Horizontal oscillation pin AC
cle
(VCC3)
• Oscillation takes place at 32 × fH ≅ 503 kHz f = 32 fH
on na
cy
by ceramic oscillator. (approx.
life
22 kΩ
• Horizontal and vertical pulse are generated 500 kHz)
ct
300 Ω
by count-down circuit inside the IC.
du
200 µA 10 kΩ 10 kΩ
80 µA
sc te
48
100 µA
220 pF: Temperature characteristic product should
ww wi co on ce c fo
be used (−750 ppm/°C)
n.
Di ain
i o
49 Overvoltage protection input pin DC
/en at
d te t o
9V d
.jp rm
ne ain ain foll
• If increasing input pin voltage from 0 V Normally

n.p bo yp pe
(VCC1-1)
co fo
at VREF (pin 46) = 6.2 V;
/
0V
co L a d t ty
pla m d m des
ic. t in
(1) Horizontal oscillation come to be out
on es
an ut e
lan nclu
1 kΩ V
of synchronization: approx. 6.15 V
M
as lat
CC3
49
48.3 kΩ
di
1 kΩ (2) Blacked out: (1)+70 mV

46
e
ue
• Recommended use range: 0 V to VCC1 (9 V)

tin
p
20 kΩ
on
100 µA
isc
/D
ce
50 6.2 V Horizontal pulse output pin AC

an
(VCC3)
4.3 V • Duty cycle approx. 37% Pulse
p:/ fo
en
19 kΩ
• Recommended use range: −6.4 mA to 3.5 V
htt visit
int
50 Ω +0.1 mA
Ma
0
se
50
ea
10 kΩ 3.5 V
40 kΩ
Pl
0V
Hor. Out
SDB00001BEB 23
AN5165K

51 CW output pin / input pin for spot killer off. AC
9 V (VCC1-1) (Output amplitude 860 mV[p-p]) Approx.
320 kΩ 80 kΩ
50 µA 30 kΩ The pin also shares in Hold-down detection. 830 mV[p-p]
15 pF To spot
270 Ω
51 killer • At normal: 6.1 V (DC)
10 kΩ circuit
44 kΩ • At hold-down: 1.2 V (DC)
• Apply 9 V(VCC1) DC to turn off spot killer. f = 3.58 MHz
ue e/
596 kΩ 100 µA 30 kΩ
Hold Recommended use range: − 0.4 mA to + 0.1 mA
0 V to VCC1
tin nc
52 Vertical pulse output pin AC
d
5V
.
ge
(VCC2-2)
50 kΩ • Negative polarity, pulse width 6.25 H Pulse
sta
52 • Recommended use range: − 0.8 mA to + 0.1 mA
4.2 V 4.2 V
cle
43 kΩ
on na
cy
0 0
life
ct
du
sc te

■ New Package Dimensions (Unit: mm)
ww wi co on ce c fo
n.
• SDIP052-P-0600F (Lead-free package)

Di ain
i o
/en at
d te t o
.jp rm
ne ain ain foll
n.p bo yp pe
47.70±0.30
co fo
/
co L a d t ty
pla m d m des
52 27
ic. t in
on es
an ut e
lan nclu
13.70±0.20
M
as lat
di
e
ue
1 26
tin
3.85±0.30
p
on
isc
/D
0.70 min.
3.30±0.30
ce
(1.625) 1.778 0.50±0.10 15.24

an
1.00±0.10 +0.10
p:/ fo
0.25 -0.05
en
Seating plane
3° to 15°
htt visit
int
Ma
se
ea
Pl
24 SDB00001BEB
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products, and no license is granted under any intellectual property right or other right owned by our company or any other
company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other
company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office
equipment, communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod-
ue e/
ucts may directly jeopardize life or harm the human body.
– Any applications other than the standard applications intended.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or im-
tin nc
provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
d
.
Standards in advance to make sure that the latest specifications satisfy your requirements.
ge
sta
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
cle
on na
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
cy
defect which may arise later in your equipment.
life
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
ct
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
du
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
sc te
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
ww wi co on ce c fo
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
n.
Di ain
o
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita
i
/en at
d te t o
Electric Industrial Co., Ltd.

d
.jp rm
ne ain ain foll
n.p bo yp pe
co fo
/
co L a d t ty
pla m d m es
ic. t in
ne lud
on es
an ut e
pla inc
M
as lat
d
ue
tin
on
isc
/D
ce
an
p:/ fo
en
htt isit
int
Ma
v
se
ea
Pl

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ICs for TV

Note) The package of this product will be changed

new package dimensions section later of this

Publication date: December 2001 SDB00001BEB 1

15 SCL 42 VCC2-2 5 V (Chroma/jungle/DAC)

17 White Detect 44 GND (Video/Chroma/Jungle)

18 VCC2-1 5 V (VIF/SIF) 45 FBP Inputd

20 VIF Input (2) 47 ic. t in

22 RF AGC Output 49 X-ray Protection Input

23 SIF APC Filter 50 Hor. Pulse Output

24 Audio Output 51 CW Output/Spot KILLER Off Input/

X-ray Protection Output

25 External Video Input

26 DC Decoupling Filter 52 Ver. Pulse Output

27 External Audio Input

■ Absolute Maximum Ratings

Parameter Symbol Rating Unit

■ Absolute Maximum Ratings (continued)

Power supply .se ng ntin tin ty e ty ur

Supply current 3 I46

Supply current 4 I46 Current at V46 = 6.2 V. However 5 7 9 mA

all other power supplies are off state

VIF circuit (Typical input fP = 45.75 MHz, VIN = 90 dBµ)

(Difference from fP = 45.75 MHz)

■ Electrical Characteristics at Ta = 25°C (continued)

Video SW voltage gain GVSW f = 1 MHz, VIN = 1 V[p-p]

Data 0 F−D5 = 1 (external) −3 −1

Audio SW voltage gain GASW 1 dB

(VWB = 1.43 V[0-p]stair-step) at GOUT.)

Contrast variable range YCmax/min 03 = 7F 19 22 26 dB

Frequency to become −3 dB from

Sharpness variable range YSmax/min 04 = 3F f = 3.8 MHz 7 10.5 14 dB

■ Electrical Characteristics at Ta = 25°C (continued)

tin nc Data 00 = 40 (typ.), 03 = 40 (typ.)

Input: Color bar

Input: Color bar

Tint center d 0 13 STEP

Tint variable range 1 ∆θ1 Data 01 = 7F

∆θ2 Data 01 = 00 −60 −45 −30

Tint variable range 2 deg

Demodulation output angle (R) ∠R Input: Rainbow 92 104 116 deg

APC pull-in range (H) fCPH 450 900  Hz

APC pull-in range (L) fCPL  −900 −450 Hz

RGB processing circuit

■ Electrical Characteristics at Ta = 25°C (continued)

External RGB contrast variable range ECmax/min 03 = 7F 5 8 11 dB

Input 0.2 V[p-p], DC = 1 V d 

Synchronizing signal processing circuit

Difference from fH = 15.75 kHz ±500 ±650 

Horizontal pull-in range fHP Hz

Vertical free-running oscillation fVO-N Without sync. signal input 58 60 62 Hz

Vertical output pulse width τVO 5.5 6.5 7.5 1/fH

between HSYNC and HOUT Data from

SCL, SDA signal input high level VIHI 3.1  5.0 V

SCL, SDA signal input low level VILO 0  0.9 V

• Design reference data

■ Electrical Characteristics at Ta = 25°C (continued)

RF AGC adjustment sensitivity SRF Average amount of change of output

Video detection output-temperature ∆VP/T Ta = −20°C to +70°C  ±5 ±10 %

Input resistance (pin 19, 20) RI19,20 f = 45.75 MHz  1.2  kΩ

Input capacitance (pin 19, 20) CI19,20 f = 45.75 MHz  4.0  pF

∆VDP/T Ta = −20°C to +70°C

RF AGC delay point 0 3 5 dB

VCO free-running frequency ∆fP/T Ta = −20°C to +70°C  300  kHz