Lecture 5

Logic Families and Binary Representation

5.1 Logic Families

5.1.1 Overview

The choice of logic levels is arbitrary, but all gates that communicate must have compatible logic levels.
Therefore, gates are grouped into logic families such that all gates in a logic family obey the static
discipline when used with other gates in the family. Logic gates in the same logic family are compatible
in that, they use consistent power supply voltages and logic levels. A logic family is a circuit technology
that can be used to create many different types of gates: inverter, NAND, NOR, etc. Most logic today is
based on CMOS logic families based on MOSFETs.

If we mix logic from two different logic families, we need to be careful to obey the input and output signal
specifications. These specifications also limit our ability to connect logic gates to nonlogic circuits. For
example, a logic gate may not be able to supply enough current to directly drive a speaker.

5.1.2 Common Logic Families

There are many logic families but in this section we will limit ourselves to three major common logic
families. These families are TTL, ECL and CMOS as described briefly in section below. There are
various other families such as dynamic current mode logic (DCML) which operates in differential mode
(hence reducing crosstalk) for small swings (hence leading to fast switching).

5.1.2.1 TTL Family

In transistor-transistor logic (TTL), logic gates and other digital circuits are made using BJTs and resis-
tors. The term transistor-transistor is indicative of the fact that both logic function and amplification are
done by transistors. Using TTL logic family, many logic gate can be fabricated in a single circuit. For

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LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 55

logic gates built using TTL logic family, inputs are given to the emitter of the input transistor. In TTL
logic family, the analog voltage value from 0.0V to 0.8V is regarded as logic 0 while the analog voltage
value from 2.0V to 5.0V is regarded as logic 1. Advantage of TTL logic family is include high switching
speed (125MHz), less noise and more current (3mA) driving capability. One of the logic families closely
related to TTL family is the Low Voltage TTL Logic (LVTTL).

5.1.2.2 ECL Family

Emitter coupled logic (ECL), also referred to as current mode logic family, is a digital technology with
extremely high-speed. Transistors are not allowed to to go into deep saturation thus, eliminating storage
delays like in TTL family. Transistors are driven either in cut-off or in active region. This is achieved by
using voltage values close to each other. For logic one it is -0.90V and for logic zero, it is -1.75V. In the
active region, charge stored in the base region of transistors is kept to minimum. The difference between
these logic states is very small. This improves the speed of operation at the expense of noise margin.
Propagation time for an ECL gate is 0.5 ns to 2 ns which is very low compared to its TTL counterpart.

The disadvantage of ECL family is that it uses a negative power supply such that the logic levels are not
compatible with any other logic family and makes analysis and measurement inconvenient. ECL family
requires large currents, therefore power dissipation is three to ten times higher than that of TTL family.
Because of its large power consumption and high requirement of silicon area, CMOS logic family gates
are preferred over ECL family in large scale integrated circuits.

5.1.2.3 CMOS Logic Family

Because of high noise immunity and low static power dissipation, now the complementary metal oxide
semiconductor (CMOS) logic family is most preferred in large scale integrated circuits. CMOS has
complementary and symmetrical NMOS and PMOS transistors. For an inverter circuit only one transistor
if the CMOS will be ON at a time for an inverter thereby reducing static power loss of a transistor. One
of the closely related families is the Low Voltage CMOS Logic (LVCMOS).

5.1.3 Further Classifications

5.1.3.1 Types of Logic Family

The digital integrated circuits are designed using bipolar devices or Metal Oxide Semiconductor (MOS)
or a combination of both. There are two kinds of semiconductor devices. The logic family which falls
under the first kind Bipolar logic family and the other is Unipolar logic family.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 56

5.1.3.2 Bipolar Logic Family

There are two kinds of operations in bipolar integrated circuits:

(a). Saturated Bipolar Logic family and

(b). Non-saturated Bipolar Logic family.

Saturated Bipolar Logic Families are:

• Diode Logic (DL)

• Resistor Transistor Logic (RTL)

• Diode Transistor Logic (DTL)

• Integrated Injection Logic (IIL or I2L)

• Transistor Transistor Logic (TTL)

Non-saturated Bipolar Logic Families are:

• Schottky TTL

• Emitter Coupled Logic (ECL)

5.1.3.3 Unipolar Logic Family

Unipolar logic family consists of;

(a). Metal Oxide Semiconductor (MOS) Logic families.

They are:

• P-type MOS (PMOS) Logic

• N-type MOS (NMOS) Logic

• Complementary MOS (CMOS) Logic

• Bipolar MOS (BiMOS) Logic

• Bipolar CMOS (BiCMOS) Logic

LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 57

5.1.3.4 Classification of Logic Family

Logic families are mainly classified as;

(a). Bipolar Logic Families and

(b). Unipolar Logic Families.

Bipolar Logic Families

It mainly uses bipolar devices like diodes, transistors in addition to passive elements like resistors and
capacitors. These are sub-classified as saturated bipolar logic family and unsaturated bipolar logic family.

Saturated Bipolar Logic Family: In this family the transistors used in ICs are driven into saturation.
For example:

• Transistor-Transistor Logic (TTL)

• Resistor-Transistor Logic (RTL)

• Direct Coupled Transistor Logic (DCTL)

• Diode Transistor Logic (DTL)

• High Threshold Logic (HTL)

• Integrated Injection Logic (IIL or I2L)

Unsaturated bipolar logic family: In this family the transistors used in IC is not driven into saturation.
For example:

• Schottky TTL

• Emitter Coupled Logic(ECL)

Unipolar Logic Families

It mainly uses Unipolar devices like MOSFETs in addition to passive elements like resistors and capaci-
tors. These logic families have the advantages of high speed and lower power consumption than Bipolar
families. These are classified as:

(a). PMOS or P-Channel MOS Logic Family

(b). NMOS or N-Channel MOS Logic Family

(c). CMOS Logic Family

LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 58

Table 5.1: Logic levels of different logic families.

Family VDD VIL VIH VOL VOH
TTL 5.0 (4.75 - 5.25) 0.8 2.0 0.4 2.4
CMOS 5.0 (4.50 - 6.00) 1.35 3.15 0.33 3.84
LVTTL 3.3 (3.00 - 3.60) 0.8 2.0 0.4 2.4
LVCMOS 3.3 (3.00 - 3.60) 0.9 1.8 0.4 2.7

5.1.3.5 Features of Some Logic Families

(a). TTL - Transistor-Transistor Logic: Standard logic family; used for the longest time.

(b). ECL - Emitter Coupled Logic: Suitable for systems requiring high-speed operations.

(c). MOS - Metal Oxide Semiconductor Logic: Suitable for systems with high component density.

(d). CMOS - Complementary Metal Oxide Semiconductor Logic: Suitable for systems with low power
consumption (VLSI circuits). Gradually becomes the dominant logic family.

5.1.4 Characteristics

The main characteristics of logic families include:

• Speed: Time between input applied and output received.

• Fanin: The number of inputs a logic gate can handle.

• Fanout: The number of circuits a logic gate can drive.

• Noise immunity: Maximum noise that a circuit can withstand without affecting the output.

• Power dissipation: When a circuit switches from one state to another, power is dissipated.

• Supply voltage range: A range of voltage values allowed at logic gate supply pin.

• I/O logic levels: A range of allowed voltage values defining input and output levels of a logic gate.

Fanin and fanout can also be related to current sinking and sourcing capabilities. These characteristics
can also be used as objective measures for comparing the performance different logic families. Size, cost
of production and flexibility can also be added to the list above.

5.1.5 Comparison and Compatibility

The logic levels of four chosen logic families are compared in table 5.1.

Note that a 5 V logic family such as TTL or CMOS may produce an output voltage as HIGH as 5 V. If
this 5 V signal drives the input of a 3.3 V logic family such as LVTTL or LVCMOS, it can damage the
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 59

Table 5.2: Logic families compatibility.

Driver TTL Receiver CMOS Receiver LVTTL Receiver LVCMOS Receiver
TTL Ok No Maybe Maybe
CMOS Ok Ok Maybe Maybe
LVTTL Ok No Ok Ok
LVCMOS Ok No Ok Ok

receiver, unless the receiver is specially designed to be 5-volt-compatible. Table outlines which of the
logic families in table 5.1 can communicate with each other reliably based only on their logic levels

Given this basic understanding of how these logic families work, we can set up a scenario in which
each logic families fail. The mechanisms by which they fail are different due to the different operating
characteristics of the families. CMOS is sensitive to fanout, which is the number of gates attached to the
output of a driver gate. Some logic families are also sensitive to fanin constraints, which is the number
of gates connected to the input of a given gate. Capacitance is at the root of the fanout problem. In
practice, the load capacitance is the gate capacitance of the transistors that form the next logic gate. As
fanout increases, the capacitive load increases.

Typically the input capacitances of the load gates are in parallel so we can add them to find the total
load capacitance. The voltage across this capacitance is equal to the input voltage at each fanout gate;
all fanout gates see the same input voltage. This voltage waveform is a simple ramp which increases
steadily until it reaches the power supply voltage, at which point the driver transistor turns off. The slope
of the ramp depends on the ratio of the load capacitance and the driver current. The output current is
determined by the logic family.

As the load capacitance increases, the slope decreases and the time required for the voltage to reach its
final value increases. Interfaces have timing requirements, which is a maximum delay from the change of
an input to the change at its output. If the slope of the voltage waveform is shallow enough, the logic fails
to satisfy its timing requirement. Given these illustrations of the importance of electrical specifications
to the proper function of logic gates, we can now look at the specifications themselves.

Most logic families represent logic values as voltages; a few logic families use currents to represent logi-
cal values. We talk informally about a high voltage representing a logic 1 and a low voltage representing
a logic 0. In fact, a range of voltages can be used to represent logic values. Accepting a range of signal
values protects the logic functions against noise, which is inevitable in real circuits. Intermediate values
represent invalid logic values. Leaving a gap between the valid logic 0 and logic 1 levels also contributes
to noise immunity. The next section elaborates more on the binary number representation as a means of
representing logic values.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 60

5.2 Binary Number Representation

5.2.1 Number Base Conversion

There are many number systems differing by the base. One of the most common number system is
decimal which uses base ten. There are other numbering systems based on different bases including the
following;

• Binary: Uses base two.

• Octal: Uses base eight.

• Hexadecimal: Uses base sixteen.

In this section we will limit ourselves to binary and decimal. We will proceed to discuss the conversion
between decimal and binary in the next sections.

5.2.1.1 Decimal To Binary

We can convert from decimal to binary by using long division (by 2 as a base number) techniques and
keeping remainders as digits of our binary number. Here is an example with a decimal number 10810 .
Here are the steps:

(a). Divide 108 by 2 to get 54 remainder 0,

(b). Divide 54 by 2 to get 27 remainder 0,

(c). Divide 27 by 2 to get 13 remainder 1,

(d). Divide 13 by 2 to get 6 remainder 1,

(e). Divide 6 by 2 to get 3 remainder 0,

(f). Divide 3 by 2 to get 1 remainder 1,

(g). Divide 1 by 2 to get 0 remainder 1,

(h). Now that we arrived at zero, we stop dividing. We combine all the remainders (starting from the
most recent remainder all the way to the oldest one) to get a binary number 11011002 .

Therefore, we can conclude that the binary conversion of a decimal number 10810 is 11011002 . Here is
another example with a decimal number 17010 ,

(a). Divide 170 by 2 to get 85 remainder 0,

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(b). Divide 85 by 2 to get 42 remainder 1,

(c). Divide 42 by 2 to get 21 remainder 0,

(d). Divide 21 by 2 to get 10 remainder 1,

(e). Divide 10 by 2 to get 5 remainder 0,

(f). Divide 5 by 2 to get 2 remainder 1,

(g). Divide 2 by 2 to get 1 remainder 0,

(h). Divide 1 by 2 to get 0 remainder 1,

(i). Now that we arrived at zero, we stop dividing. We combine all the remainders (starting from the
most recent remainder all the way to the oldest one) to get a binary number 101010102 .

Therefore, we can conclude that the binary conversion of a decimal number 17010 is 101010102 .

5.2.1.2 Binary To Decimal

Converting from binary to decimal is a bit easier than converting from decimal to binary. We will
demonstrate the conversion using an example. Given a binary number, we convert it to decimal by
treating each digit as if it is a coefficient in a polynomial and the position of that digit is treated as a
power/exponent of a base number 2. The positions of the digits starts from zero at the least significant
bit (LSB) and increases all the way to the most significant bit (MSB). The sum of all the polynomial
terms will give us the decimal number equivalent to the given binary number. As an example, let us
convert the binary number 011011002 to decimal. We write this as follows,

011011002 ⇒ 0 × 27 + 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20 = 10810

Therefore, the decimal equivalent of the binary number 011011002 is 10810 . Here is another example
for binary number 101010102 .

101010102 ⇒ 1 × 27 + 0 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 0 × 20 = 17010

Therefore, the decimal equivalent of the binary number 101010102 is 17010 .

5.2.2 Unsigned Binary Numbers

5.2.2.1 Overview

We can make the binary numbers into the following two groups − Unsigned numbers and Signed num-
bers. Unsigned numbers contain only magnitude of the number. They don’t have any sign. That means
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 62

all unsigned binary numbers are positive. As in decimal number system, the placing of positive sign
in front of the number is optional for representing positive numbers. Therefore, all positive numbers
including zero can be treated as unsigned numbers if positive sign is not assigned in front of the number.

5.2.2.2 Representation

The bits present in the un-signed binary number holds the magnitude of a number. That means, if the
un-signed binary number contains ‘N’ bits, then all N bits represent the magnitude of the number, since
it doesn’t have any sign bit. As an example, consider the decimal number 108. The binary equivalent of
this number is 1101100. This is the representation of unsigned binary number.

10810 = 11011002

It is having 7 bits. These 7 bits represent the magnitude of the number 108.

5.2.3 Signed Binary Numbers

5.2.3.1 Overview

Signed numbers contain both sign and magnitude of the number. Generally, the sign is placed in front
of number. So, we have to consider the positive sign for positive numbers and negative sign for negative
numbers. Therefore, all numbers can be treated as signed numbers if the corresponding sign is assigned
in front of the number. If sign bit is zero, which indicates the binary number is positive. Similarly, if
sign bit is one, which indicates the binary number is negative.

5.2.3.2 Representation

The MSB (Most Significant Bit) of signed binary numbers is used to indicate the sign of the numbers.
Hence, it is also called as sign bit. The positive sign is represented by placing ‘0’ in the sign bit.
Similarly, the negative sign is represented by placing ‘1’ in the sign bit. If the signed binary number
contains ‘N’ bits, then N − 1 bits only represent the magnitude of the number since one bit MSB is
reserved for representing sign of the number.

There are three types of representations for signed binary numbers which are Sign-Magnitude form, 1’s
complement form, and 2’s complement form. Representation of a positive number in all these three
forms is the same while the representation of negative number will differ in each form. As an example,
consider the positive decimal number +108. The binary equivalent of magnitude of this number is
1101100. These 7 bits represent the magnitude of the number 108. Since it is a positive number, consider
the sign bit as zero, which is placed on left most side of magnitude.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 63

+10810 = 011011002

Therefore, the signed binary representation of positive decimal number +108 is 01101100. The same
representation is valid in sign-magnitude form, 1’s complement form and 2’s complement form for pos-
itive decimal number +108.

Sign-Magnitude Form

In sign-magnitude form, the MSB is used for representing sign of the number and the remaining bits
represent the magnitude of the number. So, just include sign bit at the left most side of unsigned binary
number. This representation is similar to the signed decimal numbers representation. As an example,
consider the negative decimal number −108. The magnitude of this number is 108. We know the
unsigned binary representation of 108 is 1101100. It is having 7 bits. All these bits represent the
magnitude. Since the given number is negative, consider the sign bit as one, which is placed on left most
side of magnitude.

−10810 = 111011002

Therefore, the sign-magnitude representation of −108 is 11101100.

1’s Complement Form

The 1’s complement of a number is obtained by complementing all the bits of signed binary number.
Therefore, the 1’s complement of positive number gives a negative number. Similarly, 1’s complement
of negative number gives a positive number. That means, if you perform two times 1’s complement of a
binary number including sign bit, then you will get the original signed binary number. As an example,
consider the negative decimal number −108. The magnitude of this number is 108. We know the signed
binary representation of 108 is 01101100. It is having 8 bits. The MSB of this number is zero, which
indicates positive number. Complement of zero is one and vice-versa. So, replace zeros by ones and all
ones by zeros in order to get the negative number.

−10810 = 100100112

Therefore, the 1’s complement of 10810 is 100100112 .

2’s Complement Form

The 2’s complement of a binary number is obtained by adding one to the 1’s complement of signed binary
number. So, 2’s complement of positive number gives a negative number. Similarly, 2’s complement
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 64

of negative number gives a positive number. That means, if you perform two times 2’s complement
of a binary number including sign bit, then you will get the original signed binary number. As an
example, consider again the negative decimal number −108. We know the 1’s complement of (108)10 is
(10010011)2 . The 2’s compliment of 10810 = 1’s compliment of 10810 + 110 which is,

10810 + 110 = 100100112 + 12 = 100101002

Therefore, the 2’s complement of 10810 is 100101002 .

5.2.3.3 Addition Operation

Consider the two signed binary numbers A & B, which are represented in 2’s complement form. We
can perform the addition of these two numbers, which is similar to the addition of two unsigned binary
numbers. But, if the resultant sum contains carry out from sign bit, then discard or ignore it in order to
get the correct value. If resultant sum is positive, you can find the magnitude of it directly. But, if the
resultant sum is negative, then take 2’s complement of it in order to get the magnitude. As an example,
let us perform the addition of two decimal numbers +7 and +4 using 2’s complement method. The 2’s
complement representations of +7 and +4 with 5 bits each are shown below.

+710 = 001112

+410 = 001002

The addition of these two numbers is,

(+7)10 + (+4)10 = 001112 + 001002 = 010112

The resultant sum contains 5 bits. So, there is no carry out from sign bit. The sign bit ‘0’ indicates that
the resultant sum is positive. So, the magnitude of sum is 11 in decimal number system. Therefore,
addition of two positive numbers will give another positive number. As another example, let us perform
the addition of two decimal numbers −7 and −4 using 2’s complement method. The 2’s complement
representation of −7 and −4 with 5 bits each are shown below.

−710 = 110012

−410 = 111002
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 65

The addition of these two numbers is,

(−7)10 + (−4)10 = 110012 + 111002 = 1101012

The resultant sum contains 6 bits. In this case, carry is obtained from sign bit. So, we can remove it such
that the resultant sum after removing carry is 101012 . The sign bit ‘1’ indicates that the resultant sum is
negative. So, by taking 2’s complement of it we will get the magnitude of resultant sum as 11 in decimal
number system. Therefore, addition of two negative numbers will give another negative number.

5.2.3.4 Subtraction Operation

Consider the two signed binary numbers A and B, which are represented in 2’s complement form. We
know that 2’s complement of positive number gives a negative number. So, whenever we have to subtract
a number B from number A, then take 2’s complement of B and add it to A. Mathematically we can write
it as,

A − B = A + 20s complement of B

Similarly, if we have to subtract the number A from number B, then take 2’s complement of A and add it
to B. So, mathematically we can write it as,

B − A = B + 20s complement of A

The subtraction of two signed binary numbers is similar to the addition of two signed binary numbers.
But, we have to take 2’s complement of the number, which is supposed to be subtracted. This is the
advantage of 2’s complement technique. We follow the same rules of addition of two signed binary
numbers. As an example let us perform the subtraction of two decimal numbers +7 and +4 using 2’s
complement method. The subtraction of these two numbers is

(+7)10 − (+4)10 = (+7)10 + (−4)10

The 2’s complement representation of +7 and −4 with 5 bits each are shown below.

+710 = 001112

−410 = 111002
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 66

Here, the carry obtained from sign bit. So, we can remove it. The resultant sum after removing carry is

(+7)10 + (−4)10 = 001112 + 111002 = 000112

The sign bit ‘0’ indicates that the resultant sum is positive. So, the magnitude of it is 3 in decimal
number system. Therefore, subtraction of two decimal numbers +7 and +4 is +3. As another example,
let us perform the subtraction of two decimal numbers +4 and +7 using 2’s complement method. The
subtraction of these two numbers is

(+4)10 − (+7)10 = (+4)10 + (−7)10

The 2’s complement representation of +4 and −7 with 5 bits each are shown below.

+410 = 001002

−710 = 110012

In this case the sum becomes,

+410 + −710 = 001002 + 110012 = 111012

Here, carry is not obtained from the sign bit. The sign bit ‘1’ indicates that the resultant sum is negative.
By taking 2’s complement of it we will get the magnitude of resultant sum as 3 in decimal number
system. Therefore, subtraction of two decimal numbers +4 and +7 is −3.

5.2.4 Reflected Binary (or Gray) Code

This an ordering of the binary numeral system such that two successive values differ in only one bit
(binary digit). Gray codes are very useful in the normal sequence of binary numbers generated by the
hardware that may cause an error or ambiguity during the transition from one number to the next. This
means the Gray code can eliminate this problem easily since only one bit changes its value during any
transition between two numbers. The following table shows the first sixteen (or four-bit) Gray codes
along with their corresponding decimal and binary.

There are several ways of converting between binary and Gray code, such as using Karnaugh map and
exclusive OR operation. We will deal with these methods in a few lectures to comes.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 67

Table 5.3: Gray codes and their corresponding binary and decimal equivalents.
Gray Code Binary Decimal
0000 0000 00
0001 0001 01
0011 0010 02
0010 0011 03
0110 0100 04
0111 0101 05
0101 0110 06
0100 0111 07
1100 1000 08
1101 1001 09
1111 1010 10
1110 1011 11
1010 1100 12
1011 1101 13
1001 1110 14
1000 1111 15