Introduction to Laboratory Equipment Lab 1

Lab 1 Introduction to Laboratory Equipment

Objective
To understand the working and purpose of the equipment present in the Lab.

The Trainer Board

In the Digital Logic labs, the primary piece of equipment that you will be dealing with is the trainer
Board. A trainer board is essentially a collection of most of the tools that are typically required
when working with logic circuits. There are three types of trainer boards present in the lab. All
three are equipped with the following.
1. Breadboard
2. Power Supply for ICs
3. Logic Switches
4. LED output
5. Seven Segmented Display
6. Clock

1. The Breadboard
While most of the circuits you come across in your
everyday life are in the form of Printed Circuit Boards
(PCBs), every circuit starts off as an implementation on
a breadboard. A breadboard is a prototyping board
made of insulated material with a perforated top in
which wires and components can be inserted. The
perforations in the board are connected in a special
manner through internal wiring at the bottom of the
board. The fact that wires and components are inserted,
and not soldered, means they can be easily removed,
replaced or have their interconnections altered easily.
In contrast, to make changes on a PCB, a new PCB
needs to be designed which incurs costs in terms of both
time and resources. Therefore, breadboards are ideal for
testing and lab work since, in both cases, circuits
undergo a lot of changes. Figure 1 shows the layout of

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Introduction to Laboratory Equipment Lab 1

a basic breadboard. In order to allow for large circuits to be made, as is the case with some of the
later labs, two such breadboards are sometimes placed.

Figure 2a shows the manner in which the inner perforations are connected. Each row of 5 holes
is “shorted”, that is, each hole in a row is connected to each other through an internal wire. The
large rectangle in the center represents a grove. It should be noted here that holes on one side of
the grove are not connected to the holes on the other side. Figure 2b shows the connections of the
outer perforations. The holes are shorted column wise with no connections between the adjacent
columns. Also, while the number of perforations in a column may vary with the length of the
breadboard, there is always a break in connection at the half way point in a column as shown in
the figure. This means that each column is essentially split into two smaller columns.

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Introduction to Laboratory Equipment Lab 1

2. Power Supply for ICs

In digital logic, the components that you will be dealing with
mostly are Integrated Circuits (ICs). There are several different
types of ICs, each with its unique functionality. Figure 3 shows
the structure of a typical IC chip package (called IC for
convenience). Every IC has a grove at the top which is used to
determine its orientation. Figure 4 shows the manner in which
an IC is placed on the breadboard. It is recommended to ensure
that the groove on the IC is pointing towards the left as
illustrated in the figure.
ICs are active elements. This means that they require to be
“powered up” before they can be used. Therefore, every IC, no matter what its functionality, will
always have two special pins labeled Vcc and Ground (or Gnd). Ground is to be connected to the
Gnd supply of the trainer board while Vcc is to be connected to the 5V supply. Ignore the 12V and
the -12V supplies on the board.

It should be noted here that voltage is a

relative quantity. The voltage at any point
can only be expressed as the amount of
difference between that point and the
voltage at a reference point. The reference
point that you will be using is called
Ground. Ground is all the connections on
the trainer board that are assumed to be at
0V and all voltages marked on the trainer
board are with reference to Ground pins.
For example, the pin marked +5V is at a
voltage that is 5 Volts greater than the Ground pin. This also means that if the pin marked +5V is
assumed to be at 0V, then the Ground pin will be at -5V.

When using multiple trainer boards, make sure that the ground pin of the trainer boards are shorted
to ensure that the reference voltage is the same throughout the circuit.

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Introduction to Laboratory Equipment Lab 1

3. Logic Switches
The inputs to a logic circuit are composed of a collection
of ON/OFF signals. An ON signal (or logic ‘1’) is
generated by applying +5V to an input pin while an OFF
signal (or logic ‘0’) is generated by applying 0V to an
input pin. Figure 5 shows the internal structure of a
switch in the ON and OFF state. When the switch is
closed (by moving the switch down), it outputs +5V
while when the switch is opened (by moving it up), the
output of the same pin is now 0V.
This is called “Positive Logic Connection”. To provide
these ON/OFF signals, the trainer boards are equipped with the following logic switches:

(i) Inverting switches (set A/set B)

These switches have 2 outputs. The first output is the normal output, which follows the convention
described above. The second (inverted) output is the inverse of the first output, that is, if the normal
output is 5V, then the inverted output is 0V and vice versa. The inverted output is typically denoted
with an apostrophe (‘).

(ii) Non Inverting Switches

These switches have a single output, which follows the normal convention as stated above.

(iii)Debouncing Switches
When a normal switch is “thrown”, that is its state is changed, the resulting output voltage does
not immediately go to and stay at the new value. Rather, it oscillates between 5V and 0V for a
short period before settling at desired output. In sensitive circuits, this will lead to the circuit
producing incorrect results. A debouncing switch employs a circuit to remove these oscillations
and produce a clean transition when the switch is thrown.

4. LED output
The outputs of logic circuits, like the inputs, are composed of ON/OFF signals. They can be
verified by using the LEDs available on the trainer boards. LED stands for Light Emitting Diode;
a two terminal device only conducts in one direction, as is the case with a typical diode. They
convert electrical energy into light energy. The conversion results in a drop in voltage across the
terminals of the LED, which is typically around 2V. LEDs offer a big advantage over traditional

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Introduction to Laboratory Equipment Lab 1

bulbs in that they consume negligible amount of power. The disadvantage of LEDs is their inability
to withstand high voltages or currents. Therefore, when using an LED, always connect a resistor
(100-200Ω) in series with it.

The LEDs present in the trainer board already have one terminal connected to the ground and
resistor connected to the other terminal internally. Therefore, you do NOT need to connect a
resistor when using the LEDs on the trainer board. To test an output of an IC, connect it directly
to the input terminal of an LED made available on the trainer board. If an LED turns on, then the
output state at that pin is ON (+5V). If it remains off, then the pin is in OFF state (0V). Remember
to turn on the trainer board before using the LEDS (in case you are using an external supply to
power up your circuit).

5. Seven Segmented Display

The seven-segmented display allows outputs to be viewed in decimal form. It takes 4 inputs
(binary) and, depending on their state, turns on LEDs in the display to show the corresponding
digit. For example, if the input to the display is 0111, then the display will show the number 7. If
the input to the display is a number >9 (1001 in binary), the display will not show a number.
Instead, it will display a unique character corresponding to that binary input. To turn off the
display, apply the input 1111 to it.

6. Clock
The trainer board provides a square wave that oscillates between a minima of 0V and a maxima of
5V. This is called a clock. The clock is used to drive “sequential” logic devices, which you will
come across in the later labs. Essentially, this clock is used for the same purpose as the clock in
you computers. The trainer board provides the option of varying the frequency of this clock, but
the amplitude is fixed.

The Digital Multi Meter (DMM)

The multimeter, as suggested by its name, is used to measure multiple parameters in a circuit. It
can be used to measure voltage, current, resistance, capacitance and it even has a mode for
checking for short circuits. In logic circuits, you will typically be using only the voltage and the
short circuit mode.

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Introduction to Laboratory Equipment Lab 1

Task: Resistors Color Marking

Resistors have color markings representing resistance value. You can find a resistance color map,
shown below, to help you read color marking on resistor. We will take several resistors to practice
reading resistance values two different ways – reading color markings and using the Multimeter.
Follow the steps:
1. Find 7 resistors with different color markings from your parts.
2. Read the resistance of the resistors by referring to the color marking chart.
3. Place them in order on the Breadboard, and mark their color in the table.
4. Use Multimeter to check the resistance value using the color marking. Write the value to the
table.

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Introduction to Laboratory Equipment Lab 1

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Introduction to Logic Gates Lab 2

Lab 2 Introduction to Logic Gates

OBJECTIVE
Familiarization with the AND, OR, NOT, and XOR gates.

TASK 1: LOGICAL “AND” OPERATION

The AND operation produces an output of 1 (or high) when all of the inputs are 1 (or high). It
produces an output of 0 (or low) when any or all of the inputs are 0 (or low). Symbol for “Two
Input AND Gate” and “Truth Table” for AND operation is as given below:

Symbol of AND gate (7408) Truth Table for AND operation

Inputs Outputs

Desired Observed
A B
x= A . B
0 0 0
0 1 0
1 0 0
1 1 1

PROCEDURE
1. Insert the IC 7408 on the trainer’s breadboard.
2. Use any two Logic Switches (S2 to S9) of the trainer for Input and any one of the LEDs
(L0 to L15) of the trainer for Output indication.
3. Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
4. By setting various combinations of the two switches verify that the output of the AND
gate is in accordance with the Truth Table shown above. Record your observation.

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Introduction to Logic Gates Lab 2

TASK 2: LOGICAL “OR” OPERATION

The OR operation produces an output of 1 (or high) when any of the inputs is 1 (or high). It
produces an output of 0 (or low) when all of the inputs are 0 (or low). Symbol for “Two Input
OR Gate” and “Truth Table” for OR operation is as given below:

Symbol of OR gate (7432) Truth Table for OR operation

Inputs Outputs

Desired Observed
A B x= A + B
0 0 0
0 1 0
1 0 0
1 1 1

PROCEDURE
1. Insert the IC 7432 on the trainer’s breadboard.
2. Do the same procedure and verify the results.

TASK 3: LOGICAL “NOT” OPERATION

The NOT operation produces an output of 1 (or high) when the inputs is 0 (or low). It produces
an output of 0 (or low) when the inputs is 1 (or high). Symbol for “ NOT Gate” and “Truth
Table” for NOT operation is as given below:

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Introduction to Logic Gates Lab 2

Symbol of NOT gate (7404) Truth Table for NOT operation

Inputs Outputs

Desired Observed
A
x= A’
0 1
1 0

PROCEDURE
1. Insert the IC 7404 on the trainer’s breadboard.
2. Do the same procedure and verify the results.

TASK 4: LOGICAL “XOR” OPERATION

The XOR operation produces an output of 1 (or high) when the inputs are even 1 . It produces an
output of 0 (or low) when all of the inputs are odd 1. Symbol for “Two Input xOR Gate”
and “Truth Table” for XOR operation is as given below:

Symbol of XOR gate (7486) Truth Table for XOR operation

Inputs Outputs

Desired Observed
A B x= A Θ B
0 0 0
0 1 1
1 0 1
1 1 0

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Introduction to Logic Gates Lab 2

PROCEDURE
1. Insert the IC 7486 on the trainer’s breadboard.
2. Do the same procedure and verify the results.

TASK 5
 Repeat Task for IC 7400, IC 7402. Draw truth table and show your results to lab
instructor [For IC configuration see datasheet].

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Universality of NAND and NOR Gates Lab 3

Lab 3 Universality of NAND and NOR Gates

OBJECTIVE
To learn the implementation of any logic expression by using only NAND or NOR gates.

THEORY
Digital circuits are more frequently constructed with NAND or NOR gates than with AND and
OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the
basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR
gates in the design of digital circuits, rules and procedures have been developed for conversion
from Boolean function given in terms of AND, OR, and NOT into equivalent NAND and NOR
logic diagram.

TASK 1: NAND GATE IMPLEMENTATION OF BOOLEAN FUNCTIONS

If we can show that the logical operations AND, OR, and NOT can be implemented with NAND
gates, then it can be safely assumed that any Boolean function can be implemented with NAND
gates. Figure-1 below shows such implementation:

Figure 1a: AND gate operation

Figure 1b: OR gate operation

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Universality of NAND and NOR Gates Lab 3

Figure 1c: NOT gate operation

PROCEDURE
1. Insert the IC on the trainer’s breadboard.
2. Use any one or more of the NAND gates of the IC for this experiment.
3. Any one or more Logic Switches of the trainer (S2 to S9) can be used for input to the
NAND gate.
4. For output indication, connect the output pin of the circuit to any one of the LEDs of the
trainer (L0 to L15).
5. Connect the circuit as per Fig. 1(a) above.
6. Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
7. By setting the switches to 1 and 0, verify that the output of the circuit conforms to that of
an AND gate. Record your observation in the table below:

Inputs Output
A Desired Observed
B x=A.B
0 0 0
0 1 0
1 0 0
1 1 1

 Verify OR gate operation using NAND gates (See Fig. 1b).

 Show your results to the lab instructor.

Inputs Output
A Desired Observed
B x=A+B
0 0 0
0 1 1
1 0 1
1 1 1

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Universality of NAND and NOR Gates Lab 3

 Verify NOT gate operation using NAND gates (See Fig. 1c).
 Show your results to the lab instructor.

Inputs Output
A Desired Observed
X=A'
0 1
1 0

TASK 2: ALTERNATE LOGIC GATE REPRESENTATION

It is becoming increasingly more common to use alternate logic symbols in logical circuit
diagrams, in addition to the standard symbols. Proper use of alternate gate symbols in the circuit
diagram can make the circuit operation much clearer.

Alternate symbols of the basic gates are given below. Find out which gate each of these
represents.

Inputs Output
A Observed
B
0 0
0 1
1 0
1 1

Above mentioned alternate logic gate is equivalent to _________ gate.

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Universality of NAND and NOR Gates Lab 3

Inputs Output
A Observed
B
0 0
0 1
1 0
1 1

Above mentioned alternate logic gate is equivalent to _________ gate.

Inputs Output
A Observed
0
1

Above mentioned alternate logic gate is equivalent to _________ gate.

LAB ASSIGNMENT

1. Implement AND, OR and NOT operation using NOR gate. Show truth table and
logic diagram.

2. Find the equivalence of the following alternate logic gate. Also show truth table.

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 Minimization of Boolean Functions Lab 4

Lab 4 Minimization of Boolean Functions

OBJECTIVE
To understand the minimization of Boolean functions and their hardware implementation.

TASK 1:

1. Write the Boolean expression of the following two functions. Simplify the expression using
algebraic manipulation and draw the logic diagram.
F (A, B, C) = Σ (2, 3, 7)
G (A, B, C) = Σ (4, 5, 7)

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Minimization of Boolean Functions Lab 4

2. Mention the number of literals and gates needed for implementing the above function in
hardware.

TASK 2:
Implement the Boolean functions in hardware you simplified in your Task 1. Make truth table
and Schematic. Mention what and how many gates you would be using?

Truth Table:

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Minimization of Boolean Functions Lab 4

Schematic:

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Minimization of Boolean Functions Lab 4

TASK 3:
Implement the reduced expressions in Sum-of-Product (SOP) and Product-of-Sum (POS) forms
using AND, OR, and NOT gates. Show proper wiring in prototyping your circuit.

School of Systems and Technology Digital Logic Design Lab 4

Binary-to-Gray and Gray-to-Binary Code Conversion Lab 5

Lab 5 Binary-to-Gray and Gray-to-Binary Code Conversion

OBJECTIVE
To understand the binary codes for decimals and their hardware realization.

TASK 1:
Implement a gray to binary and binary to gray code converter. Make a truth table for both the
codes by filling in the following tables and Simplify the expressions for W,X,Y,Z in terms of
A,B,C,D and vice versa.( Use backside of the page if necessary). Also give some applications in
which gray code could be used.

Binary Gray
Decimal
A B C D W X Y Z

HINT:
The inputs and outputs are
of 4-bit each. You will
have to make 4 K-Maps
Arrive at the simplest
expression for each
output.

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Binary-to-Gray and Gray-to-Binary Code Conversion Lab 5

W=

X=

Y=

Z=

Gray Binary
Decimal
W X Y Z A B C D

HINT:
The inputs and outputs are
of 4-bit each. You will
have to make 4 K-Maps
Arrive at the simplest
expression for each
output.

A=
B=
C=
D=

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Binary-to-Gray and Gray-to-Binary Code Conversion Lab 5

TASK 2:
Draw the logic diagram for the Binary-to-Gray and Gray-to-Binary code converters using two-
input gates in the space provided below.

TASK 3:
Implement the Binary to Gray Code Converter using exclusive- OR gates. Make the Schematic
Diagram. Show the results to your Teacher. What and how many gates did you use? Use LEDs
to show input-output relationship.

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Binary-to-Gray and Gray-to-Binary Code Conversion Lab 5

TASK 4:
Implement the Gray to Binary Code Converter using exclusive- OR gates. Make the Schematic
Diagram. Show the results to your Teacher. What and how many gates did you use? Use LEDs
to show input-output relationship.

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Binary-to-Gray and Gray-to-Binary Code Conversion Lab 5

TASK 5:
Now cascade the two circuits in series by connecting the outputs of binary-to-gray converter to
the inputs of the gray-to-binary converter. You should be able to get the binary input at output as
well. Show the results to your Lab Engr. Use LEDs to show input-output relationship.

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BCD to Seven Segment Display Lab 6

Lab 6 BCD to Seven Segment Display

OBJECTIVE
To learn about BCD to Seven Segment Display Code.

THEORY
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different digital systems. Some times it becomes necessary to use
output one system as input to another system. A conversion circuit must be inserted between the
two systems, if each uses different code for the same information. When a decimal number is
decoded such that each digit of the number is represented by a 4-bit binary number, it is called a
8421 Binary Coded Decimal Code or more simply a BCD code. Here , ten out of sixteen
possible combinations of the code are selected to represent decimal 0 through 9. Most
commonly used BCD codes are given below:

DECIMAL BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

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BCD to Seven Segment Display Lab 6

TASK 1:
Most Digital equipment has some means for displaying information in a form that can be
understood readily by the user or operator. One of the simplest and most popular methods for
displaying numerical digits uses a 7-segment configuration. To form decimal characters 0
through 9 and some times hex characters A through F. A BCD to 7-Segment Driver (IC 7447) is
used to take four bit BCD input and provide the outputs that will pass current through the
appropriate segment of the display to generate desired output/ number. Truth Table for Active
High and Active Low cases are shown below:

INPUT –BCD Deci Output- Seven Segment Decoder (Active High) Display
So S1 S2 S3 mal a b c d e f g Output
0 0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 1 1 0 1 1 0 0 0 0 1
0 0 1 0 2 1 1 0 1 1 0 1 2
0 0 1 1 3 1 1 1 1 0 0 1 3
0 1 0 0 4 0 1 1 0 0 1 1 4
0 1 0 1 5 1 0 1 1 0 1 1 5
0 1 1 0 6 0 0 1 1 1 1 1 6
0 1 1 1 7 1 1 1 0 0 0 0 7
1 0 0 0 8 1 1 1 1 1 1 1 8
1 0 0 1 9 1 1 1 0 0 1 1 9

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BCD to Seven Segment Display Lab 6

INPUT –BCD Deci Output- Seven Segment Decoder (Active Low -IC Display
mal 7447) Output
So S1 S2 S3 a b c d e f g
0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 1 0 0 1 1 1 1 1
0 0 1 0 2 0 0 1 0 0 1 0 2
0 0 1 1 3 0 0 0 0 1 1 0 3
0 1 0 0 4 1 0 0 1 1 0 0 4
0 1 0 1 5 0 1 0 0 1 0 0 5
0 1 1 0 6 1 1 0 0 0 0 0 6
0 1 1 1 7 0 0 0 1 1 1 1 7
1 0 0 0 8 0 0 0 0 0 0 0 8
1 0 0 1 9 0 0 0 1 1 0 0 9

Figure 1: BCD to Seven Segment Converter Circuit.

The segments of Seven Segment display are made of LEDs. Depending on the arrangements of
the LEDs, the display could be Common Anode or Common Cathode type. We are using

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BCD to Seven Segment Display Lab 6

common anode type of display, which would require that either pin 3 or pin 8 is connected to
Vcc and the input is active low.

Procedure
1. Wire the circuit as per figure 1 above. Connect pin 3 or pin 8 to Vcc.
2. By setting various combinations of the switches verify the result.

TASK 2:
Design a circuit which calculates 9’s complement of a four bit number (BCD) and show the
results on seven segment display.

Truth Table

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BCD to Seven Segment Display Lab 6

Logic Diagram

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Implementation of Full Adder and Parallel Adder Lab 7

Lab 7 Implementation of Full Adder and Parallel Adder

OBJECTIVE
(1) To learn Half and Full Adder Operations.
(2) To learn 4- Bit Binary Parallel Adder Operations.

THEORY
a. Half Adder: The possible operations, when we want to add only two bits, would be the
followings:
0+0=0
0+1=1
1+0=1
1 + 1 = 0 & Carry 1
Above mentioned operation could be performed by a Half Adder circuit.

b. Full Adder : We know that in practice, all addition operations must take into account the
Carry bit (or digit) from the previous operation. Adders in digital computers also take into
account the Carry bit from last operation and add it with the Augend and Addend bits of the
present operation to complete the addition operation. The possible operations are:
0 + 0 + 0 (carry) = 0
0 + 0 + 1 (carry) = 1
0 + 1 + 0 (carry) = 1
0 + 1 + 1 (carry) = 0 & carry 1 (to be added to next higher digit)
1 + 1 + 0 (carry) = 0 & carry 1 (to be added to next higher digit)
1 + 1 + 1 (carry) = 1 & carry 1 (to be added to next higher digit)
The adder that performs the addition of three bits (two significant bits and a previous carry)
is called a Full Adder.

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Implementation of Full Adder and Parallel Adder Lab 7

TASK 1: HALF ADDER.

Arbitrarily assign symbols A and B to the two inputs and S (for sum) and Cout (for Carry) to the
two outputs. Truth table for Half Adder as shown below:-

Input Output Output

Desired Observed

A B S Cout S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Table 1: Truth Table for Half Adder operation

The simplified Boolean function for the two outputs can be written from this truth table as:-
S = A'.B +A.B' or A⊕B
Cout = A.B

The circuit diagram for the Half Adder to implement above mentioned Boolean function could
be quite a few. We will however verify only one.

Figure 1: Half Adder using AND and XOR gates.

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Implementation of Full Adder and Parallel Adder Lab 7

PROCEDURE
Implement the circuit as per figure 1 above.By setting various combinations of the two switches
verify that the output of the circuit is in accordance with the Truth Table shown above. Record
your observation.

TASK 2: FULL ADDER.

As mentioned in the beginning, a full-adder is a combinational circuit that form the arithmetic
sum of three input bits (two significant bits and a previous carry bit ) and two output bits. We
arbitrarily assign symbols A and B to the two significant bit inputs and Cin for the Carry from
the previous lower significant position, and S (for sum) and Cout (for Carry) to the two outputs.
Truth table for the Full Adder is shown below

Input Output Output

Desired Observed
A B Cin S Cout S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Simplified Boolean function for the two outputs can be written from this truth table as:-

S = A ⊕ B ⊕ Cin

Cout = ( A ⊕ B) Cin +A.B

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Implementation of Full Adder and Parallel Adder Lab 7

The circuit diagram for the Full Adder is as under:

Figure 2: Full Adder comprising of two Half Adders and an OR gate.

PROCEDURE
Implement the Full Adder circuit as per figure 2 above.By setting various combinations of the
two switches verify that the output of the circuit is in accordance with the Truth Table shown
above. Record your observation.

TASK 3: 4 BIT BINARY PARALLEL ADDER

Figure 3 : IC 7483 Internal Functional Structure

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Implementation of Full Adder and Parallel Adder Lab 7

Adders that are available in integrated circuit form are parallel binary adders. A 4-Bit parallel
adder actually consists of four full adders connected in parallel. The carry output of each adder is
internally connected to the carry input of the next higher order adder. Fig 5 shows the internal
functional structure of 7483 IC in which 4 full adders are shown as separate entity. Figure 6 is
connection diagram for full adder function.

Figure 4: Connection Diagram for 4-Bit Parallel Adder

PROCEDURE:
1. Wire the circuit as per figure 4 above.
2. Use first four Logic Switches of the trainer for the inputs A0 to A3, and next four switches
for inputs B0 to B3.
3. Connect Cin (pin 13) to GND (we are assuming initial carry to be zero).
4. Use first four LEDs of the trainer to indicate Sum outputs S0 to S3, and another LED to
indicate status of the most significant carry bit Cout.

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 Implementation of Full Adder and Parallel Adder Lab 7

5. Connect +5V to pin 5 (Vcc) and Ground to pin 12 (GND) of the ICs.
6. By setting various combinations of the two sets of input switches verify that the output of the
circuit is in accordance with the Table shown below (only few of the possible additions have
been shown here). Record your observation.

Inputs Desired Output Observed Output

Decimal Decimal
Binary Augend Binary Addend Binary Output Binary Output
Value value

A3 A2 A1 A0 B3 B2 B1 B0 A B Co S3 S2 S1 S0 Sum Co S3 S2 S1 S0

0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 2
0 0 1 1 0 0 0 1 3 1 0 0 1 0 0 4
0 1 0 0 0 0 1 0 4 2 0 0 1 1 0 6
0 1 0 0 0 1 0 0 4 4 0 1 0 0 0 8
0 1 0 1 0 1 0 0 5 4 0 1 0 0 1 9
0 1 0 1 0 1 0 1 5 5 0 1 0 1 0 10
1 0 0 0 0 1 0 0 8 4 0 1 1 0 0 12
1 0 0 1 0 1 1 0 9 6 0 1 1 1 1 15
1 0 0 1 1 0 0 0 9 8 1 0 0 0 1 17
1 0 0 1 1 0 0 1 9 9 1 0 0 1 0 18

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Implementation of Full Subtractor and Parallel Subtractor Lab 8

Lab 8 Implementation of Full Subtractor and Parallel Subtractor

OBJECTIVE
(1) To learn Half and Full Subtractor Operations.
(2) To learn 4- Bit Binary Parallel Subtractor Operations.

THEORY
a. Half Subtractor :
In binary subtraction, when larger digit is to be subtracted from a smaller digit, it becomes
necessary to BORROW a value from the next higher position. Thus the binary subtraction results
in the following basic operations
0-0=0
0 - 1 = 1 , with a 1 borrowed from next higher digit position (which became 11 binary
on reaching current position).
1-0=1
1-1=0
The arithmetic element that performs this subtraction operation is called a Half Subtractor.

b. Full Subtractor :
When we have borrowed a value from a higher position, then it must be accounted for when
subtraction is performed at that higher position. The way it is done can be explained with the
following example:-
Posn 4 Posn 3 Posn 2 Posn 1 Posn 0
Minued 26 = 1 1 0 1 0
Subtrahend - 12 = 0 1 1 0 0
------- ------------------------------------------
14 = 0 1 1 1 0

School of Systems and Technology Digital Logic Design Lab 1

Implementation of Full Subtractor and Parallel Subtractor Lab 8

At position 2 we borrowed a “1” from position 3 to carry out subtraction. When we move to
position 3 for subtraction, the position 2 should have returned the borrowed “1”, which will be
added to the Subtrahend at position 3. (Note: Minuend at Posn3 will remain 1).

We need to have two arrangement to carry out above mentioned action: first, in-addition to the
subtraction result (call it Do), the Position2 should give out another output as high (or 1) (call it
Bo- borrow out) which would indicate it’s obligation to return the borrowed “1” to position 3;
second, position three should have some input arrangement (call it Bin – borrow in), which
would take the “1” returned by position 2 and add it to the Subtrahend of position 3.
The possible combinations for full subtraction would be;
0 - 0 with a 0 as Bin = 0
0 - 0 with a 1 as Bin = 1, only if a 1 is borrowed from next higher digit position.
0 - 1 with a 1 as Bin = 0, only if a 1 is borrowed from next higher digit position.
0 - 1 with a 1 as Bin = 0, only if a 1 is borrowed from next higher digit position.
1 - 0 with a 0 as Bin = 1
1 - 0 with a 1 as Bin = 0
1 - 1 with a 0 as Bin = 0
1 - 1 with a 1 as Bin = 1, only if a 1 is borrowed from next higher digit position.

The arithmetic element that performs this subtraction operation is called a Full Subtractor.

School of Systems and Technology Digital Logic Design Lab 2

Implementation of Full Subtractor and Parallel Subtractor Lab 8

TASK 1:
Implement Half subtractor .

Logic Diagram:

Truth Table:

School of Systems and Technology Digital Logic Design Lab 3

Implementation of Full Subtractor and Parallel Subtractor Lab 8

TASK 2:
Implement Full Subtractor

Logic Diagram:

Truth Table:

School of Systems and Technology Digital Logic Design Lab 4

Implementation of Full Subtractor and Parallel Subtractor Lab 8

TASK 3:
Implement 4-bit parallel subtractor operation using given IC’s. Show truth table and logic
diagram.

Logic Diagram:

Truth Table:

School of Systems and Technology Digital Logic Design Lab 5

Implementation of Encoder and Decoder Lab 9

Lab 9 Implementation of Encoder and Decoder

OBJECTIVE
To learn about Encoder and Decoder.
THEORY
 An encoder circuit has more input lines and fewer output
lines.
 A decimal to BCD encoder (10 line to 4 line) will convert
(at any one time) one active input out of ten to a BCD
code output.
 An octal-to-binary encoder (8 line to 3 line) will convert Figure 1 4-to-2 line encoder
(at any one time) one-of-eight inputs to a binary code
output
 A decoder circuit few input lines and more output lines.
 A binary-to-octal decoder converts 3 binary bits into 8
outputs (only one which will be active at one time)
 A BCD decoder converts a 4-bit BCD code on into 10
output outputs (only one which will be active at one
time).
 A hexadecimal decoder converts a 4-bit binary code on
the input to a 1-of-16 output. Figure 2 2-to-4 line decoder

 Decoders are often used in microprocessor systems to decode the address information from
the microprocessor in order to select the correct memory chip.

School of Systems and Technology Digital Logic Design Lab 1

Implementation of Encoder and Decoder Lab 9

TASK 1: ENCODER
IC 74148 is a 8- Line-to- 3-line (octal to binary) Priority Encoder. It has 8 Inputs (0-7), an
Enable Input EI, an Enable Output EO, 3 Output (A0-A2), and a Gs Output. Details as under:
 A0-A2 outputs reflect a code that is equal to the highest valued active input.
 Gs output goes low any time any of the input goes low (this low signal is used for
interrupt request to CPU, when connected for the purpose).
 EI and EO are used for cascading more than one 74148 together.
Functional block diagram of IC 74148 is attached. Connection diagram and Truth table of is
shown below:

INPUT OUTPUT
EI 0 1 2 3 4 5 6 7 A2 A1 A0 Gs Eo
0 X x x x x x X 0 0 1
0 x x x x x x 0 1 0 1
0 x x x x x 0 1 1 0 1
0 x x x x 0 1 1 1 0 1
0 x x x 0 1 1 1 1 0 1
0 x x 0 1 1 1 1 1 0 1
0 x 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 0 1

Wire the circuit as per figure above and fill in the blanks in the truth table.

School of Systems and Technology Digital Logic Design Lab 2

Implementation of Encoder and Decoder Lab 9

TASK 2: DECODERS
IC 74138 has been used here as a decoder. It has 3-Select Inputs and 8- Data Outputs. Functional
block diagram of IC 74138 is attached. Note that the IC 74138 has Enable Inputs which we
will not use during decoder operation, therefore we will keep G1 as high and G2A and G2B as
low so that the output of Enable gate remains always high and does not interfere with our desired
result. Also note that the output of the IC is active low. Connection diagram and Truth table of
the IC 74138 when used as decoder is shown below:

Note: Output of the IC 74138 is active low , so the output line having a Zero in the Truth
Table will be selected
SELECT INPUT DATA OUTPUT
C B A O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1

Wire the circuit and verify the results.

School of Systems and Technology Digital Logic Design Lab 3

Implementation of Encoder and Decoder Lab 9

TASK 3:
Design priority encoder. Show all steps and wire on trainer board.

School of Systems and Technology Digital Logic Design Lab 4

Implementation of Multiplexer and Demultiplexer Lab 10

Lab 10 Implementation of Multiplexer and Demultiplexer

OBJECTIVE:
To learn about Multiplexer and Demultiplexer.

THEORY:

A. Multiplexer
1. The multiplexer circuit is used to place two or more digital signals (from two or more sources)
onto a single line, by placing them there at different time intervals (technically it is known as
time-division- multiplexing).
2. The multiplexer (also known as data selector) will select data from several transmission lines
to be gated to the single output transmission line.
3. Tthe multiplexer will have a number of control inputs that are used to select the appropriate
data channel for input.
4. The number of data inputs is equal to 2n where n is the number of control select leads.
5. A multiplexer can be used to convert parallel data to serial data.

School of Systems and Technology Digital Logic Design Lab 1

Implementation of Multiplexer and Demultiplexer Lab 10

B. Demultiplexer
1. A demultiplexer (data distributor) will receive information from a single line and selectively
transmits it to several output lines/channels (one at a time).
2. Demultiplexer has several control select lines which are used to determine (or select) the
output transmission path.
3. The number of data output lines is 2n , where N is the number of control select leads.
4. Demultiplexers are used to convert serial data to parallel data.

TASK 1: MULTIPLEXER.
IC 74151 is a 8-to-1-Line Multiplexer. It has following features:-
1. 8 Data Inputs (DO- D7 ).
2. Three Select Inputs (A,B,C) .
3. An Enable (or Strobe) G
4. A one bit output Y (and its complement W)

School of Systems and Technology Digital Logic Design Lab 2

Implementation of Multiplexer and Demultiplexer Lab 10

Procedure:
Wire the circuit as per figure above. Connect “ Clock Input” (very low frequency) to Input pins
of the IC (D0 – D1) and see if the Output LED is pulsating. Confirm your finding on the truth
table. The truth table is shown below:

Select Strobe Output Output

C B A G (or S) Y Observed
0 0 0 0 Output Y is linked with input present at D0
0 0 1 0 Output Y is linked with input present at D1
0 1 0 0 Output Y is linked with input present at D2
0 1 1 0 Output Y is linked with input present at D3
1 0 0 0 Output Y is linked with input present at D4
1 0 1 0 Output Y is linked with input present at D5
1 1 0 0 Output Y is linked with input present at D6
1 1 1 0 Output Y is linked with input present at D7

School of Systems and Technology Digital Logic Design Lab 3

Implementation of Multiplexer and Demultiplexer Lab 10

TASK 2: DEMULTIPLEXER
A 1-Line-to-8-Line demultiplexer distributes one input to 8 output lines. IC 74138 which was
used as a decoder in the last experiment will be used here as Demultiplexer. The only difference
between the previous circuit and present circuit will be addition of an INPUT (through Enable
AND gate) to the 4th pin of all the 8 NAND gates. The A, B and C inputs will serve as SELECT
input ( to select a particular output line).

Note that the Enable Inputs of IC 74138 was not used during decoder operation. We will
now use G2B pin of the IC for Data/Signal Input. We therefore need to keep pins G1 as high
and G2A as low, so that the Input Data/Signal remains present at output of Enable gate and
consequently on the 4th input pin of all the 8 NAND gates.

Connection diagram and Truth table of the IC 74138 when used as demultiplexer is shown
below. Clock signal (very low frequency) has been used as Input (so that blinking of the LEDs
can be observed):

Note: Output of the IC 74138 is active low , so the output line having a Zero in the Truth
Table will be selected.

School of Systems and Technology Digital Logic Design Lab 4

Implementation of Multiplexer and Demultiplexer Lab 10

Input Output
C B A O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1

TASK 3: DATA COMMUNICATION USING MULTIPLEXER & DEMULTIPLEXER

Multiplexer IC 74151 and Demultiplexer IC 74138 has been utilized to demonstrate single-line
data communication. The 3-bit select code will determine which data input will be steered to the
Y output of the Demultiplexer.

School of Systems and Technology Digital Logic Design Lab 5

Implementation of Multiplexer and Demultiplexer Lab 10

Select Applied Signal Observed When Clock Signal is

at Data Input Signal Out at Applied At All of D
Pin Output Pin Pins of MUX
C B A D Y Observed Output at Pin
of DEMUX
0 0 0 D0 Y0
0 0 1 D1 Y1
0 1 0 D2 Y2
0 1 1 D3 Y3
1 0 0 D4 Y4
1 0 1 D5 Y5
1 1 0 D6 Y6
1 1 1 D7 Y7

Procedure:
Wire the circuit as per figure above and verify result first by giving clock signal to One Input
pin at a time of the IC (D0 – D1) and then to all the pins Simultaneously.

TASK 3:
Design the given function (assigned by the instructor) using MUX in your design.

School of Systems and Technology Digital Logic Design Lab 6

Implementation of Latches and Flip-Flops Lab 11

Lab 11 Implementation of Latches and Flip-Flops

OBJECTIVE :
To learn about various types of Latches and Flip-Flops

THEORY:
i) A Flip Flop is a logic circuit that has two stable states Low or High. Enable input signal may
be used to enable or disable a flip flop. Clock signal is used to synchronize operations of flip
flops. Most (if not all) of the system output can change state only when the clock makes a
transition.

ii) Latches are a form of Flip Flop, which do not require clock pulse to latch or hold data
present at its input.

School of Systems and Technology Digital Logic Design Lab 1

Implementation of Latches and Flip-Flops Lab 11

TASK 1 : SR Latch
The SR is the simplest form of Flip Flop or Latch. It could be constructed from NOR gates or
NAND gates. Standard logic symbol of SR flip flop and its truth table is given below:-

NOR Gate SR Latch:

Procedure:
Wire the circuit as per figure above and verify the result.

NOTE: NAND Gate SR Latch has active low input, hence its truth table is different from the
standard i.e a low at the set terminal will set the latch.

TASK 2: GATED FLIP FLOPS

Gated SR Flip Flop: Works only when Enable is High

School of Systems and Technology Digital Logic Design Lab 2

Implementation of Latches and Flip-Flops Lab 11

Procedure:
Wire the circuit as per figure above and verify the result.

Gated D – Flip Flop :

Procedure:
Wire the circuit as per figure above and verify the result.

Gated J-K Flip Flop

Procedure:
Wire the circuit as per figure above and verify the result.

School of Systems and Technology Digital Logic Design Lab 3

 Implementation of Latches and Flip-Flops Lab 11

. TASK 3: D-LATCH AND D-FLIP FLOP OPERATIONS

Procedure:
1. Wire the circuit as per figure 1 & 2 above.
2. Connect +5V to Vcc and Ground to pin GND of the ICs.

VERIFICATION – D LATCH:
1. Verify that the data at the input terminal is reflected at
the output only when Enable (EN) input is high.
2. Verify that for the duration that the Enable input
remains high, all changes in the data input are reflected
at the output.

School of Systems and Technology Digital Logic Design Lab 4

Implementation of Latches and Flip-Flops Lab 11

VERIFICATION – D FLIP FLOP:

1. Verify that the data at the input terminal is reflected at
the output only during Positive going edge of the
Clock pulse.
2. Verify that the duration of the Clock pulse has nothing
to do with data transfer in case of Flip Flop.

School of Systems and Technology Digital Logic Design Lab 5

Implementation of Series and Parallel Registers Lab 12

Lab 12 Implementation Series and Parallel Registers

OBJECTIVE:
To learn about various types of Registers.

THEORY:
A Register is simply a group of flip-flops that can be used to store a binary number. Each flip
flop of a register (called a cell ) stores one bit of word. The bits in a binary number (let’s call it
data) can be moved from one place to another in either of two ways. The first method involves
shifting the data 1 bit at a time, in a serial fashion, beginning with either MSB (most significant
bit) or LSB (least significant bit). This technique is known as serial shifting . The second
method involves shifting all the data bits simultaneously and is referred to as parallel shifting.
There are two ways of shifting data into a register (serial or parallel) and similarly two ways
to shift data out of the register. It is therefore possible to construct four basic types of registers
as shown below:

Serial-in Serial-out Serial-in Parallel-out

Parallel-in Parallel-out Parallel-in Serial-out

School of Systems and Technology Digital Logic Design Lab 1

Implementation of Series and Parallel Registers Lab 12

TASK 1: SERIAL-IN SERIAL-OUT SHIFT REGISTER

The Serial-in Serial-out register accepts data serially that is one bit at a time on a single line. It
produces the stored information on its output in serial form. The figure below shows a 4-bit
Serial-in Serial-out shift register. It is called 4-bit shift register because it has 4-places to store
data A,B,C & D.

Inputs Data Out

Preset Clear Clock D Q Q’
PR CLR CLK
L H X X H

H L X X L

L L X X H
H H ↑ H H
Functional Table of IC 7474
H H ↑ L L
H H L X QO
Pin Configuration IC 7474

School of Systems and Technology Digital Logic Design Lab 2

Implementation of Series and Parallel Registers Lab 12

Procedure:
Wire the circuit as per figure above and complete the table below.

Data In Clock Data Out

Pulse FF
D
0 0
1(LSB) 1
1 2
1 3
1 4
0 5
0 6
1 7
1(MSB) 8
- 9
- 10
- 11
- 12

School of Systems and Technology Digital Logic Design Lab 3

Implementation of Series and Parallel Registers Lab 12

TASK 2: SERIAL-IN PARALLEL-OUT SHIFT REGISTER

The Serial-in Parallel-out register accepts data serially that is one bit at a time on a single line. It
produces the stored information on its output in parallel form. The figure below shows a 4-bit
Serial-in Parallel-out shift register.

Clock Pulse Data In Data

Out
1 1 (LSB)
2 0
3 1
4 1 (MSB)
After 4th pulse, immediately -
disconnect Clock Input to see
desired output displayed (and
latched/held indefinitely) by
the LEDs

School of Systems and Technology Digital Logic Design Lab 4

Implementation of Series and Parallel Registers Lab 12

Procedure:
Wire the circuit as per figure above and write your observation.

TASK 3: PARALLEL-IN PARALLEL-OUT SHIFT REGISTER

The Parallel-in Parallel-out register accepts data in parallel manner, that is all bits at a time on
parallel lines. It also produces the information on its output in parallel form. The figure below
shows a 4-bit Parallel-in Parallel-out shift register.

Data In Clock Data Out

School of Systems and Technology Digital Logic Design Lab 5

Implementation of Series and Parallel Registers Lab 12

Procedure:
Wire the circuit as per figure above and write your observations.

TASK 4: PARALLEL-IN SERIAL-OUT SHIFT REGISTER

The Parallel-in Serial-out register accepts data in parallel manner, that is all bits at a time on
parallel lines. It however produces the information on its output in serial form.
IC 74166 , shown below is shift register. It can shift either Serial or Parallel data entry, and
it outputs Serial data. In this experiment we willuse Parallel input and Serial Ouput
capabilities of the IC
Pin 15 is Shift and Load pin. When :
It is LOW, the register loads data.
It is HIGH, the register outputs data

CONNECTION:
1. Do not connect Pin 1 (it is for serial input)
2. Connect inputs A,B,C,D,E,F,G,H to switches S0 to S7.
3. Connect Clock Inhibit Pin 6 to Ground.
4. Connect Clock Pulse to pin 7 and also to LED L8 (for counting clock pulse)
5. (4) Connect Output QH to LED L0
6. (5) Connect a long wire to the IC pin 15 and keep other terminal of the wire hanging (due to
limited number of switches in the trainer, we will manually connect this end of the wire to ground
for data loading and keep it free (or High) for data shifting)
7. Connect Vcc and GND.

Procedure:
Wire the circuit as per figure above. Select various combination of inputs. Load the input and
then shift it to output. Observe output (the state of the LED when data is loaded shows state of
pin H).

School of Systems and Technology Digital Logic Design Lab 6

Implementation of Asynchronous and Synchronous Counters Lab 13

Lab 13 Implementation of Asynchronous and Synchronous

Counters

OBJECTIVE:
To learn about Asynchronous and Synchronous Counters.

THEORY:
a) A sequential circuit that goes through a prescribed sequence of states upon the application of
input pulses is called a counter. They are used for counting the number of occurrences of an
event and are useful for generating timing sequences to control operations in a digital system.
b) A counter that follows the binary sequence is called binary counter.
c) An N bit binary counter consists of n flip-flopa and can count in binary from 0 to 2N -1.
d) In an asynchronous counter, the output of one FF (Flip-Flop) drives the CLK(Clock) input
of the next FF.
e) In a synchronous counter (or parallel counter) all the FFs are triggered simultaneously by the
clock pulse.

TASK 1 : FOUR BIT (OR MOD 16) COUNTER

The basic asynchronous counter is limited to MOD number that are equal to 2N, where N is the
number of FFs. In case of 4 Bit Counters, we have to use 4 FFs. The counter in this case will
count upto 15.

School of Systems and Technology Digital Logic Design Lab 1

Implementation of Asynchronous and Synchronous Counters Lab 13

Procedure:
Wire the circuit as per figure above and verify the counter is counting a binary sequence, also plot timing
diagram.

Pin Configuration IC 7473

School of Systems and Technology Digital Logic Design Lab 2

Implementation of Asynchronous and Synchronous Counters Lab 13

TASK 2 : MOD 10 COUNTER

The counting sequence of mod-10 counter is from 0000 to 1001 (0 to 9 decimal)

Procedure:
Wire the circuit as per figure above and verify the counter is counting upto 9.

TASK 3: 3-BIT SYNCHRONOUS COUNTER

The counting sequence of 3 bit (mod-8) counter is from 000 to 111 (0 to 7 decimal)

School of Systems and Technology Digital Logic Design Lab 3

Implementation of Asynchronous and Synchronous Counters Lab 13

Procedure:
Wire the circuit as per figure above and verify the counter is counting upto 7.

TASK 4: SYNCHRONOUS DECADE UP/DOWN COUNTER

IC 74192 is a Synchronous Decade up/down counter. Circuit diagram is as shown below.

Procedure:
Wire the circuit as per figure above and verify the counter is counting up or down as desired.

School of Systems and Technology Digital Logic Design Lab 4

Implementation of RAM and ROM Lab 14

Lab 14 Implementation of RAM and ROM

OBJECTIVE:
To learn about various types of Memory.

THEORY:
A semi-conductor memory is an integrated circuit , capable of storing a binary number.
Generally speaking, memory elements can be divided into two categories. One is called Random
Access Memory (RAM) , and the other is called Read Only Memory (ROM). RAM is where we
store Code and Data so that CPU can work on it. It is Volatile memory, that means that when
power is turned off, the contents of the memory is cleared. ROM, on the other hand retains data
stored in it.

RAM circuits on the market have different configuration depending on how the memory cell
array is organized. A memory cell array organized with N by M cells (N x M) can store N words
with each word having M bits. So a 8K x 8 RAM (IC 6116) can store 8K words, each word
having 8 bits in it.

TASK 1 : DESIGN OF A MEMORY CELL

Flip-Flop forms the basic “memory cell” in semiconductor memories. We will verify that a
memory cell made of SR flip flop performs basic functions of Writing data into the cell and
Reading data out of it.

School of Systems and Technology Digital Logic Design Lab 1

Implementation of RAM and ROM Lab 14

Procedure:
1. Connect the circuit as shown above.
2. Input the data to be written (0 or 1) with the help of Input Switch.
3. Write data into the flip-flop by putting Write Enable switch to LOW.
4. Now that data has been written into the flip flop, put the Write Enable switch to High.
5. Put the Out Enable (Read) switch to HIGH to read the data written in the cell. The LED
should be on or off depending on what data has been written in.
6. Verify that the data written once, does not change unless a fresh data is written in the cell.

TASK 2 : WORKING WITH 8K X 8 RAM IC

The 6116 IC is a 16K (actually 16,384) bit high-speed CMOS Static RAM organized as 2K . It
has 11 Address Input pins ( so it can address 211 = 2056 addresses). Similarly it has 8 Data
Input/Output pins (hence each data word can have 8 bits)

School of Systems and Technology Digital Logic Design Lab 2

Implementation of RAM and ROM Lab 14

School of Systems and Technology Digital Logic Design Lab 3