Homework 2

Digital Integrated Circuit Design

Nguyen Tran Son
May 13, 2023

N-channel MOSFET EQUATION:

Cut Off VGS ≤ VT IDS ≈ 0

h 2
i
VDS
Linear VGS > VT , VDS ≤ VGS − VT IDS = µn COX W
L
(VGS − VT )VDS − 2
(1 + λVDS )

Sturation VGS > VT , VDS > VGS − VT IDS = 12 µn COX W

L
(VGS − VT )2 (1 + λVDS )

P-channel MOSFET EQUATION:

Cut Off VSG ≤ |VT | ISD ≈ 0

h 2
i
VSD
Linear VSG > |VT |, VSD ≤ VSG − |VT | ISD = µp COX W
L
(VSG − |VT |)VSD − 2
(1 + λVSD )

Sturation VSG > |VT |, VSD > VSG − |VT | IDS = 12 µp COX W
L
(VSG − |VT |)2 (1 + λVSD )
The simplest model in SPICE (Level 1 or default model) uses the above equations.

Parameter SPICE Parameter Units Typical Values

µn Cox KP A/V 2 200µ

VT 0 VTO V 0.5 -1.0

λ LAMBDA V −1 0.05 - 0.005

Note for Exercise:

1. Tool using: Ngspice

2. Spice Model: CE222.lib
3. Process: TT/FF/SS

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 4. Voltage supply VDD: 0.99/1.1/1.21
5. Temperature: -40C/25C/125C

Ex. 1. MOSFET mode operation: What regions are the following NMOS transis-
tors operating in if VT = 0.5V ?

Ex. 2. Using the provided material in class:(CE222.lib)

1. Study threshold voltage of MNOS, PMOS in the Spice model
2. Plot the id-vds, id-vgs characteristic of NMOS and PMOS
3. Study the leakage current of devices in the Spice model
4. Simulate and measure rise time and fall time of a CMOS inverter drive an
output loading 200fF. (NMOS: w=0.5um, L=60nm; PMOS: w=1um, L=60nm)

Ex. 3. Design, simulate and measure rising/falling delay time of an Inverter Chain
drive a loading 1.5pF. Make sure trise and tfall lesser than 1.3ns for all of variation
of voltage, process and temperature.
Hint: The result will be in table: all of results must less than 1..3ns
P V T Trise (ns) Tf all (ns)
TT 1.1 25 ... ...
FF 1.21 125 ... ...
SS 0.99 -40 ... ...

Ex. 4. Write spice netlist to do transient simulation the below circuit and:

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 1. measure rise time and fall time of output (Y)
2. measure leakage current of this circuit
3. plot waveform of this simulation

Hint:

ˆ Example measure rise time: .meas tran trise trig v(x1) VAL=’0.5*pvdd’ td=500ns
RISE=1 targ v(x2) VAL=’0.5*pvdd’ FALL=1

Ex. 5. Using SPICE and 45nm LP model with 1.1V supply, find the required width
of the PMOS transistor that minimizes the propagation delay (tpHL + tpLH)/2 for
the CMOS inverter. NMOS transistor width is 200nm.
Ex. 6. Optimally size the CMOS NAND2 gate. Find the required width (W)
for the NMOS transistors in the pull-down such that the equivalent resistance of the
pull-down network is the same as the equivalent resistance of the pull down transistor
in an inverter in Exercise 5. Calculate the transistor size. Compare with SPICE and
discuss any discrepancies.
Ex. 7. Repeat Exe. 6 for a NAND3 gate. Compare with SPICE and discuss any
discrepancies.
Ex. 8. Optimally size NOR2 gate by using SPICE to match the inverter form Exe.
5.
Ex. 9. Design and simulate a 4-to-16 decoder using above gates in above exercises.
With output loading 100fF, design for the delay time from input to output less 0.5ns
Ex. 10. Design a Ring Oscillator to generate a CLOCK frequency 100MHz and
25Mhz.