DIGITAL LOGIC DESIGN

Dr. Murad Abusubaih

murads@ppu.edu Lecture 4 Spring 2024
COURSE OUTLINE
1. Introduction
2. Gate-Level Minimization
3. Combinational Logic
4. Synchronous Sequential Logic
5. Registers and Counters
6. Memories and Programmable
Logic

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LECTURE OUTLINE
• C om bi n at i on al Lo g i c C i r cui t s
• Steps of Combinational Logic Design
• The XOR Function
• Half Adder
• Full Adder
• Binary Adder/Subtractor
• Binary Multiplier

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 COMBINATIONAL LOGIC
•Combinational logic
circuits can have any
number of inputs and
outputs.
•The logic states of the
inputs at any given instant
determine the state of the
output.
•Sequential circuits, which we will discuss later in this
course, will feature circuits in which the outputs are not
determined solely by the inputs at the same time

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HOW TO DESIGN A
COMBINATIONAL LOGIC
CIRCUIT?
1. From the specifications of the circuit,
determine the required number of inputs and
outputs and assign a letter (symbol) to each
2. Derive the truth table that defines the
required relationship between the inputs
and outputs
3. Obtain the simplified Boolean functions for
each output as a function of the input variables
(using a K- map)
4. Sketch the logic diagram

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 DESIGN PROBLEM
Design a digital system whose output is defined as
logically low if the 4-bit input binary number is a
multiple of 3; Otherwise, the output will be logically
high. The output is defined if and only if the input
binary number is greater than 2

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 INPUT/OUTPUT RELATIONSHIP
AND TRUTH TABLE

• Design a digital system

whose output is defined as
logically low if the 4-bit
input binary number is a
multiple of 3; otherwise, the
output will be logically high

• The output is defined if and

only if the input binary
number is greater than 2

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BOOLEANFUNCTION
SIMPLIFICATION USINGAK-MAP

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BOOLEAN FUNCTION SIMPLIFICATION
USING A K-MAP

SOP POS
′ ′ ′ ′ ′ ′
𝑆𝑂𝑃

′ ′ ′ ′ ′
𝑃𝑂𝑆

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SKETCHING THE
LOGIC DIAGRAM

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 XOR
THE XOR
FUNCTION
X Y Z
The XOR symbol is denoted as 0 0 0
Its Boolean operation is ′ ′ 0 1 1
1 0 1
The XNOR symbol is denoted as 1 1 0

Its Boolean operation is ′

XNOR
The identities of the XOR operation are
given by:

X Y Z
0 0 1
Commutative and associative: 0 1 0
1 0 0
1 1 1

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 THE XOR
IMPLEMENTATION
• The output analysis for the first
circuit is very easy!

• The output at each of the NAND

gates for the second circuit is as
follows:

• At L1: ′
L2

L1 L4

L3

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 THE XOR
IMPLEMENTATION
• The output analysis for the first
circuit is very easy!

• The output at each of the NAND

gates for the second circuit is as
follows:

• At L1: ′
𝒙 L2
𝒙 ′ + 𝒚′ 𝒙′ + 𝒚
• At L2: L4
′ ′ ′ ′ ′ ′
L1

𝒙 ′ + 𝒚′ 𝒙 + 𝒚′
• At L3: 𝒚 L3
′ ′ ′ ′ ′

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 THE XOR IMPLEMENTATION
• The output analysis for the first
circuit is very easy!

• The output at each of the NAND

gates for the second circuit is as
follows:

• At L1: ′
L2
• At L2: L4
′ ′ ′ ′ ′ ′ L1

• At L3: L3
′ ′ ′ ′ ′

• At L4:
′ ′ ′ ′
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 ARITHMETIC CIRCUITS

• We will continue with the design of digital logic circuits

• One of the famous digital logic circuits is the calculator
• How to design it?

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 ARITHMETIC CIRCUITS

• An arithmetic circuit is a
combinational circuit that outputs one digit
performs arithmetic operations
such as: outputs two digits!
• Addition
• Subtraction carry sum
• Multiplication
• Division

•A combinational circuit that So, we need two binary outputs to

performs the addition of two bits represent the addition block
is called a Half Adder (carry & sum)

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 HALF ADDER
It is required to design a combinational circuit that adds
two binary numbers and produces the output in the form
of two bits, sum and carry
Solution:
1. We need to determine the inputs and output of the
system and give letters for all of them: Our system
has two inputs (x, y) and two outputs (S, C)

x S

y Half Adder C

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 HALF ADDER
2. Derive the truth table Inputs Outputs
according to the given
relation between inputs and x y C S
outputs 0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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 HALF ADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

′ ′

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 HALF ADDER
4. Sketch the logic diagram

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FULL ADDER
It is required to design a combinational circuit that
adds three binary numbers and produces the
output in the form of two bits, sum and carry
Solution:
1. We need to determine the inputs and outputs of
the system and give letters for all of them: Our
system has three inputs (x, y, z) and two outputs
(S, C)

x
S
y Full Adder
C
z

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 FULL ADDER
2. Derive the truth Inputs Outputs Decimal
table according Equivalent
to the given
relation between x y z C S
the inputs and 0 0 0 0 0 0
outputs 0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 1 0 2
1 0 0 0 1 1
1 0 1 1 0 2
1 1 0 1 0 2
1 1 1 1 1 3

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 FULL ADDER
3. Obtain the simplified Boolean functions for each output as
a function of the input variables using a K-map

′ ′ ′ ′ ′ ′

Remember that:
, ′ ′ , ′ ′
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 FULL ADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

′ ′ ′ ′ ′ ′

′ ′ ′ ′ ′

′ ′ ′ ′

Remember that:
, ′ ′ , ′ ′
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 FULL ADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

Remember that:
, ′ ′ , ′ ′
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 FULL ADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

Remember that:
, ′ ′ , ′ ′
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 FULL ADDER
3. Obtain the simplified Boolean functions for each output
as a function of the input variables using a K-map

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FULL ADDER
4. Sketch the logic diagram

′ ′ ′ ′ ′ ′

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FULL ADDER
• The logic circuit for the full adder could also be sketched
using two half adders and a single OR gate
Half adder Half adder

′ ′

Compare the obtained Boolean expression ′ ′

for here and the one obtained in slide 28

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FULL ADDER
• The logic circuit for the full adder could also be sketched
using two half adders and a single OR gate
Half adder Half adder

′ ′

′ ′

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Compare the obtained Boolean expression

for here and the one obtained in slide 28
 FULL ADDER
• The logic circuit for the full adder could also be sketched
using two half adders and a single OR gate
Half adder Half adder

Compare the obtained Boolean expression

for here and the one obtained in slide 28 31
FULL ADDER
• The logic circuit for the full adder could also be sketched
using two half adders and a single OR gate
Half adder Half adder

Compare the obtained Boolean expression

for here and the one obtained in slide 28 32
4-BIT BINARY RIPPLE CARRY
ADDER
• Connecting n full adders in cascade allows us to add n-bit
binary numbers together
• Example: Connecting 4 full adders in cascade allows usto
add 1011 to 0011.

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 4-BIT BINARY RIPPLE CARRY
ADDER
𝟑 𝟑 𝟐 𝟐 𝟏 𝟏 𝟎 𝟎

𝟒 𝟑 𝟐 𝟏 𝟎

This adder is extremely

slow, as each stage must
wait for the previous one to
get the carry from it!
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BINARY SUBTRACTOR
• The subtraction of binary numbers can be easily done using
complements
• The subtraction is done by taking the 2’s complement of
and adding it to

•The 2’s complement can be obtained by taking the 1’s

complement and adding 1 to the least significant bit (LSB)
• The 1’s complement can be implemented easily with an
inverter gate
•We can add 1 to the sum by making the initial input carry of the
parallel adder equal to 1

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SUBTRACTION EXAMPLE

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BINARY MULTIPLIER
2 bits × 2 bits = max 4 bits
2 2 2
10 10 10

2 3 1 0

3 2 1 0

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