AHSANULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

ELECTRICAL AND ELECTRONIC ENGINEERING

PROJECT REPORT

Project Title: Exploring High-Speed and Energy-Efficient Comparators

Course No. : EEE 4134

Course Title : VLSI I Lab

Submitted By:

Section : C1C2
Year : 4th
Semester : 1st
Group Members :

Name ID

Nishat Tabassum 20200105149

Rakibul Bashar Adil 20200105160

Abdullah Al Muhee 20200105162

Salman Abdullah Deep 20200105163

MD. Jubaer Alam 20200105190

 Different Approaches for High-Speed and Energy-
Efficient Comparators
Nishat Tabassum Rakibul Bashar Abdullah Al Muhee
Electrical and Electronic Engineering
Electrical and Electronic Electrical and Electronic
Ahsanullah University of Science and
Engineering Ahsanullah University of Engineering Ahsanullah University of
Technology
Science and Technology Science andTechnology
Tejgaon, Dhaka, Bangladesh
Tejgaon, Dhaka, Bangladesh
Tejgaon, Dhaka, Bangladesh
Salman Deep
Electrical and Electronic Engineering Jubaer Alam
Ahsanullah University of Science and Electrical and Electronic Engineering
Technology Ahsanullah University of Science and
Tejgaon, Dhaka, Bangladesh Technology Tejgaon,
Dhaka, Bangladesh

Abstract--This study presents a comparative analysis of various

methodologies for designing high-speed and energy-efficient
comparators. Schematics representing different approaches were
simulated, and their performance data were scrutinized to
determine the fastest and most energy-efficient method, as well as
the most economically viable. Layout implementations were
conducted without encountering any design rule check errors. The
comparators were simulated using standard 90nm technology.

Keywords— high-speed, energy- efficient, comparator, layout,

CMOS

I. BACKGROUND
In contemporary times, the demand for high-
performance and high-speed devices necessitates
comparators capable of operating at swift speeds while
minimizing power consumption. The design complexity of
such high-speed comparators escalates in scaled CMOS
technology, where scaling doesn't uniformly impact device
supply and threshold voltages. Dynamic comparators
emerge as an appealing solution for high-speed devices
owing to their rapid operation and energy efficiency.
Various dynamic comparator techniques are scrutinized in
this case to address these challenges.
Fig-2: Conventional Dynamic Comparator Design
Circuit-2
The second circuit represents an enhanced iteration of
the conventional double tail comparator. This comparator
consists of preamplifier and latch stages. Its swiftness is
attributed to the direct connection of the comparator output
to the latching nodes. However, it remains unsuitable for
low-power applications.

Fig- 1: Conventional single-stage dynamic comparator.

Fig-3: XNOR-AND Gate Controlled

The initial circuit comprises a Conventional Single-Stage Comparator Design Circuit-3
Dynamic Comparator, which generates rail-to-rail outputs
upon receiving the differential inputs Vin and Vip, all the
while consuming no static power. Illustrated in Figure 1, its
fundamental components include a differential pair (M1, M2),
four pre-charge switches (S1-S4), a tail switch S7, and two
cross-coupled pairs (M3-M4 and M5-M6) forming a back-to-
back latch.
 In Figure 3, the third approach appears more favorable, III. RESULT (DATA REPRESENTATION)
employing an XNOR gate and an AND gate to regulate the
tail transistor of the pre-amplifier, thereby circumventing Truth Table: For Proposed Dynamic (Circuit 4)
static power consumption during the latching phase.
Additionally, clk2 serves as a delayed signal of clk1, aimed Clk1 InP InN O+ O-
at reducing input-referred noise by ensuring that M1 and M2 0 0 0 1 1
remain in a saturated state when clk1 exhibits high voltage 1 0 0 1 0
and clk2 shows low voltage.
0 0 1 1 1
1 0 1 1 0
0 1 0 1 1
1 1 0 1 0
0 1 1 1 1
1 1 1 1 0

Comparison of parameters:

Comparison Table
Approach Single- Conventional XNOR- Proposed
stage Dynamic AND Gate Dynamic
Dynamic Controlled
Propagation 170.1E-9 19.64E-6 5.775E-9
Delay (s) 2.641E-6
Fig-4: Proposed Dynamic Avg Power 423.7E- 2.94E-6 150E-15 40.04E-9
Comparator Design Circuit-4 (W) 12

The fourth circuit leverages clock pulses and their Power 7.20E-17 5.88E-10 3.96E-19 2.31E-16
delayed signals to effectively diminish input-referred noise. Delay
Furthermore, it directly connects pre-amplifier outputs to the Cell Area 74.031 230.44 513.56 250.125
latching nodes, expediting their regeneration. As a result, (um2)
this circuit structure capitalizes on high speed without any No. of 11 14 10+34=44 12
accompanying increase in power consumption. Transistors
No. of DRC 0 0 0 0
Subsequent sections will comprehensively compare Errors
various parameters of these approaches to ascertain the No. of LVS 0 0 0 0
optimal and most cost-effective technique for a high-speed, Mismatches
energy-efficient comparator.
II. FUTURE ASPECTS
IV. RESULT (PICTORIAL REPRESENTATION)
The future outlook for dynamic comparators appears
promising, driven by advancements in semiconductor
technology and design methodologies. Several potential Circuit No. 1:
directions can be envisioned:

1. Advanced Process Technologies: As semiconductor

processes continue to advance, dynamic comparators stand
to benefit from improved transistor characteristics. This
could result in even higher speeds and lower power
consumption. Shrinking feature sizes and enhanced
materials may lead to superior performance and efficiency.

2. Energy Efficiency: In line with the increasing focus on

energy-efficient electronics, dynamic comparators may
undergo further optimization to reduce power consumption.
Research into novel circuit techniques, voltage scaling, and
adaptive biasing could yield comparators that maintain high-
speed operation while consuming minimal energy.

3. Multi-Mode Operation: Future dynamic comparators

could integrate multi-mode functionality, allowing them to
adapt their behavior based on specific application
requirements. This adaptability might involve dynamically Fig-5.1: Conventional single-stage dynamic comparator
adjusting biasing schemes or reconfiguring circuit elements using virtuoso. (Circuit 1)
to achieve optimal performance across a spectrum of
operating conditions.
 Fig-5.2: Waveform of Circuit 1. Fig-6.2: Waveform of Circuit 2.

Fig-5.3: No DRC Error Circuit 1. Fig-6.3: No DRC Error Circuit 2.

Fig-5.4: No LVS Error Circuit 1.

Fig-6.4: No LVS Error Circuit 2.

Circuit No. 2: Conventional Dynamic

Fig-6.1: Circuit 2 using virtuoso.

Circuit No. 3: XNOR-AND Gate Controlled Circuit No.4: Proposed Dynamic

Fig-7.1: Circuit 3 using virtuoso. Fig-8.1: Circuit 4 using virtuoso.

Fig-7.2: Waveform of Circuit 3. Fig-8.2: Waveform of Circuit 4.

Fig-7.3: No DRC Error Circuit 3. Fig-8.3: No DRC Error Circuit 4.

Fig-7.4: No LVS Error Circuit 3.

Fig-8.04: No LVS Error
 V. CONCLUSION
Following the comparison, the fourth circuit emerges as the
optimal choice for a low-power, high-speed dynamic
comparator. Its superiority lies in the direct connection of the
pre-amplifier to the latch, minimizing significant capacitive
load. Static power consumption is effectively circumvented
through controlled switches governed by output logics.
Simulation results demonstrate that this proposed structure
exhibits reduced power consumption, along with viable delay,
low transistor count, and an average area footprint.
REFERENCES
[1] A Rezapour, H. Shamsi, H. Abbasizadeh, K. Lee, “Low Power High
Speed Dynamic Comparator,” in 2018 IEEE International Symposium
on Circuits and Systems (ISCAS), May 2018.
[2] Xiaomeng Zhang , Shuo Li, Ray Siferd, Saiyu Ren, "High-Sensitivity
High-Speed Dynamic Comparator with Parallel Input Clocked
Switches" in 2022 , AEU - International Journal of Electronics and
Communications, July 2020.

ACKNOWLEDGMENT
The completion of this work was made possible with the
invaluable guidance and support of the following faculty
members of the Electrical and Electronic Engineering (EEE)
department at Ahsanullah University of Science and
Technology (AUST):

Mr. Adnan Amin Siddiquee

Lecturer Grade-I
Electrical and Electronic Engineering
Ahsanullah University of Science and Technology
Tejgaon, Dhaka, Bangladesh

Mr. Dewan Monzurul Islam

Lecturer Grade-II
Electrical and Electronic Engineering
Ahsanullah University of Science and Technology
Tejgaon, Dhaka, Bangladesh