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UNIT IV: COMMUNICATION AND NETWORKING

ESP8266 CHARACTERISTICS- SPI Protocol-I2C Protocol-Wi-Fi Communication-Blynk
Protocol-ThingSpeak IoT Platform

ESP8266 CHARACTERISTICS

• ESP8266 (also called ESP8266 Wireless Transceiver) is a cost-effective, easy-to-operate, compact-

sized & low-powered WiFi module, designed by Espressif Systems, that supports both TCP/IP and
Serial Protocol.

• It's normally used in IOT cloud-based embedded projects and is considered the most widely used
WiFi module because of its low cost and small size.

• It runs at an operating voltage of 3V and can handle a maximum voltage of around 3.6 V, so an
external logic level converter is required if you are using 5V supply.

• ESP8266 WiFi module can easily be interfaced with microcontrollers board (i.e. Arduino UNO) via
Serial Port.

• There are numerous breakout boards available based on ESP8266 WiFi Module (i.e. ESP8266
NodeMCU V3).

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• Beause of its compact size, its mostly used in autonomous projects (i.e. Robotics).

• ESP8266 Pinout consists of 8 pins in total, which are given in below table along with their
operation:

ESP8266 Pinout
No. Pin Name Working
1 RX Serial Receiver Pin
2 Vcc Power Pin (+3.3 V; can handle up to 3.6 V)
3 GPIO 0 General-purpose I/O No. 0
4 RST Reset
5 CH_PD Chip power-down
6 GPIO 2 General-purpose I/O No. 2
7 TX Serial Transmitter Pin
8 GND Ground

• Each pin comes with a specific function associated with it where Vcc and GND are voltage source
and ground respectively.

• RX and TX are used for communication where TX is dedicated for data transmission and RX is
used receiving data.

FEATURES OF ESP8266

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• It is also known as a system-on-chip (SoC) and comes with a 32-bit Tensilica

microcontroller, antenna switches, RF balun, power amplifier, standard digital peripheral
interfaces, low noise receive amplifier, power management module and filter capability.

• The processor is based on Tensilica Xtensa Diamond Standard 106Micro and runs at 80
MHz.

• It incorporates 64 KB boot ROM, 80 KB user data RAM and 32 KB instruction RAM.

• It supports Wi-Fi 802.11 b/g/n around 2.4 GHz and other features including 16 GPIO, Inter-
Integrated Circuit (I²C), Serial Peripheral Interface (SPI), 10-bit ADC, and I²S interfaces with
DMA.

• External QSPI flash memory is accessed through SPI and supports up to 16 MB and 512 KB
to 4 MB is initially included in the module.

• It is a major development in terms of wireless communication with little circuitry. and

contains onboard regulator that helps in providing 3.3V consistent power to the boarIt
supports APSD which makes it an ideal choice for VoIP applications and Bluetooth
interfaces.

Serial Communication Protocols

A variety of communication protocols have been developed based on serial communication in the
past few decades. Some of them are:
• SPI – Serial Peripheral Interface: It is a three-wire-based communication system. One wire
each for Master to slave and Vice-versa, and one for clock pulses. There is an additional SS
(Slave Select) line, which is mostly used when we want to send/receive data between multiple
ICs.
• I2C – Inter-Integrated Circuit: Pronounced eye-two-see or eye-square-see, this is an
advanced form of USART. The transmission speeds can be as high as a whopping 400KHz.
The I2C bus has two wires – one for the clock, and the other is the data line, which is bi-
directional – this being the reason it is also sometimes (not always – there are a few
conditions) called Two Wire Interface (TWI). It is a pretty new and revolutionary
technology invented by Philips.
• FireWire – Developed by Apple, they are high-speed buses capable of audio/video
transmission. The bus contains a number of wires depending upon the port, which can be
either a 4-pin one, or a 6-pin one, or an 8-pin one.
• Ethernet: Used mostly in LAN connections, the bus consists of 8 lines, or 4 Tx/Rx pairs.
• Universal serial bus (USB): This is the most popular of all. Is used for virtually all type of
connections. The bus has 4 lines: VCC, Ground, Data+, and Data-.
• RS-232 – Recommended Standard 232: The RS-232 is typically connected using a DB9
connector, which has 9 pins, out of which 5 are input, 3 are output, and one is Ground. You
can still find this so-called “Serial” port in some old PCs. In our upcoming posts, we will
discuss mainly RS232 and USART of AVR microcontrollers.

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What is SPI?
SPI (Serial Peripheral Interface) is an interface bus commonly used for communication with
flash memory, sensors, real-time clocks (RTCs), analog-to-digital converters, and more. The
Serial Peripheral Interface (SPI) bus was developed by Motorola to provide full -duplex
synchronous serial communication between master and slave devices.

SPI Interface
As shown in Figure 1, a standard SPI connection involves a master connected to slaves using the
serial clock (SCK), Master Out Slave In (MOSI), Master In Slave Out (MISO), and Slave Select
(SS) lines. The SCK, MOSI, and MISO signals can be shared by slaves while each slave has a
unique SS line.

Figure 1. 4-wire SPI bus configuration with multiple slaves

SPI Mode: Polarity and Clock Phase

The SPI interface defines no protocol for data exchange, limiting overhead and allowing for high
speed data streaming. Clock polarity (CPOL) and clock phase (CPHA) can be specified as ‘0’ or
‘1’ to form four unique modes to provide flexibility in communication between master and slave
as shown in Figure 2.

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Figure 2. SPI bus timing

If CPOL and CPHA are both ‘0’ (defined as Mode 0) data is sampled at the leading rising edge of
the clock. Mode 0 is by far the most common mode for SPI bus slave communication. If CPOL is
‘1’ and CPHA is ‘0’ (Mode 2), data is sampled at the leading falling edge of the clock. Likewise,
CPOL = ‘0’ and CPHA = ‘1’ (Mode 1) results in data sampled at on the trailing falling edge and
CPOL = ‘1’ with CPHA = ‘1’ (Mode 3) results in data sampled on the trailing rising edge. Table
1 below summarizes the available modes.

Table 1. SPI mode definitions

Mode CPOL CPHA

0 0 0

1 0 1

2 1 0

3 1 1

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SPI Bus 3-Wire and Multi-IO Configurations

In addition to the standard 4-wire configuration, the SPI interface has been extended to include a
variety of IO standards including 3-wire for reduced pin count and dual or quad I/O for higher
throughput.

In 3-wire mode, MOSI and MISO lines are combined to a single bidirectional data line as shown
in Figure 3. Transactions are half-duplex to allow for bidirectional communication. Reducing the
number of data lines and operating in half-duplex mode also decreases maximum possible
throughput; many 3-wire devices have low performance requirements and are instead designed
with low pin count in mind.

Figure 3. 3-wire SPI configuration with one slave

Multi I/O variants such as dual I/O and quad I/O add additional data lines to the standard for
increased throughput. Components that utilize multi I/O modes can rival the read speed of parallel
devices while still offering reduced pin counts. This performance increase enables random access
and direct program execution from flash memory (execute-in-place).

Quad I/O devices can, for example, offer up to 4 times the performance of a standard 4 -wire SPI
interface when communicating with a high speed device. Figure 4 shows an example of a single
quad IO slave configuration.

Figure 4. Quad IO SPI configuration with one slave

SPI Bus Transactions

The SPI protocol does not define the structure of the data stream; the composition of data is
completely up to the component designer. However, many devices follow the same basic format
for sending and receiving data, allowing interoperability between parts from different vendors.

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Simple SPI Write Transaction

Most SPI flash memories have a write status register command that writes one or two bytes of
data, as shown in Figure 6. To write to the status register, the SPI host first enables the slave select
line for the current device. The master then outputs the appropriate instruction followed by two
data bytes that define the intended status register contents. Since the transaction does not need to
return any data, the slave device keeps the MISO line in a high impedance state and the master
masks any incoming data. Finally, slave select is de-asserted to complete the transaction.

Figure 5. Write command using a single-byte instruction and two-byte data word

Using the Corelis SPI Exerciser command language, this transaction can be accomplished with the
following code, where Data Byte 2 is “55” and Data Byte 1 is “AA”. For brevity we are using the
short version of commands; the command script language supports both full commands such as
“write, read” as well as abbreviated versions “wt, rd”. For example, the code for a write
transaction below activates slave select, performs a write operation, then deactivates slave select:

sson // Activate slave select wt 01 55 AA // Write instruction 01h and data bytes 55h, AAh ssoff //
Deactivate slave select

Simple SPI Read Transaction

A status register read transaction would be similar to the write transaction, but now takes
advantage of data returned from the slave as shown in Figure 7. After sending the read status
register instruction, the slave begins transmitting data on the MISO line at a rate of one byte per
eight clock cycles. The host receives the bitstream and completes the transaction by de -asserting
SS#.

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Figure 6. Read command using a single-byte instruction and two-byte data word

This sequence is really a single-byte write followed by a two byte read; it can be considered a
three-byte combined write/read command or a single byte write and two-byte read. We can create
this transaction with the Corelis SPI Exerciser debugger command sequence:

Quad IO SPI Transaction

Quad IO is gaining popularity with flash memories for its increased performance. Instead of using
a single output and single input interface, Quad IO utilizes 4 separate half-duplex data lines for
both transmitting and receiving data for up to four times the performance of standard 4 -wire SPI.

Figure 7 shows an example read command for a Spansion S25FL016K serial NOR flash device.
To read from the device, a fast read command (EBh) is first sent by the master on the first IO line
while all others are tristated. Next, the host sends the address; since the interface now has 4
bidirectional data lines, it can utilize these to send a complete 24-bit address along with 8 mode
bits in just 8 clock cycles. The address is then followed with 2 dummy bytes (4 clock cycles) to
allow the device additional time to set up the initial address.

Figure 7. Quad mode fast read sequence for Spansion S25FL016K or equivalent

After the address cycle and dummy bytes have been sent by the host, the component begins
sending data bytes; each clock cycle consists of a data nibble spread across the 4 IO lines, for a

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total of two clock cycles per byte of data. Compare this to the 16 clock cycles required for our
simple read transaction and it’s easy to see why quad mode is gaining popularity for high speed
flash memory applications! To create this sequence in the SPI Exerciser command language, we
would use the example code:

4m // Start in 4-wire mode sson // Activate slave select wt EB // Write instruction EBh qm //
Switch to quad mode wt AA AA AA 00 // Write 3-byte address and 8 read mode bits wt 55 55 //
Write 2 dummy bytes rd 2 // Read two data bytes ssoff // Deactivate slave select

Note that we’re changing from 4-wire mode to quad mode in the middle of the transaction. In quad
mode, the software automatically distributes the data bytes among the IO lines using the same bit
pattern

Advantages of SPI

• It’s way faster than asynchronous serial communication and I2C (almost twice as fast).
• No start and stop bits, so the data can be streamed continuously without interruption.
• No slave addressing mechanism like I2C.
• It has separate MISO and MOSI lines, so data can be sent and received at the same time
(Full duplex).
• Not Limited to 8-bit data.
• The received hardware (slave) can be a simple shift register.
• It supports multiple slave devices.

Disadvantages of SPI

• It requires more lines (wires) than other communication methods. (UART and I2C only
require 2 lines).
• There is no acknowledgment to inform that data has been successfully transferred like I2C
and No error detection protocol is defined.
• The communications must be well-defined in advance (you can’t send random amounts of
data whenever you want).
• The master must control all communications (slaves can’t talk directly to each other).
• It usually requires separate CS lines to each peripheral, which can be problematic if
numerous slaves are needed.
• SPI only supports a single master.
• Can be used only from short distances.

Applications

• SPI is used to talk to a variety of peripherals, such as,

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• Sensors: temperature, pressure, ADC, touchscreens, video game controllers

• Control devices: audio codecs, digital potentiometers, DAC
• Camera lenses: Canon EF lens mount
• Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11, handheld
video games
• Memory: flash and EEPROM
• Real-time clocks
• LCD
• Any MMC or SD card

I2C Protocol

I2C is a serial protocol for a two-wire interface to connect low-speed devices like
microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces, and other similar
peripherals in embedded systems. It was invented by Philips and now it is used by almost all major
IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP
(formerly Philips semiconductors).

The I2C bus is popular because it is simple to use, there can be more than one master, only upper
bus speed is defined and only two wires with pull-up resistors are needed to connect an almost
unlimited number of I2C devices. I2C can use even slower microcontrollers with general -purpose
I/O pins since they only need to generate correct Start and Stop conditions in addition to functions
for reading and writing a byte.

Each slave device has a unique address. Transfer from and to the master device is serial and it is
split into 8-bit packets. All these simple requirements make it very simple to implement the I2C

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interface even with cheap microcontrollers that have no special I2C hardware controller. You only
need 2 free I/O pins and few simple i2C routines to send and receive commands.

I2C bus specification describes four operating speed categories for bidirectional data transfer:

Standard-mode (Sm) a bit rate up to 100 kbit/s

Fast-mode (Fm) a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+) a bit rate up to 1 Mbit/s

High-speed mode (Hs-mode) a bit rate up to 3.4 Mbit/s

Ultra-fast mode (UFm) a bit rate up to 5 Mbit/s

I²C Interface

I2C uses only two wires:

• SCL (serial clock)

• SDA (serial data)

Both need to be pulled up with a resistor to +Vdd. There are also I2C level shifters that can be
used to connect to two I2C buses with different voltages.

I²C Address

Basic I2C communication is using transfers of 8 bits or bytes. Each I2C slave device has a 7 -bit
address that needs to be unique on the bus. Some devices have fixed I2C addresses while others
have few address lines which determine lower bits of the I2C address. This makes it very easy to
have all I2C devices on the bus with a unique I2C address. There are also devices that have a 10 -
bit address as allowed by the specification.

The 7-bit address represents bits 7 to 1 while bit 0 is used to signal reading from or writing to the
device. If bit 0 (in the address byte) is set to 1 then the master device will read from the slave I2C
device.

The master device needs no address since it generates the clock (via SCL) and addresses
individual I2C slave devices.

I²C Protocol

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In a normal state, both lines (SCL and SDA) are high. The communication is initiated by the
master device. It generates the Start condition (S) followed by the address of the slave device (B1).
If bit 0 of the address byte was set to 0 the master device will write to the slave device (B2).
Otherwise, the next byte will be read from the slave device. Once all bytes are read or written (Bn)
the master device generates Stop condition (P). This signals to other devices on the bus that the
communication has ended and another device may use the bus.

Most I2C devices support repeated start conditions. This means that before the communication
ends with a stop condition, the master device can repeat the start condition with the address byte
and change the mode from writing to reading.

Wi-fi Communication

Wi-Fi stands for Wireless Fidelity, and it is developed by an organization called IEEE (Institute of
Electrical and Electronics Engineers) they set standards for the Wi-Fi system.
Each Wi-Fi network standard has two parameters :
1. Speed –
This is the data transfer rate of the network measured in Mbps (1 megabit per second).
2. Frequency –
On what radio frequency, the network is carried on. Two bands of frequency for the Wi-Fi are
2.4 GHz and 5 GHz. In short, it is the frequency of radio wave that carries data.

Two Frequencies of Wi-Fi signal :

Wi-Fi routers that come with 2.4 GHz or5 GHz are called the single-band routers but a lot of new
routers support both 2.4 GHz and 5 GHz frequency they are called dual-band routers.
The 2.4 GHz is a common Wi-Fi band, but it is also used by other appliances like Bluetooth
devices, wireless phones, cameras, etc. Because of the signal used by so many devices, the signal
becomes overcrowded and speed becomes slow. So 5 GHz comes into the picture, It is new, and
not commonly used, and because it is used by fewer devices there is no signal crowding and
interference.
The 2.4 GHz transmits data at a slower speed than 5 GHz but does have a longer range than 5
GHz. The 5 GHz transmits data at a faster rate, but it has a shorter range because it has a higher
frequency.

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Parameter 2.4 GHz 5 GHz

Speed Comparatively Low High

Range High Comparatively low

Different standards of Wi-Fi :

These are the Wi-Fi standards that evolved from 1997 to 2021. In 1997 IEEE created one standard
and gave the name 802.11.

IEEE 802.11 –
1. It was developed in 1997.
2. Speed is about 2 Mbps (2 megabits per second).

IEEE 802.11a –
This standard is developed in 1999.
1. 802.11a is useful for commercial and industrial purposes.
2. It works on a 5 GHz frequency.
3. The maximum speed of 802.11a is 54 Mbps.
4. This standard was made to avoid interference with other devices which use the 2.4 GHz band.

IEEE 802.11b –
1. This standard also created with 802.11a in 1999.
2. The difference is that it uses a 2.4 GHz frequency band.
3. The speed of 802.11b is 11 Mbps.
4. This standard is useful for home and domestic use.

IEEE 802.11g –
1. This standard is designed in 2003.
2. Basically, it has combined the properties of both 802.11a and 802.11b.
3. The frequency band used in this is 2.4 GHz for better coverage.
4. And the maximum speed is also up to 54 Mbps.

IEEE 802.11n –
1. This was introduced in 2009.
2. 802.11n operates on both 2.4 GHz and 5 GHz frequency bands, they are operated individually.
3. The data transfer rate is around 600 Mbps.

IEEE 802.11ac –
1. This standard is developed in 2013 named 802.11ac.

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2. Wi-Fi 802.11ac works on the 5 GHz band.

3. The maximum speed of this standard is 1.3 Gbps.
4. It gives less range because of the 5 GHz band, but nowadays most of the devices are working on
802.11n and 802.11ac standards.

IEEE 802.11ax –
1. It is the newest and advanced version of Wi-Fi.
2. This is released in 2019.
3. Operates on both 2.4 GHz and 5 GHz for better coverage as well as better speed.
4. User will get 10 Gbps of maximum speed around 30-40 % improvement over 802.11ac

Tabular Representation:

Version Introduced in Frequency band used Maximum speed provided

IEEE 802.11a 1999 5 GHz 54 Mbps

IEEE 802.11b 1999 2.4 GHz 11 Mbps

IEEE 802.11g 2003 2.4 GHz 54 Mbps

IEEE 802.11n 2009 Both 2.4 GHz and 5 GHz 600 Mbps

IEEE 802.11ac 2013 5 GHz 1.3 Gbps

IEEE 802.11ax 2019 Both 2.4 GHz and 5 GHz Up to 10 Gbps

Now recently Wi-Fi alliance announced the new naming scheme for Wi-Fi standards. Rather than
the complex names like “802.11b” name now we can call as “Wi-Fi 1“, and similar for others. This
will help consumers for easy to understand as 802.11 is difficult to understand.

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New Naming Standards :

Network Wi-Fi Standard

IEEE 802.11b Wi-Fi 1

IEEE 802.11a Wi-Fi 2

IEEE 802.11g Wi-Fi 3

IEEE 802.11n Wi-Fi 4

IEEE 802.11ac Wi-Fi 5

IEEE 802.11ax Wi-Fi 6

Wi-fi Collision handling mechanism :

IEEE 802.11 wireless LANs use a media access control protocol called Carrier Sense Multiple
Access with Collision Avoidance (CSMA/CA). While the name is similar to Ethernet's Carrier
Sense Multiple Access with Collision Detection (CSMA/CD), the operating concept is totally
different.

WiFi systems are the half duplex shared media configurations, where all stations transmit and
receive on the same radio channel. The fundamental problem of a radio system is that a station
cannot hear while it is sending, and hence it is impossible to detect a collision. Because of this, the
developers of the 802.11 specifications came up with a collision avoidance mechanism called
the Distributed Control Function (DCF).

According to DCF, a WiFi station will transmit only when the channel is clear. All transmissions
are acknowledged, so if a station does not receive an acknowledgement, it assumes a collision
occurred and retries after a random waiting interval.

The incidence of collisions will increase as the traffic increases or in situations where mobile
stations cannot hear each other.

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Communication in Wi-Fi

Data exchange in Wi-Fi can be summarized into three phases:

Phase I: Where data is prepared for transmission; it is encoded; changed into frames (digital
signals are sent in frames for better QoS). The frequency for data transmission is also chosen
depending upon the technique used to send the signals wirelessly.

Phase II: Where data is transmitted with air as the medium of wave transmission

Phase III: Where data is received, decoded, acknowledged and then used.

All of these phases apply some of the popular digital communications spread spectrum techniques
for signal multiplexing (FHSS, Infrared, OFDM etc.), make use of security methods (WEP, WPA).
Let’s find out the technical insides of the Wi-Fi legacy.

[header= OSI Model for Wi-Fi]

Technical Intricacies

For a user, Wi-Fi appears to be a wireless form of Ethernet, but it is a fairly different technology.
Deriving its working strategy from the OSI model, Wi-Fi uses various data exchange techniques,
security measures, network topologies that make it a well strategized wireless network. Since its

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inception, there have been numerous changes in the 802.11 standard. Let’s start with the features
that were there when the legacy had just begun. OSI Model and WLAN

Wireless LAN uses physical layer and MAC sub-layer (of data link layer) of the OSI model. The
physical layer takes care of the wireless data exchange and the MAC layer synchronizes the
transmission of data.

PHYSICAL Layer in 802.11

Defined in the 2.4 and 5GHz spectrum, Wi-Fi standard has been designed to be enough robust
against the interfering frequencies by other electronic gadgets such as microwave ovens, cordless
telephones etc. Also, the data transmission speeds were to be maintained high along with
maintaining the data safety features. Fulfilling these conditions were three wireless data exchange
schemes adopted by physical layer in 802.11: Infrared, Frequency Hopping Spread Spectrum
Technique and Direct Sequence Spread Spectrum Technique. Out of these techniques, infrared
was soon eliminated due to range limitations. Information about how other techniques work can be
fetched here. DSSS technique works well in low to high interferences while FHSS can take care of

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high interference signals. DSSS technique uses a Barker code (pre-determined sequence made by
+1 and -1 only) sequence in order to encode the data to be transmitted. The new code generated is
decoded using the same barker sequence.

In 802.11, Physical Layer can be divided into two sub-layers: Physical Layer Convergence
Procedure (PLCP) and Physical Medium Dependent (PMD) Protocol. PLCP layer either analyzes
the data packets received or prepares them to be sent across the radio channel. PMD layer’s task is
to demodulate the packets received or modulate the data packets before they are sent over the
channel.

Additions to the Physical Layer

Initial spread spectrum techniques of FHSS and DSSS sufficed for transmission speeds up -to 1-
2mbps but were incapable at higher ones. IEEE then further provided more modulation techniques
that were able to provide higher data rates. Complementary Code Keying (CCK) data modulation
technique is been included in the IEEE standard update for a, b and above versions. CCK
technique uses 64 code words of 8bit which are mathematically unique and are easily
distinguishable at receiver end. Using CCK technique increased the data transmission rates to 5.5
and 11mbps, respectively. Further, inclusions of techniques such as OFDM and MIMO-
OFDM have increased the speed to 54mbps and more.

It has been the modifications in the physical layers that have been responsible for various versions
of Wi-Fi as shown in the graphic below:

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MAC Layer

Medium Access Layer’s task is to ensure reliability in data transmission which it can manage
using two utilities: Distributed Coordinated Function and Point Coordinated Function.

Distributed Coordinated Function

This is a mandatory method used in 802.11standard and utilizes Carrier Sense Multiple Sense with
Collision Avoidance (CSMA-CA) technique. CSMA technique is deployed to make the source
confirm first that whether channel is free to transmit data or not. It is a contingent (subject to
chance) technique which ideally lets only one source transmit over a channel at a particular period
of time, thus avoiding signal collision and its consequent re-transmission. After a frame is sent,
the transmission in channel ceases for certain time called inter-frame space (IFS). During this
period, sources can whether channel is occupied or not. In case, multiple channels are to transmit
at the same time, a priority algorithm is applied so that transmission conflict gets avoided. To aid
the stations in determining the time for which channel would be occupied, a network allocation

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vector (NAV) is used. This vector suggests the time for which current data transmission is taking
place and when a source can check the channel again to send data.

Handshaking Process: Whenever a source has to transmit data, it sends a Request-to –send (RTS)
frame to the receiver which is followed by a clear-to-send (CTS) frame by receiver. The CTS
frame is broadcasted and other sources ready to transmit data start running a back off algorithm so
as to suspend their signal transmission on the channel for random amount of time. The receiver
sends an ACK (acknowledge) frame to the transmitter after the whole signal is received.

Carrier Sensing: When 802.11 standard applies the CSMA-CA technique, it senses the carrier at
two levels: the MAC sublayer and the air interface. Carrier sensing at latter is termed as physical
carrier sensing while for the former, it is known as virtual carrier sensing. Physical carrier sensing
analyzes the total number of 802.11 based stations present while virtual carrier sensing is applied
by source to convey how long it would be utilized the channel when it has to transmit.

Point Coordination Function (PCF)

It is a contingent-free optional technique that uses a polling method through round robin or
priority based algorithms. This function requires a point coordinator, whose function is to divide
time in such a manner that all the information sources are able to transmit information at different
time intervals. Working in a synchronous manner, PCF divides time into super frame, using which
the sources can transmit. PCF mandatorily requires presence of a point coordinator unit along with
providing a time-bound distributed data service.

On the other hand, DCF doesn’t require a point coordinator, thus sources can connect to each other
without needing a mediator.

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Wi-Fi Framing
In Wi-Fi technology, three types of frame have been protocoled: management frames, control
frames and data frames.

Type of Frame Prime Responsibility Sub-frames

Management Frame (MAC

1. Connection and Assosiation Request
protocol Data Unit) disconnection of STA with AP, Assosiation Response
Reassosiation Request
Reassosiation Response
Probe request
Probe Response
Beacon
Announcement Traffic
Indication Message(ATIM)
Disassosiation
Authentication
Deauthenication

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Action
Power Save(PS) Poll
Control Frame 1. Assist with delivery of data
Request to Send (RTS)
frame. Clear to send (CTS)
Acknowledgement(ACK)
2. Provide unicast frame
Contention-Free(CF)-End
acknowledgements. (PCF only)
CF-End+CF-ACK (PCF
only)
Black-ACK(HCF)
Black Ack Request(HCF)

Data
Data Frame Carry actual data that is
Data+CF-Ack (PCF only)
passed from higher layer Data+CF-Poll (PCF only)
Data+CF-Ack+CF-Poll (PCF
protocols.
only)
Null data (no data transmitted)
CF-Ack (no data transmitted)
(PCF only)
CF-Poll (no data transmitted)
(PCF only)
Data+CF-Ack+CF-Poll (PCF
only)
Qos Data (HCF)
Qos Null (No Data) (HCF)
QosData+CF-Ack (HCF)
QosData+CF-Poll (HCF)
QosData+CF-Ack+CF-Poll
(HCF)
QosCf-Poll(HCF)
Qos CF-ACK+CF-Poll (HCF)

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Frame format in MAC:

Preamble: It is first part of the PLCP(Physical layer convergence protocol) header and It indicates
to the receiver that it is about to receive data. This aids in receiver identifying beginning of signal
reception and synchronize frame transmission. A preamble is of two types:
Long Preamble: Compatible with the 802.11 legacy, long preamble takes 192micro seconds for
transmission. Hence, majority of the Wi-Fi routers and adapters are pre-configured for long
preamble reception.
Short Preamble: Not compatible with the 802.11 legacy yet, short preamble takes 96 micro
seconds for transmission. It is incorporated in the new standards which are at developmental
stages.
Preamble is dependent on the physical layer and consists of two parts:
Synch: this is 80 bit long sequence implemented by physical layer to choose the destination and
synchronize data transmission and reception frequency.
Start Frame Delimiter: It is 16 bit digital code which aids the receiver in deciding frame timing.
PLCP Header: Aforementioned, PLCP layer consists of functions to code or decode the logical
information (data packets) transmitted or received. The PLCP header consists of three parts:

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PLCP_PDU Length Word: Contains information about totally bytes contained in data packet,
hence helping the receiver to determine end of the frame.
PLCP Signaling Field: Details with the data rate i.e. rate at which message is transmitted.
Header Error Check: This is a 16bit field which applies CRC check as an error detection
technique.
MAC Header: MAC header details about frame control, duration, addressing, sequence control
etc. Let’s understand all the fields in a standard MAC header.
1. Frame Control: It is 16 bit field under which following are specified:
• ·The version of the protocol (a, b, g, n etc.)
• Type of frame: management (00), data(10) or control(01).
• Sub-type of the frame sent.
• To DS and From DS indicate signal transmission from BSS to DS and DS to
BSS, respectively.
• More Frag: In cases of large message transmission, packet fragmentation takes
place. This fragmentation is indicated by more frag field.
• Retry: Some frames might require re-transmission from time to time and
through retry field, the receiver is able to filter off duplicate frames from those
which are sent on purpose.
• Power Management: This field indicates whether the transmitter would be in
active state or power saving state after transmission of message.
• More Data: When a station is in power save mode, a high bit on this field
indicates it that more frames are ready to be transmitted to it from AP.
• WEP Field: This field indicates the security measures on the frame, and goes
high when data is encrypted or encoded.

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2. Frame Duration: A 16 bit long field, field duration is used in multiple ways: (a) to indicate
the duration of the frame sent using network allocation vector; (b)carrying the ID of the
station that has transmitted the data (used when control frames are transmitted)
3. Address fields: The quadruple of address fields along with To DS and From DS field of
frame control, form the following combination of data transmission:

Blynk Protocol:

Blynk is a comprehensive software suite that enables the prototyping, deployment, and remote
management of connected electronic devices at any scale.

Whether it's personal IoT projects or commercial connected products in the millions, Blynk
empowers users to connect their hardware to the cloud and create iOS, Android, and web
applications, analyze real-time and historical data from devices, remotely control them from
anywhere, receive important notifications, and much more.

Blynk Library uses proprietary binary protocol.

Every message consists of 2 parts.

1. Header :

Protocol command (1 byte);

MessageId (2 bytes);

Body message length (2 bytes);

2. Body : string (could be up to 2^15 bytes).

Blynk transfers binary messages with the following structure:

Command Message Id Length/Status Body

1 byte 2 bytes 2 bytes Variable

Hardware side protocol

Blynk data packets travel server-hardware and vice versa using this structure:

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Command Message ID Length/Status Body

1 byte 2 bytes 2 bytes Variable

Mobile app side protocol

Server-mobile app communication uses the same structure.

Command Message ID Length/Status Body

1 byte 2 bytes 4 bytes Variable

Websockets web side protocol

Web sockets require a header in their structure.

Websocket header Command Message ID Body

1 byte 2 bytes Variable

When command code == 0, than message structure is next:

Websocket header Command Message ID Response code

1 byte 2 bytes 4 bytes

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