SRM Institute of Science and Technology

Faculty of Engineering and Technology

Department of Electronics and Communication Engineering
(21ECC101J/ELECTRONIC SYSTEM AND PCB DESIGN– Semester: II)

Classification of Solids: Conductors

Classification of Solids: Insulators

Classification of Solids: Semiconductors

Classifications of Semiconductor:

Intrinsic Semiconductors:
Extrinsic Semiconductors:

Extrinsic Semiconductors (n-type):

Extrinsic Semiconductors (p-type):

Conductivity of Semiconductors:
Energy Distribution and Fermi Level:
The maximum energy of a free electron can have in a material at absolute temperature i.e. at 0k is known
as Fermi energy level. Fermi level is the energy state which has probability ½ of being occupied by an
electron. In simple terms, it is the maximum energy level that an electron can have at 0k and the probability
of finding the electron above this level at absolute temperature is 0. At absolute zero temperature, half of
the Fermi level will be filled with electrons. In energy band diagram of semiconductor, Fermi level lies in
the middle of conduction and valence band for an intrinsic semiconductor. For extrinsic semiconductor,

Fermi level lies near valency band in P-type semiconductor and for N-type semiconductor, it lies near to
the conduction band. Fermi energy level is denoted by EF, the conduction band is denoted as EC and valence
band is denoted as EV.
Fermi Dirac Distribution Function

The probability that the available energy state ‘E’ will be occupied by an electron at absolute temperature
T under conditions of thermal equilibrium is given by the Fermi-Dirac function. From quantum physics,
the Fermi-Dirac Distribution Expression is:

The Fermi level represents the energy state with a 50% probability of being filled if no forbidden band
exists, i.e., if E = EF then f(E)=1/2 for any value of temperature.

Fermi-Dirac distribution only gives the probability of occupancy of the state at a given energy level but
doesn’t provide any information about the number of states available at that energy level.
Intrinsic Concentration and Mass Action Law:
Charge Distribution in an Open Circuited Semiconductor:
Problems:
1.

2.
3.
Drift Current and Diffusion Current

There are two types of current through a semiconducting material – one is drift current and the other is
diffusion current. The mechanism of drift current is similar to the flow of charge in a conductor. In case of
conductor when a voltage is applied across the material, the electrons are drawn to the positive end. Similar
is the case in semiconductor. However, the movement of the charge carriers may be erratic path due to
collisions with other atoms, ions and carriers. So, the net result is a drift of carriers to the positive end. In
semiconducting material, when a heavy concentration of carrier is introduced to some region, the heavy
concentrations of carriers distribute themselves evenly through the material by the process of diffusion. It
should be remembered that there is no source of energy as required for drift current. When an electric field
is applied across the crystal, every charge carrier experiences a force due to the electric field and hence it
will be accelerated in the direction of force. This results in drifting of the charge carriers in the direction of
force will cause a net flow of electric current through the crystal.

Drift current

The flow of charge carriers, which is due to the applied voltage or electric field is called drift
current. In a semiconductor, there are two types of charge carriers, they are electrons and holes.
When the voltage is applied to a semiconductor, the free electrons move towards the positive
terminal of a battery and holes move towards the negative terminal of a battery.

Electrons are the negatively charged particles and holes are the positively charged particles. As we already
discussed that like charges repel each other and unlike charges attract each other. Hence, the electrons
(negatively charged particle) are attracted towards the positive terminal of a battery and holes (positively
charged particle) are attracted towards the negative terminal.
 Figure: Drift current

In a semiconductor, the electrons always try to move in a straight line towards the positive terminal of the
battery. But, due to continuous collision with the atoms they change the direction of flow. Each time the
electron strikes an atom it bounces back in a random direction. The applied voltage does not stop the
collision and random motion of electrons, but it causes the electrons to drift towards the positive terminal.
The average velocity that an electron or hole achieved due to the applied voltage or electric field
is called drift velocity.

The drift velocity of electrons is given by

Vn = µnE

The drift velocity of holes is given by

Vp = µpE

Where vn = drift velocity of electrons vp = drift

velocity of holes

µn = mobility of electrons
µp = mobility of holes
E = applied electric field

The drift current density due to free electrons is given by

Jn = enµn E
and the drift current density due to holes is given by

Jp = epµp E

Where Jn = drift current density due to electrons

Jp = drift current density due to holes
e = charge of an electron =1.602 × 10-19 Coulombs (C).
n = number of electrons
p = number of holes

Then the total drift current density is

J = Jn + Jp

= enµn E + epµp E J = e
(nµn + pµp ) E

Diffusion Current

Diffusion current is mainly generated in semiconductors. The doping done in the semiconductors is non-
uniform. In order to achieve uniformity, the flow of charge carriers takes place from higher concentration
area to lower concentration area. It is referred to as diffusion. This process generally doesn’t occur in
conductors. Fick’s law well describes the diffusion of flux from that the thesis is derived for the diffusion
of electrons as well as for holes.

The necessity of the diffusion current in the semiconductor is because of the reason behind the dominating
current at the junction. At the equilibrium condition, the net currents are zero because the forward current
is balanced by the reverse drift current but inside the depletion region, both drift and diffusion currents are
present.

What do you mean by Diffusion Current?

Generally in semiconductors, one can find the movement of charge carriers. This movement of the
carriers is termed as Diffusion. The movement of carriers is observed from the higher concentration
area to the lower concentration area.
In this process of movement, there is some generation of the current. This type of current is referred to
as Diffusion Current for the semiconductors.

Diagram

Diffusion current can occur in the semiconductors that are non-uniformly doped because in non- uniformity
only one can find the majority and the minority concentration so that movement can be observed for the
carriers from higher concentration to the lower concentration. Consider an n-type semiconductor that is
non-uniformly doped as shown in below figure. Due to the non-uniform doping, more number of electrons
is present at left side whereas lesser number of electrons is present at right side of the semiconductor
material. The number of electrons present at left side of semiconductor material is more. So, these electrons
will experience a repulsive force from each other. The electrons present at left side of the semiconductor
material will moves to right side, to reach the uniform concentration of electrons. Thus, the semiconductor
material achieves equal concentration of electrons. Electrons that moves from left side to right side will
constitute current. This current is called diffusion current.

Figure: Diffusion Current

In p-type semiconductor, the diffusion process occurs in the similar manner.

Both drift and diffusion current occurs in semiconductor devices. Diffusion current occurs without an
external voltage or electric field applied. Diffusion current does not occur in a conductor. The direction
of diffusion current is same or opposite to that of the drift current.

Concentration gradient

The diffusion current density is directly proportional to the concentration gradient. Concentration gradient
is the difference in concentration of electrons or holes in a given area. If the concentration gradient is high,
then the diffusion current density is also high. Similarly, if the concentration gradient is low, then the
diffusion current density is also low.

The concentration gradient for n-type semiconductor is given by

The concentration gradient for p-type semiconductor is given by

Where Jn = diffusion current density due to electrons Jp = diffusion current

density due to holes

The constants it does depend on are Dp and Dn, and +q and -q, for holes and electrons respectively. The
first constants are called the diffusion coefficients, a proportionality factor

Diffusion current density

The diffusion current density due to electrons is given by

Where Dn is the diffusion coefficent of electrons

The diffusion current density due to holes is given by

Where Dp is the diffusion coefficent of holes

The above equation is for the densities of diffusion densities with respect to electrons and holes but the
overall density of the current of respective holes or electrons can be given by the sum of the diffusion
current and the drift current.
The overall diffusion density with respect to electrons can be given as

The overall diffusion density with respect to holes can be given by the equations for the individual
densities of electrons as well as holes. Therefore the overall current density can be given by
In this way, the equations for the diffusion current densities are described for holes as well as electrons.
The diffusion current in the semiconductor has occurred before the application of external supply. It is
also termed as the process of recombination in order to achieve uniformity. But have you ever thought
why the diffusion doesn’t take place in conductors?

Difference between Drift Current and Diffusion Currents

Drift Current Diffusion Current

The movement of charge carriers is because of the

applied electric field is known as drift current. The diffusion current can be occurred
because of the diffusion in charge
carriers.

It requires electrical energy for the process of drift Some amount of external energy is
current. enough for the process of diffusion
current.

This current obeys Ohm’s Law. This current obeys Fick’s Law.

The direction of charge carriers in the semiconductor is

reverse to each other.
The direction of the drift current, as well as the
electric field, will be the same.
For charge carriers, the densities of
diffusion are reverse in symbol to each
other.
The direction of this current can be
decided by the concentration of the
carrier slope.

It depends on the permittivity It is independent of

permittivity

The direction of this current mainly depends on the The direction of this current mainly depends
charge within the concentrations of carrier on the polarity of the applied electric field.
Einstein Relationship for semiconductors
PN Junction Diode:

 A PN junction is formed from a piece of semiconductor (Ge or Si) by diffusing p-type material
(Acceptor impurity Atoms) to one half side and N type material to (Donar Impurity Atoms) other
half side. The plane dividing the two zones is known as 'Junction'. The P-region of the
semiconductor contains a large number of holes and N region, contains a large number of electrons.
A PN junction just immediately formed is shown in Fig.

 When PN junction is formed, there is a tendency for the electrons in the N-region to diffuse into
the pregion, and holes from P-region to N-region. This process is called diffusion. While crossing
the junction, the electrons and holes recombines with each other, leaving the immobile ions in the
neighborhood of the junction neutralized as shown in Fig.

 These immobile + ve and –ve ions, set up a potential across the junction. This potential is called
potential barrier or junction barrier. Due to the potential barrier no further diffusion of electrons
and holes takes place across the junction. Potential barrier is defined as a potential difference built
up across the PN junction which restricts further movement of charge carriers across the junction.
The potential barrier for a silicon PN junction is about 0.7 volt, whereas for Germanium PN junction
is approximately 0.3 volt.

Symbol of Diode:

 The symbol of PN junction diode is shown in Fig. The P-type and N-type regions are referred to as
Anode and Cathode respectively. The arrowhead shows the conventional direction of current flow
when the diode is forward biased.

Figure: Symbol of PN diode

Working of PN Junction Diode:

Forward Bias: When the positive terminal of the external battery is connected to the P-region and negative
terminal to the N-region, the PN junction is said to be forward biased as shown in Fig.
 Figure: PN diode Operation

 When the junction is forward biased, the holes in the p-region are repelled by the positive terminal
of the battery and are forced to move towards the junction. similarly, the electrons in the N-region
are repelled by the negative terminal of the battery and are forced to move towards the-junction.

 This reduces the width of the depletion layer and barrier potential. If the applied voltage is greater
than the potential barrier vr, then the majority carriers namely holes in P-region and electrons in N-
region, cross the barrier. During crossing some of the charges get neutralized the remaining charges
after crossing, reach the other side and constitute current in the forward direction.

Figure: PN diode Forward Bias Operation

The PN junction offers very low resistance under forward biased condition. Since the barrier potential is
very small (nearly 0.7 V for silicon and 0.3 V for Germanium junction), a small forward voltage is enough
to completely eliminate the barrier. once the potential barrier is eliminated by the forward voltage, a large
current start flowing through the PN junction.

Reverse Bias:

 When the positive terminal of the external battery is connected to the N-region and negative
terminal to the p-region, the PN junction is said to be reverse biased.

 When the junction is reverse biased, the holes in the P-region are attracted by the negative terminal
of the battery. Similarly, the electrons in the N-region are attracted by the positive terminal of the
external battery. This increases the width of the depletion layer and barrier potential (Vs).

 The increased barrier potential makes it very difficult for the majority carriers to diffuse across the
junction. Thus, there is no current due to majority carriers in a reverse biased PN junction. In other
words, the PN junction offers very high resistance under reverse biased condition.

 In a reverse biased PN junction, a small amount of current (in µA) flows through the junction
because of minority carriers. ( i.e., electrons in the P-region and holes in the N region).The reverse
current is small because the number of majority carrier in both regions is small.

Figure: PN diode Reverse Bias Operation

V-I characteristics of PN junction diode:

Figure: PN diode V-I characteristics

Fig. shows the forward and reverse V-I characteristics of PN junction diode. To apply a forward bias, the
+ve terminal of the battery is connected to Anode (A) and the negative terminal of the battery is connected
to Cathode (K). Now, when supply voltage is increased the circuit current increases very slowly and the
curve is nonlinear (region-OA). The slow rise in current in this region is because the external applied voltage
is used to overcome the barrier potential (0.7 V for Si; 0.3V for Ge ) of the PN junction. However once the
potential barrier is eliminated and the external supply voltage is increased further, the current flowing
through the PN junction diode increases rapidly (region AB). This region of the curve is almost linear. The
applied voltage should not be increased beyond a certain safe limit, otherwise the diode will burnout. The
forward voltage at which the current through the PN junction starts increasing rapidly is called by knee
voltage. It is denoted by the letter VB.

To apply a reverse bias, the +ve terminal of the battery is connected to cathode (K) and - ve terminal of the
battery is connected to anode (A). Under this condition the potential buried at the junction is increased.
Therefore, the junction resistance becomes very high and practically no. current flows through the circuit.
However, in actual practice, a very small current (of the order of µA) flows in the circuit. This current is
called reverse current and is due to minority carriers. It is also called as reverse saturation current (I). The
reverse current increases slightly with the increase in reverse bias supply voltage. If the reverse voltage is
increased continuously at one state (marked by point C on the reverse characteristics) breakdown of junction
occurs and the resistance of the barrier regions falls suddenly. Consequently, the reverse current increases
rapidly (as shown by the curve CD in the current) to a large value. This may destroy the junction
permanently. The reverse voltage at which the PN junction breaks is called as break down voltage.
Diode Equation:

Applications of PN diode:

Due to this characteristic, the diode finds number of applications as given below:
 Diodes are used in clamping circuits for DC restoration.
 Diodes are used in clipping circuits for wave shaping.
 Diodes are used in voltage multipliers.
 Diodes are used as switch in digital logic circuits used in computers.
 Diodes are used in demodulation circuits.
 Laser diodes are used in optical communications.
 Light Emitting Diodes (LEDs) are used in digital displays.
 Diodes are used in voltage regulators.

Rectification
The conversion of alternating current into direct current is known as rectification. A p-n junction diode
allows electric current when it is forward biased and blocks electric current when it is reverse biased. This
action of p-n junction diode enables us to use it as a rectifier.

Figure: PN diode Rectifier applications

Bipolar Junction Transistor:

The transistor is formed by starting with a p-type substrate. An n-type region is thermally diffused through
an oxide window into this p-type substrate. A very heavily doped p+ region is then diffused into the n-type
region. Metallic contacts are made to the p+- and n-regions through the windows opened in the oxide layer
and to the p-region at the bottom.
Normally, the bipolar transistor has three separately doped regions and two p–n junctions. The heavily
doped p+-region is called the emitter (symbol E in the figure). The narrow central n-region, with moderately
doped concentration, is called the base (symbol B). The width of the base is small compared with the
minority carrier diffusion length. The lightly doped p-region is called the collector (symbol C). The doping
concentration in each region is assumed to be uniform.
Figure 2b shows the circuit symbol for a p-n-p transistor. The current components and voltage polarities
are shown in the figure. The arrows of the various currents indicate the direction of current flow under
normal operating conditions (also called the active mode). The + and – signs are used to define the voltage
polarities. We can also denote the voltage polarity by a double subscript on the voltage symbol. In the active
mode, the emitter base junction is forward biased (VEB > 0) and the base-collector junction is reverse biased
(VCB < 0). According to Kirchhoff’s circuit laws, there are only two independent currents for this three-
terminal device. If two currents are known, the third current can be obtained.
The n-p-n bipolar transistor is the complementary structure to the p-n-p bipolar transistor. The structure and
circuit symbol of an ideal n-p-n transistor are shown in Figs. 2c and 2d, respectively. The n-p-n structure
can be obtained by interchanging p for n and n for p in the p-n-p transistor. As a result, the current flows
and voltage polarities are all reversed. In subsequent sections, we concentrate on the p-n-p type because the
direction of minority-carrier (hole) flow is the same as that of current flow. It provides a more intuitive base
for understanding the mechanisms of charge transport. Once we understand the p-n-p transistor, we need
only reverse the polarities and conduction types to describe the n-p-n transistor.

Operation in the Active Mode

Figure 3a show an idealized p-n-p transistor in thermal equilibrium, that is, when all three leads are
connected together or all are grounded. The depletion regions near the two junctions are illustrated by
colored areas. Figure 3b shows the impurity densities in the three doped regions, where the emitter is more
heavily doped than the collector. However, the base doping is less than the emitter doping but greater than
the collector doping. Figure 3c shows the corresponding electric-field profiles in the two depletion regions.
Figure 3d illustrates the energy band diagram, which is a simple extension of the thermal-equilibrium
situation for the p–n junction applied to a pair of closely coupled p+-n and n-p junctions. The results
obtained for the p–n junction in Chapter 3 are equally applicable to the emitter-base and base-collector
junctions. At thermal equilibrium there is no net current flow, and hence the Fermi level is a constant in the
regions.

Figure 4 shows the corresponding cases when the transistor in Fig. 3 is biased in the active mode. Figure
4a is a schematic of the transistor connected as an amplifier with the common-base configuration, that is,
the base lead is common to the input and output circuits.3 Figures 4b and 4c show the charge densities and
the electric fields, respectively, under biasing conditions. Note that the depletion layer width of the emitter-
base junction is narrower and the collector-base junction is wider than in the equilibrium case in Fig. 3.
Figure 4d shows the corresponding energy band diagram under the active mode. Since the emitter-base
junction is forward biased, holes are injected (or emitted) from the p+ emitter into the base and electrons
are injected from the n base into the emitter. Under the ideal-diode condition, there is no generation-
recombination current in the depletion region; these two current components constitute the total emitter
current. The collector base junction is reverse biased and a small reverse saturation current will flow across
the junction. However, if the base width is sufficiently small, the holes injected from the emitter can diffuse
through the base to reach the base-collector depletion edge and then “float up” into the collector (recall the
“bubble analogy”). This transport mechanism gives rise to the terminology of emitter, which emits or injects
carriers, and collector, which collects these carriers injected from a nearby junction. If most of the injected
holes can reach the collector without recombining with electrons in the base region, the collector hole
current will be very close to the emitter hole current. Therefore, carriers injected from a nearby emitter
junction can result in a large current flow in a reverse-biased collector junction. This is the transistor action,
and it can be realized only when the two junctions are physically close enough to interact in the manner
described. The two junctions are called the interacting p–n junctions. If, on the other hand, the two junctions
are so far apart that all the injected holes are recombined in the base before reaching the base-collector
junction, then the transistor action is lost and the p-n-p structure becomes merely two
diodes connected back to back.
Current Gain
Figure 5 shows the various current components in an ideal p-n-p transistor biased in the active mode. Note
that we assume that there are no generation-recombination currents in the depletion regions. The holes
injected from the emitter constitute the current IEp, which is the largest current component in a well-
designed transistor.
Most of the injected holes will reach the collector junction and give rise to the current ICp. There are three
base current components, labeled IBB, IEn, and ICn. IBB corresponds to electrons that must be supplied by
the base to replace electrons recombined with the injected holes (i.e., IBB = IEp – ICp). IEn corresponds to
the current arising from electrons being injected from the base to the emitter. However, IEn is not desirable,
as shown later. It can be minimized by using heavier emitter doping (Section 4.2) or a heterojunction
(Section 4.5). ICn corresponds to thermally generated electrons that are near the base-collector junction
edge and drift from the collector to the base. As indicated in the figure, the direction of the electron current
is opposite the direction of the electron flow. We can now express the terminal currents in terms of the
various current components described above:
MOSFETs:

Basic Characteristics
The source contact is used as the voltage reference throughout this section. When no voltage is applied to
the gate, the source-to-drain electrodes correspond to two p–n junctions connected back to back. The only
current that can flow from the source to drain is the reverse-leakage current.† When we apply a sufficiently
large positive bias to the gate, the MOS structure is inverted so that a surface inversion layer (or channel)
is formed between the two n+- regions. The source and drain are then connected by a conducting surface
n-channel through which a large current can flow. The conductance of this channel can be modulated by
varying the gate voltage. The substrate contact can be at the reference voltage or is reverse biased with
respect to the source; the substrate bias voltage will also affect the channel conductance.

Linear and Saturation Regions

We now present a qualitative discussion of MOSFET operation. Let us consider that a voltage is applied to
the gate, causing an inversion at the semiconductor surface (Fig. 22). If a small drain voltage is applied,
electrons will flow from the source to the drain (the corresponding current will flow from drain to source)
through the conducting channel. Thus, the channel acts as a resistor, and the drain current ID is proportional
to the drain voltage. This is the linear region, as indicated by the constant-resistance line in the right-hand
diagram of Fig. 22a.
When the drain voltage increases, eventually it reaches VDsat, at which the thickness of the inversion layer
xi near y = L is reduced to zero; this is called the pinch-off point, P (Fig. 22b). Beyond the pinch-off point,
the drain current remains essentially the same, because for VD > VDsat, at point P the voltage VDsat remains
the same. Thus, the number of carriers arriving at point P from the source or the current flowing from the
drain to the source remains the same. This is the saturation region, since ID is a constant regardless of an
increase in the drain voltage.
The major change is the decrease of L to the value L′ shown in Fig. 22c. Carrier injection from P into the
drain depletion region is similar to that of carrier injection from an emitter-base junction to the base-
collector depletion region of a bipolar transistor.
We now derive the basic MOSFET characteristics under the following ideal conditions. (a) The gate
structure corresponds to an ideal MOS capacitor, as defined in Section 5.1, that is, there are no interface
traps, fixed-oxide charges, or work function differences. (b) Only drift current is considered. (c) Carrier
mobility in the inversion layer is constant. (d) Doping in the channel is uniform. (e) Reverse-leakage current
is negligibly small. (f) The transverse field created by the gate voltage (E x in the x-direction, shown in Fig.
21, which is perpendicular to the current flow)
in the channel is much larger than the longitudinal field created by the drain voltage (Ey in the y-direction,
which is parallel to the current flow). The last condition is called the gradual-channel approximation and
generally is valid for long-channel MOSFETs. Under this approximation, the charges contained in the
surface depletion region of the substrate are induced solely from the field created by the gate voltage.
Figure 23a shows the MOSFET operated in the linear region. Under the above ideal conditions, the total
charge induced in the semiconductor per unit area, Qs, at a distance y from the source is shown in Fig. 23b,
which is an enlarged central section of Fig. 23a. Qs is given from Eqs. 13 and 14 by
Types of MOSFET
There are basically four types of MOSFETs, depending on the type of inversion layer. If, at zero gate bias,
the channel conductance is very low and we must apply a positive voltage to the gate to form the n-channel,
then the device is a normally off (enhancement) n-channel MOSFET. If an n-channel exists at zero bias and
we must apply a negative voltage to the gate to deplete carriers in the channel to reduce the channel
conductance, then the device is a normally on (depletion) n-channel MOSFET. Similarly, we have the p-
channel normally off (enhancement) and normally on (depletion) MOSFETs.
The device cross sections, output characteristics (i.e., ID versus VD), and transfer characteristics (i.e., ID
versus VG) of the four types are shown in Fig. 26. Note that for the normally off n-channel device, a positive
gate bias larger than the threshold voltage VT must be applied before a substantial drain current flows. For
the normally on n-channel device, a large current can flow at VG = 0, and the current can be increased or
decreased by varying the gate voltage. This discussion can be readily extended to p-channel device by
changing polarities.

Challenges for Nano MOSFETs (Scaling Issues):

Scaling down of MOSFET’s dimensions is a continuous trend since its inception. Smaller device size makes
possible higher device density in an integrated circuit. In addition, a smaller channel length improves the
driving current (ID ~ 1/L) and thus the operation performance. As a device’s dimensions are reduced,
however, influences from the side regions of the channel (i.e., source, drain, and isolation edge) become
significant. Device characteristics, therefore, deviate from those derived from gradual-channel
approximation for long-channel MOSFETs.
Short-Channel Effects
The threshold voltage given in Eq. 47 is derived based on the gradual-channel approximation stated in
Section 5.5.1. That is, the charges contained in the surface depletion region of the substrate are induced
solely from the field created by the gate voltage. In other words, the third term on the right-hand side of Eq.
47 in Chapter 5 is independent of the lateral fields from the source and drain. As channel length is reduced,
however, the fields originating from the source/drain regions may influence the charge distribution and,
thus, device characteristics such as the threshold voltage control and device leakage. When the source and
drain depletion regions become a substantial fraction of the channel length, short channel effects start to
occur.

Threshold Voltage Roll-off in Linear Region

For long-channel devices, the charge reduction is smaller, since Δ (Fig. 2c) is much smaller than L. For
short channel devices, however, the charges needed to turn on the device are dramatically reduced, since Δ
is comparable to L. As can be seen from Eq. 1, for a given set of NA, Wm , rj and Co, the threshold voltage
decreases with decreasing channel length.

Drain-Induced Barrier Lowering (DIBL)

For an n-channel MOSFET, the p-Si substrate forms a potential barrier between n+ source and drain and
limits the electron flow from source to drain. In the long-channel case operated in the saturation region, the
increase in depletion-layer width of the drain junction will not affect the potential barrier height at the
source end shown in Fig. 3a. That is to say, for a long-channel device a drain bias can change the effective
channel length but the barrier at the source end remains constant. When the drain is close to the source, as
in a short-channel MOSFET, the drain bias can influence the barrier height at the source end. This is
ascribed to the field penetration at the surface region from the drain to the source. Figure 3b shows the
energy bands along the semiconductor surface. For a short-channel device, this lowered barrier with
decreasing channel length or increasing drain bias is commonly called drain-induced barrier lowering
(DIBL). The lowering of the source barrier causes an injection of extra carriers from the source to the drain,
thereby increasing the current substantially. This increase of current will be shown in both the above-
threshold and subthreshold regions, and the threshold voltage will decrease with increasing drain bias.
Figure 4 illustrates the subthreshold characteristics of a long and a short n-channel MOSFET at low and
high drain bias conditions. The parallel shift in subthreshold current in the short-channel device (Fig. 4b)
as the drain voltage increases indicates that a significant DIBL effect has been induced.

Bulk Punch-through
DIBL causes the formation of a leakage path at the SiO2/Si interface. If the drain voltage is large enough,
significant leakage current may also flow from drain to source via the bulk of the substrate for a short-
channel MOSFET. This is also ascribed to the increase in the depletion-layer width of the drain junction
with increasing drain voltage.
In the extreme case for a short-channel MOSFET, the sum of depletion-layer width for source and drain
junctions is comparable to the channel length (yS + yD ≅ L). The depletion region of the drain junction
gradually merges with that of the source junction as the drain voltage is increased. An example of severe
punch-through characteristics above threshold is shown in Fig. 5a. For this device, at VD = 0 the sum of yS
and yD is 0.26 μm, which is larger than the channel length of 0.23 μm. Therefore, the depletion region of
the drain junction has reached the depletion region of the source junction. Over the drain range shown, the
device is operated in punchthrough condition. Electrons in the source region can be injected into the
depleted channel region, where they
SOI MOSFET

For certain applications, MOSFETs are fabricated on an insulating substrate rather than on a semiconductor
substrate. The characteristics of these transistors are similar to those of an MOSFET. Usually, we call such
devices thin film transistors (TFT) if the channel layer is an amorphous or polycrystalline silicon. If the
channel layer is a monocrystalline silicon, we call it silicon-on-insulator (SOI).

Thin Film Transistor (TFT)

Hydrogenated amorphous silicon (a-Si:H) and polysilicon are the two most popular materials for TFT
fabrication. They are usually deposited on an insulating substrate such as a glass, quartz, or Si substrate
with a thin SiO2 capping layer. The a-Si:H TFT is an important device in electronic applications that require
a large area, such as liquid crystal displays (LCD) and contact imaging sensors (CIS). The a-Si:H materials
are usually deposited with a plasma-enhanced chemical vapor deposition (PECVD) system. Since the
deposition temperature is low (typically 200° – 400°C), inexpensive substrate materials such as glass can
be used. The role played by the hydrogen atoms contained in the a-Si:H is to passivate dangling bonds in
the amorphous silicon matrix and thus reduce the defect density. Without hydrogen passivation, the gate
voltage cannot adjust the Fermi level at the insulator and the a-Si interface, since the Fermi level is pinned
by the large amount of defects. The a-Si:H TFT is usually fabricated using the inverted staggered structure,
as shown in Fig. 20. The inverted staggered structure is a bottom-gate scheme. A metal gate can be used
since the post-process temperature is low (< 400°C). A dielectric layer such as silicon nitride or silicon
dioxide, also deposited by PECVD, is often used as the gate dielectric. An undoped a-Si:H layer is
subsequently deposited to form the channel. The source and drain of the TFT are formed with an in situ–
doped n+ a-Si:H layer complying with the requirement of low process temperature. A dielectric layer that
serves as an etch- stop for patterning of n+ a-Si:H is often used. Device characteristics of TFTs with the
bottom-gate structure are usually better than those with the top-gate structure.
This is because the a-Si:H channel could be damaged by plasma during PECVD gate-dielectric deposition
of top-gated TFTs. In addition, the source/drain formation process is easier for the bottom-gate structure.
A typical subthreshold characteristic of the a-Si:H TFT is shown in Fig. 21. Because of the amorphous
matrix present in the channel material, its carrier mobility is usually very low (< 1 cm2/V-s). The polysilicon
TFT uses a thin polysilicon as the channel layer. Polysilicon consists of many Si grains. Within the grains
are the monocrystalline Si lattices. The orientations of two side-by-side grains are, however, different from
each other. The interface between the two grains is called the grain boundary. Polysilicon TFT exhibits
much higher carrier mobility and thus better drive capability than a-Si:H TFT because of higher
crystallinity. Carrier mobility of these devices typically ranges from 10 to several hundred cm2/V-s,
depending on the grain size and process conditions. Polysilicon is usually deposited with low-pressure CVD
(LPCVD). The grain size of polysilicon is an important factor in determining TFT performance, since the
carrier mobility generally decreases with decreasing grain size. This is mainly because of the large number
of defects contained in the grain boundaries that impede the transport of carriers.

The defects at the grain boundary can also affect the threshold voltage and subthreshold swing of the device.
When gate voltage is applied to induce an inversion layer in the channel, these defects act as traps and
impede the movement of the Fermi level in the forbidden gap. To alleviate these drawbacks, a
hydrogenation step is often adopted after device fabrication. The hydrogenation treatment is usually done
in a plasma reactor. Hydrogen atoms or ions generated in the plasma diffuse into the grain boundaries and
passivate these defects. After hydrogenation, there is significant improvement in device performance.
Unlike a-Si:H TFT, polysilicon TFT is usually fabricated with the top-gate structure, as shown in Fig. 22.
A self-aligned implant is used to form the source/drain. One main limitation of polysilicon TFT
manufacturing is the high process temperature (> 600°C). Consequently, expensive substrates such as
quartz are usually needed to tolerate the high process temperatures. This makes polysilicon TFT less
attractive than a-Si:H TFT in production for low-end applications because of higher cost. Laser
crystallization of Si is a potential way to overcome the problem. In this method, an a-Si layer is deposited
first on a glass substrate at low temperatures by PECVD or LPCVD. A high-power laser source is then used
to irradiate the a-Si. The energy is absorbed by the a-Si and melting occurs locally in the a-Si layer. After
cooling, the a-Si turns into polysilicon with very large grain size (≥ 1 μm). Very high carrier mobility,
approaching that of crystalline Si MOSFETs, can be obtained using this method.
Double gate MOSFET (Working Principle):
The working principle of a double-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is
similar to that of a traditional MOSFET, with the key difference being the presence of two gates. Double-
gate MOSFETs are often implemented as FinFETs, and I'll use this type as an example for explanation. The
working principle involves the control of current flow between the source and drain terminals through the
manipulation of charge carriers in a semiconductor channel.

Here are the key steps in the operation of a double-gate MOSFET (FinFET):
Basic Structure:

The double-gate MOSFET consists of a thin silicon fin that acts as the channel. This fin is raised above the
insulating substrate. Two gate terminals are placed on either side of the fin, providing independent control
over the channel.

Zero Bias (No Applied Voltage):

In the absence of an applied voltage, the device is in its off-state. The insulating material (oxide) between
the gates and the channel prevents the flow of charge carriers.

Applying Voltage to Gates:

When a voltage is applied to the gates, an electric field is created in the channel region. The gates are
designed to control the flow of charge carriers (electrons for n-type MOSFETs, and holes for p-type
MOSFETs) in the channel.
Threshold Voltage and Channel Formation:

When the voltage applied to the gates reaches a certain threshold, it induces a strong electric field in the
channel. This electric field attracts or repels charge carriers, forming a conductive channel in the silicon fin
between the source and drain.

Control of Current Flow:

The voltage on the gates controls the number of charge carriers in the channel, determining the conductivity
of the channel. By independently adjusting the voltages on the two gates, the device allows for fine control
over the flow of current.

Off-State and On-State:

When the gates have low or no voltage, the channel is effectively turned off, and the device is in its off-
state. When appropriate voltages are applied to the gates, the channel is turned on, allowing current to flow
from the source to the drain, and the device is in its on-state.

Advantages:

The double-gate structure provides better electrostatic control over the channel, reducing leakage current
and improving performance compared to traditional single-gate MOSFETs. In summary, the double-gate
MOSFET, such as the FinFET, leverages the presence of two gates to enhance control over the channel and
improve the overall performance and efficiency of the transistor in electronic devices.

FinFET

To overcome short channel effects, three-dimensional MOSFETs were developed as discussed in Chapter
6, Section 6.3.3. Among them, FinFET is a typical structure. The device structure of the FinFET is shown
in Fig.24. The channel was formed on the side “vertical” surface of the Si-fin, and the current flows in
parallel to the wafer surface. The heart of the FinFET is a thin (~10 nm) Si fin that serves as the body of
the MOSFET. A heavily doped poly-Si film wraps around the fin and makes electrical contact with its
vertical faces. The poly-Si film greatly reduces the source/drain series resistance and provide a convenient
means for local interconnect and making connections to the metal. A gap is etched through the poly-Si film
to separate the source and drain.

The width of this gap, further reduced by the dielectric spacers, determines the gate length. The channel
width is basically twice the fin height (plus the fin width). The conducting channel is wrapped around the
surface of the fin (hence the name FinFET). Because the source/drain and gate are much thicker (taller)
than the fin, the device structure is quasiplanar.
The typical fabrication sequence is shown in Fig. 25.
1. A conventional SOI wafer with a 400-nm thick buried oxide layer and 50-nm thick silicon film can be
used as the starting material, except that the alignment notch of the wafer is preferably rotated 45° about
the axis of symmetry of the wafer. The reason for this deviation is to provide {100} planes on silicon fins.
2. The CVD Si3N4 and SiO2 stack layer is deposited on the silicon film to make a cover layer that will
protect the Si-fin through the fabrication process. The fine Si-fin is patterned by electron beam lithography.
3. Phosphorus-doped amorphous Si (for source and drain pads) is deposited at 480oC, and will be
polycrystallized in the following step. After amorphous Si deposition, SiO2 is deposited at 450oC. The
process temperatures are low enough to suppress impurity diffusion into the Si fin.
4. Using electron-beam lithography, the S/D pads with a narrow gap in between them are delineated. The
SiO2 and amorphous Si layers are etched and the gap is formed. While the cover layer protects the Si fin,
the amorphous Si is completely removed from the side of the Si fin. The amorphous Si in contact with the
Si fin at its side surfaces becomes the impurity diffusion source that forms the transistor S/D later.
5. CVD SiO2 is deposited to make spacers around the S/D pads. The height of the Si fin is 50 nm, and the
total pads thickness is 400 nm. Making use of the difference in the heights, the SiO2 spacer on the sides of
the Si-fin is completely removed by over etching of SiO2 while the cover layer protects the Si-fin. The Si
surface is again exposed on the sides of the Si fin. During this over-etching, SiO2 on the S/D pads and the
buried oxide between S/D pads are etched.
6. By oxidizing the Si surface, gate oxide as thin as 2.5 nm is grown. During gate oxidation, the amorphous
Si of the S/D pads is crystallized. Also, phosphorus diffuses from the S/D pads into the Si fin and forms the
S/D extensions under the oxide spacers. Then, the gate deposition follows.
Insulated Gate Field Effect Transistor (IGFET)
IGFET stands for Insulated Gate Field Effect Transistor, and it is a type of transistor that includes Metal-
Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Metal-Semiconductor Field Effect
Transistors (MESFETs). MOSFET is the most common type of IGFET and the working principle are
similar to MOSFET.

Figure: Insulated Gate Field Effect Transistor