BCSE205L - Computer Architecture and Organization

L T PC
3 0 0 3

Dr. M. Bhuvaneswari
Assistant Professor Senior Gr.2
School of Computer Science and Engineering
Vellore Institute of Technology, Vellore
m.bhuvaneswari@vit.ac.in
 BCSE205L - Computer Architecture and Organization
• Syllabus

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 Connection between processor and memory
• Address bus provides the address of the memory location to be accessed.
• Data bus transfers the data read from memory, or data to be written into
memory
• Bidirectional
• Control bus provides various signals like READ, WRITE, etc.

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 An Example Memory Module
• n address lines - The maximum number of memory locations that can be
accessed is 2n
• m data lines - The number of bits stored in every addressable location is
m.
• The RD/WR’ control line selects the memory for reading or writing (1:
read, 0: write).
• The chip select line (CS’) when active (=0) will enable the chip;
otherwise, the data bus is in the high impedance state.

Total Size of the Memory = 2n X m

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 Conceptual view of memory cell
• Organization of cells in an 8 X 4 Memory Chip

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 Organization of cells in an 8 X 4 Memory Chip
• A 32 bit memory chip organized as 8 X 4 is shown.
• Every row of the cell array constitutes a memory word.
• A 3 X 8 decoder is required to access any one of the 8 rows.
• The rows of the cells are connected to the word lines.
• Individual cells are connected to two bit lines.
• Bit b and its complement b’.
• Required for reading and writing.

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 Organization of cells in an 8 X 4 Memory Chip
• Cells in each column are connected to a sense / write circuit by the two
bit lines.
• Other than address and data lines, there are two control lines: R/W’ and
CS’ (Chip Select).
• CS is required to select one single chip in a multi-chip memory system.

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 External Connection to the 8 X 4 memory chip
• The 8 X 4 memory requires the following external connections:
• Address decoder of size: 3 X 8
• 3 external connections for address.
• Data output : 4 bit
• 4 external connections for data.
• 2 external connections for R/W’ and CS’.
• 2 external connection for power supply and ground.
• Total of 3 + 4 + 2 + 2 = 11.

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 External Connection to the 256 X 16 memory chip
• Address decoder size: 8 X 256
• 8 external connections for address.
• Data output : 16 bit
• 16 external connections for data.
• 2 external connections for R/W’ and CS’.
• 2 external connections for power supply and ground.
• Total of 8 + 16 + 2 + 2 = 28.

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 Memory Interface Signals
• The data signals of a memory module (RAM) are typically bidirectional.
• Some memory chips may have separate data in and data out lines.
• For memory READ operation:
• Address of memory location is applied to address lines.
• RD/WR’ control signal is set to 1, and CS’ is set to 0.
• Data is read out through the data lines after memory access time delay.
• For memory WRITE operation:
• Address of memory location is applied to address lines, and the data to
be written to data lines.
• RD/WR’ control signal is set to 0, and CS’ is set to 0.

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 Memory Interface Signals
• Why is CS’ signal required?
• To handle multiple memory modules interfacing problem
• We typically select only one out of several memory modules at a
time.
• What happens when CS’ = 1?
• When a memory module is not selected, the data lines are set to the
high impedance state (i.e electrically disconnected).
• An example scenario is shown.

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 Construction of larger size memories
• How Larger Memories are built from Smaller Memory Modules?
• How many 128 X 8 RAM chips are required to construct 2048 X 8
memory system?
• Solution
• No of memory chip required = 2048 X 8/ 128 X 8 = 16 number of
128 X 8 RAM chips are required to construct 2048 X 8 memory
system

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 Construction of larger size memories
• How Larger Memories are built from Smaller Memory Modules?
• How many 128 X 8 RAM chips are required to construct 2048 X 8
memory system?
• Solution
• No of memory chip required = 2048 X 8/ 128 X 8 = 16 number of
128 X 8 RAM chips are required to construct 2048 X 8 memory
system

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 Construction of larger size memories
• Memory Address Map
• How 16 number of 128 X 8 RAM chips are organized to construct
2048 X 8 memory system and discuss about the memory address
map?
• Solution
• To access 2048 X 8 memory system, we need 11 bits of address
(A10,...,A0). But we organize 16 number of 128 X 8 RAM chips
together to make it.
• To access 128 X 8 memory system,
we need 7 bits of address (A6,...,A0).

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 Construction of larger size memories
• Memory Address Map
• How 16 number of 128 X 8 RAM chips are organized to construct
2048 X 8 memory system and discuss about the memory address
map?
Hence, higher order 4 bits (A10,
A9,A8,A7) will be used to select
one of the 128 X 8 RAM chips.
Eg.: 1111 means 15th RAM chip

The bits from A6 to A0 will be

used to access one word from
the selected 128 X 8 RAM chips.
Eg.: 1111 0000001 means
1st word of 15th RAM chip

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 Construction of larger size memories
• How Larger Memories are built from Smaller Memory Modules?
• How many 128 X 8 RAM chips are required to construct 2048 X 16
memory system?
• Solution
• No of memory chip required = 2048 X 16/ 128 X 8 = 32 number of
128 X 8 RAM chips are required to construct 2048 X 16 memory
system

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 Construction of larger size memories
• Memory Address Map
• How 128 X 8 RAM chips are organized to construct 2048 X 16
memory system and discuss about the memory address map?
Hence, higher order 4 bits (A10,
A9,A8,A7) will be used to select
pair of the 128 X 8 RAM chips.
Eg.: 1111 means pair of
15th RAM chips

The bits from A6 to A0 will be

used to access one word (16 bits)
from the selected pair of 128 X 8
RAM chips.
Eg.: 1111 0000001 means
1st words (8+8 bits) from the pair
Of 15th RAM chip
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Memory Interfacing and Addressing

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Memory Interfacing and Addressing

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 Memory Interfacing
• Consider the real processor with 32 bit address
• Hence Maximum size of the memory can be connected is 232 = 4GBytes
• Processor data lines are 8 bits
• Assume that we have only 1Gbyte memory chips (RAM).
• 230 = 1GByte (30 bits address and 8 bits data)
• To construct 4GBytes of memory system, we need to connect 4 number of
1Gbyte memory chips to the processor.

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 Memory Interfacing
• Consider the real processor with 32 bit address
• To construct 4GBytes of memory system, we need to connect 4 number of
1Gbyte memory chips to the processor.
• Lower order 30 (A29,...,A0) address lines are connected to the memory
module and higher order (A31,A32) used to select one of the 4 modules.

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Memory Interfacing

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 Memory Interfacing
Issue in this memory organization??!!

How this can be resolved??? – 32 bits of data need to be fetched in

single memory access cycle – Exploit the concept memory interleaving.

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 Memory Interfacing
How are the addresses are mapped to the memory module?

Here memory address are interleaved across the memory modules.

Consecutive words are present in consecutive memory modules.
Benefits over this mapping technique:
• It is possible to access 4 consecutive words in the same cycle, if four
modules are enabled simultaneously.

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 Memory Interleaving

Still one of the modules is selected at a time. 8 bits data transfer per
cycle.

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 Memory Interleaving

• All modules is selected (CS=0) at a time because the address decoder has
been removed .
• Since the data line can transfer 32 bits, we can access all four modules (8
bits from each) parallel and 32 bits data can be transferred to the processor
in a single cycle. 26