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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2798611, IEEE
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A Space Vector Modulation Scheme of

Quasi-Z-Source Three-Level T-Type Inverter
for Common-Mode Voltage Reduction
Changwei Qin, Chenghui Zhang, Senior Member, IEEE, Alian Chen, Member, IEEE,
Xiangyang Xing, Student Member, IEEE, and Guangxian Zhang

Abstract—The conventional three-level inverter suffers ac voltage higher than the dc-link voltage. In practical ap-
the limitation of voltage buck operation. In order to give plications, e.g., PV system, a dc-dc boost converter is usually
both voltage buck and boost operation capability, the quasi- added before the inverter, which increases the cost and control
Z-source three-level T-type inverter (3LT2 I) has been pro-
posed. This paper further proposes a space vector modu- complexity [6].
lation (SVM) scheme for quasi-Z-source 3LT2 I to reduce the In order to solve the problem, Prof. F. Z. Peng proposed
magnitude and slew rate of common-mode voltage (CMV). a Z-source topology, which can provide voltage boosting
By properly selecting the shoot-through phase, the shoot- capability in a single stage by employing an impedance
through states are inserted within zero vector in order not network to couple the inverter main circuit to the dc power
to affect the active states and output voltage. Doing so, the
CMV generated by the quasi-Z-source 3LT2 I is restricted source [7]. In three-level topology, the conventional Z-source
within one-sixth of dc-link voltage, and voltage boosting three-level NPC inverter was proposed in [8], where two
and CMV reduction can be simultaneously realized. In addi- additional Z-source networks were adopted, and voltage buck-
tion, high dc-link voltage utilization can be maintained. The boost conversion can be achieved. However, two Z-source
proposed scheme has been verified in both simulations and networks increase the system cost. Therefore, the three-level
experiments. Comparisons are conducted with convention-
al SVM method and phase-shifted sinusoidal PWM method. NPC inverter with a single Z-source network was presented
in [9], and the system cost can be decreased. Alternative phase
Index Terms—Voltage boosting, common-mode voltage opposition disposition modulation scheme was also designed.
(CMV) reduction, quasi-Z-source, three-level T-type inverter
(3LT2 I).
Operational analysis and phase disposition carrier-based mod-
ulation technique of Z-source three-level NPC inverter were
presented in [10], and output waveforms with better quality
I. I NTRODUCTION and lower current ripple can be achieved. However, the input

I
current of Z-source three-level NPC inverter is discontinuous
N recent years three-level inverters have been widely used
in nature, which restricts its applications in PV generation
in various industrial applications like photovoltaic (PV)
system and fuel cell system.
generation system [1], wind turbine system [2], medium-
As a derivative of Z-source inverter, the quasi-Z-source
voltage ac drives [3], etc. Compared to the three-level neutral
inverter was proposed to reduce component ratings and obtain
point clamped (NPC) inverter, the three-level T-type inverter
the continuous input current [11]. Quasi-Z-source inverter has
(3LT2 I) employs a bidirectional switch to the dc-link voltage
been used in many energy conversion applications, such as PV
midpoint, and this bidirectional switch blocks only half of the
generation system and auxiliary power supply [6], [12]. Sev-
dc-link voltage. The 3LT2 I combines advantages of both two-
eral modulation methods have been proposed to control quasi-
level inverters and three-level inverters, such as simple opera-
Z-source inverters in [13]–[16]. The quasi-Z-source three-level
tion principle, low conduction losses and switching losses, and
NPC inverter topology, presented in [17], combines advantages
good output voltage quality [4], [5]. The efficiency of 3LT2 I
of three-level NPC inverter and quasi-Z-source inverter, such
is outstanding for medium switching frequencies from 4 to
as superior output waveforms, low voltage stress of power
30 kHz [4].
devices, single-stage energy conversion, and continuous input
However, like other three-level NPC inverters, the 3LT2 I
current. The quasi-Z-source 3LT2 I was presented in [18], and
only has voltage buck capability, and it is unable to output
a phase-shifted sinusoidal PWM scheme was proposed. A
Manuscript received July 29, 2017; revised October 25, 2017 and three-level LC-switching based voltage boost NPC inverter
January 5, 2018; accepted January 10, 2018. This work was supported with continuous input current was proposed in [19]. Since
in part by the National Natural Science Foundation of China (61527809, less number of passive elements were used, system size and
61703239 and 51377101) and in part by the Major International (Re-
gional) Joint Research Project of the National Natural Science Founda- weight can be reduced, and two additional power switches
tion of China (61320106011). (Corresponding author: Chenghui Zhang.) were adopted in the intermediate network. A high voltage gain
The authors are with the School of Control Science and En- factor can be achieved by using this topology.
gineering, Shandong University, Jinan 250061, China (e-mail: qin-
changwei2008@[Link]; zchui@[Link]; chenalian@[Link]; Due to high voltage utilization and superior output wavefor-
xxy198513@[Link]; zgx@[Link]). m, space vector modulation (SVM) scheme was employed in

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Z-source and quasi-Z-source inverter [13]. The SVM method C1

iIN L1 D1 L2
of Z-source three-level NPC inverter was developed in [20],
and the upper-shoot-through states and lower-shoot-through
states were inserted to conventional seven-segment switching C2
C Lf Zl
sequences. In [21], the switching sequence was modified by vdc_link Sa1
Vdc O B
Sa2 Sa3
properly adding or subtracting a percentage of the minimum A
turn-on time to balance neutral-point potential in Z-source C3
3LT2 I. L3 D2 L4
Sa6 Cf

Common-mode voltage (CMV) will be generated by the Sa4

C4
inverter system, and the high magnitude, high frequency, and
Quasi-Z-source network Three-level T-type inverter LC filter Load
slew rate (dv/dt) of CMV cause some unwanted problems,
such as shaft voltage, ground leakage and bearing currents, Fig. 1. Topology of quasi-Z-source 3LT2 I.
as well as electromagnetic interference (EMI) [22]–[24]. For
PV generation system, the CMV can cause leakage current to TABLE I
flow into the ground [25]. A modulation technique that used S WITCHING S TATES OF Q UASI -Z-S OURCE 3LT2 I (x = a, b, c)
only medium vectors and zero vector to synthesis the reference
vector was proposed in [26] to eliminate the leakage current. State of Operation ON switches Output Voltage
However, the maximum output voltage of the inverter is P State Sx1 , Sx2 +Vdc link /2
smaller than that of the conventional PWM method. The large, O State Sx2 , Sx3 0
N State Sx3 , Sx4 −Vdc link /2
medium, and zero vector modulation (LMZVM) strategy was
Shoot-through State (F State) Sx1 , Sx2 , Sx3 , Sx4 0
proposed in [27], and the magnitude of CMV can be restricted
within one-sixth of dc voltage. Since no small vectors are
adopted, neutral point voltage self-balancing can be obtained
Like the conventional Z-source inverters, the quasi-Z-source
in three-phase symmetrical case by using this strategy. How-
3LT2 I is able to operate in shoot-through mode and non-shoot-
ever, this strategy cannot be directly implemented in quasi-Z-
through mode. Shoot-through states can be realized by turning
source 3LT2 I, because it does not contain shoot-through state
on all the switches in one phase leg of the inverter, which
and voltage boosting capability cannot be realized.
provides approaches for boost operation. In non-shoot-through
In this paper, a SVM scheme for quasi-Z-source 3LT2 I is
mode, the energy stored in quasi-Z-source network and dc
proposed. In this scheme, large, medium, zero, and shoot-
power source is transmitted to the load through the 3LT2 I.
through voltage vectors are adopted to synthesis the reference
It is worth mentioning that the quasi-Z-source 3LT2 I does not
voltage vector. By properly selecting shoot-through phase
need dead-time for short-circuit protection. Thus, performance
according to sector number, shoot-through states are inserted
limitations resulted from dead-time can be avoided, and the
within zero vector [OOO] to realize voltage boosting. The
system reliability can be increased.
zero voltage vector and shoot-through voltage vectors have
One phase leg is considered to describe the operational
the same output voltage across the load, i.e., 0 V, so the
principle of the quasi-Z-source 3LT2 I. Selecting the common
normalized volt-second balance is not affected. Dwell times
point O of two quasi-Z-source networks as the reference,
of voltage vectors are calculated through the modified volt-
switching states and the corresponding output voltages of the
second balance principle. Although the CMV is not completely
quasi-Z-source 3LT2 I is summarized in Table I. It can be seen
eliminated, its magnitude can be restricted within one-sixth of
that shoot-through state (denoted as F State) is obtained by
dc-link voltage, and its slew rate is also reduced. What’s more,
turning on all the switches in one phase leg.
the modulation index is not affected, and high dc-link voltage
Considering that the quasi-Z-source network is symmetrical
utilization can be maintained.
( C1 = C4 , C2 = C3 , L1 = L3 , and L2 = L4 ), then vC1 =
The rest of this paper is organized as follows. Section II
vC4 , vC2 = vC3 , vL1 = vL4 , and vL2 = vL3 . Detailed steady
presents the topology of quasi-Z-source 3LT2 I and its oper-
state analysis of quasi-Z-source 3LT2 I is similar to that of
ational principle. In Section III, the proposed SVM scheme
quasi-Z-source three-level NPC inverter [12], and the boost
is elaborated in detail. Simulation results based on MAT-
factor can be expressed as
LAB/Simulink and experimental results based on an exper-
imental prototype are presented in Section IV and Section V, Vdc link 1
B= = (1)
respectively. Section VI concludes this paper. Vdc 1 − 2dST
where B is the boost factor, Vdc link is the magnitude of dc-
II. Q UASI -Z-S OURCE 3LT2 I link voltage, and Vdc is the dc input voltage. dST is the shoot-
The topology of quasi-Z-source 3LT2 I is drawn in Fig. 1, through duty cycle given by dST = tST /Ts , tST is the shoot-
where the dc power source and 3LT2 I are connected by through interval, and Ts is the switching period.
an intermediate network consisting of two identical quasi-Z- In steady state, the sum of capacitor voltages vC2 and vC3
source networks, and the common point is connected to the can be expressed as [12]
neutral point of the 3LT2 I. The 3LT2 I uses a bidirectional
switch to connect to the neutral point , and this bidirectional 1 − dST
vC2 + vC3 = · Vdc (2)
switch blocks only half of the dc-link voltage. 1 − 2dST

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TABLE II A. Duty Cycle Calculation

V ECTORS AND C OMMON - MODE VOLTAGES OF 3LT2 I #»
Assuming the reference voltage vector V ref is located in
#» #»
Sector 1, large vector V 13 , medium vector V 7 , and zero vector
Vectors State vCM State vCM State vCM #»
Zero [OOO] 0 [PPP] Vdc /2 [NNN] −Vdc /2 V 0 are adopted to synthesize the reference vector. According
P-Type [POO] Vdc /6 [PPO] Vdc /3 [OPO] Vdc /6 to the volt-second balance principle
Small [OPP] Vdc /3 [OOP] Vdc /6 [POP] Vdc /3 #» #» #» #»
V ref Ts = V 13 tL + V 7 tM + V 0 tZ (4)
N-Type [ONN] −Vdc /3 [OON] −Vdc /6 [NON] −Vdc /3
#» #» #» #»
Small [NOO] −Vdc /6 [NNO] −Vdc /3 [ONO] −Vdc /6 where voltage vectors V 13 , V 7 , V 0 , and V ref can be ex-
Medium
[PON] 0 [OPN] 0 [NPO] 0 pressed as ⎧
[NOP] 0 [ONP] 0 [PNO] 0 ⎪ #» 2
⎪
⎪ V 13 = B · Vdc
⎪
√3
[PNN] −Vdc /6 [PPN] Vdc /6 [NPN] −Vdc /6 ⎪
Large ⎪
⎪
[NPP] Vdc /6 [NNP] −Vdc /6 [PNP] Vdc /6 ⎨ #» 3
V7 = B · Vdc · ejπ/6 (5)
⎪ 3
⎪
⎪ #»
E ⎪V 0 = 0
⎪
Sector 4 Sector 3 ⎪
⎪
V 15 (NPN
(NPN) V 8 (OPN
(OPN) V 14 (PPN
(PPN) ⎩ #»
V ref = Vref · ejθ
Sector 5 Sector 2 #» #»
The dwell times of large vector (V 13 ), medium vector (V 7 ),
V 9 (NPO
(NPO) V 7 (PON
(PON) #»
and zero vector (V 0 ) can be calculated as
Sector 6
V reff
Sector 1 ⎧ √ π 
⎪
⎪ t = 3mT sin − θ
V 0 (O
(OOO)
OOO T (PNN) D
V 13 (PNN ⎨ L s
6
V 16 (NPP
(NPP)
V ST
tM = 2mTs sin θ (6)
⎪
⎪
Sector 7 Sector 12
⎩
V 10 (NOP
(NOP)
t Z = T s − tL − tM
V 12 (PNO
(PNO)
#»
where tL , tM , and tZ are dwell times of large vector (V 13 ),
Sector 8 Sector 11
#» #»
medium vector (V 7 ), and zero vector (V 0 ), respectively. Ts is
(NNP) V 11 (ONP
V 17 (NNP (ONP) V 18 (PNP
Sector 9 Sector 10
(PNP)
the switching period, and 0  θ < π/6. m is the modulation
Phase A as shoot-through phase index, which can be defined as
Phase B as shoot-through phase √
3Vref
Phase C as shoot-through phase m= (7)
B · Vdc
Fig. 2. Space vector diagram of the proposed modulation scheme. The maximum magnitude of the reference voltage vector
#»
V ref is equal to the length of medium vector, and can be
found from
III. T HE P ROPOSED S PACE V ECTOR M ODULATION
√
S CHEME 3B · Vdc
Vref,max = (8)
The CMV generated by the inverter is the average value of 3
three-phase output voltages [25], and it can be calculated by Substituting (8) into (7) gives the maximum modulation
vAO + vBO + vCO index
vCM = (3)
3
mmax = 1 (9)
where vAO , vBO , and vCO are three-phase output voltages.
The CMVs generated by voltage vectors of 3LT2 I are listed The maximum RMS value of line-to-line voltage generated
in Table II. When all vectors are adopted to generate the output by the proposed scheme can be calculated by
voltage, the magnitude of CMV is Vdc /2. When zero vectors √  √ 
[PPP] and [NNN] are not adopted, the magnitude of CMV is VL,max = 3 · Vref,max / 2 = 0.707B · Vdc (10)
Vdc /3 [28].
It can be seen that the dc-link voltage utilization of the
This paper proposes a SVM scheme for quasi-Z-source
proposed scheme is the same as conventional SVM method.
3LT2 I, and the space vector diagram is shown in Fig. 2. The
Although small vectors are not adopted to synthesis the
magnitudes of large vectors,
√ medium vectors, and zero vector
reference voltage vector, the dc-link voltage utilization is not
[OOO] are 23 B ·Vdc , 33 B ·Vdc , and 0, respectively, where B is
affected.
the boost factor. Since shoot-through states can be inserted in
The selected switching sequence in Sector 1 is [OOO]-
Phase A, Phase B, or Phase C, there exist three shoot-through
[PON]-[PNN]-[PON]-[OOO], and state transition time for
vectors: [FOO], [OFO], and [OOF]. It is worth mentioning that
Phase A, B, and C can be calculated as
the shoot-through vectors and zero vector have the same output ⎧
⎪ tZ
voltage across the load. The detailed duty cycle calculation, ⎪
⎪ Ta =
⎪
⎪ 2
insertion of shoot-through states, and implementation process ⎨
tZ + t M
will be presented in this section. Sector 1 and Sector 2 in Tb = (11)
⎪
⎪ 2
Fig. 2 will be considered as representative examples for odd ⎪
⎪
⎪
⎩ T c = tZ
and even sectors to explain the proposed scheme.
2

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It can be seen that the maximum positive pulse width exists Ts

in Phase A, while the maximum negative pulse width exists A
in Phase C. The dwell times of these two pulses are identical.
#»
When the reference voltage vector V ref is located in B
#» #»
Sector 2, large vector V 14 , medium vector V 7 , and zero vector
#» C
V 0 are adopted to synthesize the reference vector. According
to the volt-second balance principle tZ' t tM t'
tST M tL tST Z
#» #» #» #» 2 2 2 2
2 PON 2 OOO
V ref Ts = V 14 tL + V 7 tM + V 0 tZ (12) vCM
OOO
OOF
PNN PON
OOF
#» #» #» #» 0
where voltage vectors V 14 , V 7 , V 0 , and V ref can be ex- -Vdc_link/6
pressed as ⎧
⎪ #» 2 (a)
⎪
⎪V 14 = B · Vdc · e
jπ/3
⎪
⎪ 3
⎪
⎪ √ Ts
⎨ #» 3
V7 = B · Vdc · ejπ/6 (13) A
⎪ 3
⎪
⎪ #»
⎪
⎪ V0 =0
⎪
⎪ B
⎩ #»
V ref = Vref · ejθ
C
#» #» tZ' t t'
The dwell times of large vector (V 14 ), medium vector (V 7 ), tM
#» 2
tST M
2
tL
2
tST Z
2
and zero vector (V 0 ) can be obtained as 2 PON 2 OOO
⎧ √  π vCM
OOO
FOO
PPN PON
FOO
⎪
⎪ tL = 3mTs sin θ −
⎪
⎨ 6 Vdc_link/6
π 0
tM = 2mTs sin −θ (14)
⎪
⎪ 3 (b)
⎪
⎩
tZ = T s − tL − tM
Fig. 3. Switching sequences in Sector 1 and Sector 2. (a) Sector 1. (b)
Sector 2.
where π/6  θ < π/3.
The selected switching sequence in Sector 2 is [OOO]-
[PON]-[PPN]-[PON]-[OOO], and state transition time for #»
vector V 0 and the corresponding medium vector in each sector.
Phase A, B, and C can be calculated as The symmetrical characteristic in one switching period can be
⎧
⎪ tZ guaranteed in this way.
⎪
⎪ Ta = #»
⎪
⎪ 2 When the reference voltage vector V ref is located in
⎨
tZ + t M Sector 1, for the proposed scheme, the shoot-through interval
Tb = (15)
⎪
⎪ 2 is inserted in Phase C, and shoot-through vector [OOF] is
⎪
⎪
⎪
⎩ T c = tZ additionally utilized to synthesize the reference vector. A
2 shoot-through interval tST is subtracted from the dwell time
of zero vector, and then the modified dwell time of zero vector
B. Insertion of Shoot-Through States can be expressed

When shoot-through states are inserted in aforementioned tZ = tZ − tST (17)
switching sequences, the modified volt-second balance princi-
The shoot-through interval is equally divided into two parts,
ple can be expressed as
 #» and symmetrically inserted into one switching cycle. State
#» #» #» #»
V ref Ts = V L tL + V M tM + V 0 tZ + V ST tST transition time for Phase A and Phase B remain unchanged,
(16) while state transition time for Phase C should be modified as
Ts = tL + tM + tZ + tST ⎧ 
#» ⎪
⎪ Ta = Ta
where V ST is the shoot-through voltage vector, Ts is the ⎨ 
switching period, and tL , tM , tZ and tST are dwell times Tb = Tb (18)
#» ⎪
⎪
of large vector, medium vector, zero vector (V 0 ), and shoot- ⎩T  = T − tST
#» c c
2
through vector (V ST ), respectively.
Shoot-through state (State F in Table I) can be inserted As shown in Fig. 3(a), the designed switching sequence
in Phase A, Phase B, or Phase C, so three kinds of shoot- in Sector 1 is [OOO]-[OOF]-[PON]-[PNN]-[PON]-[OOF]-
through vectors ([FOO], [OFO], [OOF]) can be determined. [OOO]. During the insertion of shoot-through state [OOF],
It is important to note that the waveform of output voltage output of Phase C is connected to the neutral point, which
should not be affected by the insertion of shoot-through states. is the same as state O. The line-to-line voltage will not be
For the proposed scheme, shoot-through states are inserted affected in this way.
#» #»
within the time interval of zero vector V 0 ([OOO]). The When the reference voltage vector V ref is located in Sec-
total shoot-through interval is divided into two identical parts tor 2, the shoot-through interval is inserted in Phase A. Shoot-
per switching period, and each part is inserted between zero through vector [FOO] is additionally utilized to synthesize the

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TABLE III Control of ac output voltage

vd* Shoot-through
S WITCHING S EQUENCES OF THE P ROPOSED M ODULATION S CHEME  
phase judgment
  PI
va vd ia PI id ud tL Sa1~Sa4
Sector Switching sequence vb abc ib abc dq uD Dwell time tM
uE Sb1~Sb4
vc dq i dq aE Sector calculation tZ
1 [OOO]-[OOF]-[PON]-[PNN]-[PON]-[OOF]-[OOO] vq c iq uq
  
vq* Sector tST Sc1~Sc4
2 [OOO]-[FOO]-[PON]-[PPN]-[PON]-[FOO]-[OOO] 
judgement PWM
3 [OOO]-[OFO]-[OPN]-[PPN]-[OPN]-[OFO]-[OOO] PI PI generation
4 [OOO]-[OOF]-[OPN]-[NPN]-[OPN]-[OOF]-[OOO] Vdc _ ref  dST Shoot-through
5 [OOO]-[FOO]-[NPO]-[NPN]-[NPO]-[FOO]-[OOO] Vdc _ link  PI
interval calculation
vC2
vC3 
6 [OOO]-[OFO]-[NPO]-[NPP]-[NPO]-[OFO]-[OOO] Eq. (1) and (2)

Vdc
7 [OOO]-[OOF]-[NOP]-[NPP]-[NOP]-[OOF]-[OOO] Control of dc-link voltage
8 [OOO]-[FOO]-[NOP]-[NNP]-[NOP]-[FOO]-[OOO]
9 [OOO]-[OFO]-[ONP]-[NNP]-[ONP]-[OFO]-[OOO] Fig. 4. Control block diagram of the quasi-Z-source 3LT2 I.
10 [OOO]-[OOF]-[ONP]-[PNP]-[ONP]-[OOF]-[OOO]
11 [OOO]-[FOO]-[PNO]-[PNP]-[PNO]-[FOO]-[OOO]
12 [OOO]-[OFO]-[PNO]-[PNN]-[PNO]-[OFO]-[OOO]
and reference value going through a PI controller produces the
shoot-through duty cycle (dST ), as expressed in Eq. (20).

reference vector. State transition time for Phase B and Phase

C remain unchanged, while state transition time for Phase A ki,ST
dST = kp,ST + (Vdc ref − Vdc link ) (20)
should be modified as s
⎧  tST
⎪
⎪ Ta = Ta − where dST is the shoot-through duty cycle. Vdc link and
⎨ 2

(19) Vdc ref are the magnitude of dc-link voltage and its reference
⎪ T = T
⎪
⎩ 
b b value, respectively. kp,ST and ki,ST are the proportional and
Tc = Tc integral coefficient of the PI controller for dc-link voltage
control.
As shown in Fig. 3(b), the designed switching sequence
For the ac-side control, three-phase ac output voltages and
in Sector 2 is [OOO]-[FOO]-[PON]-[PPN]-[PON]-[FOO]-
currents are sampled and transformed to dc components via
[OOO]. During the insertion of shoot-through state [FOO],
abc/dq transformation. The double loop control scheme is de-
output of Phase A is connected to the neutral point, which
signed to make the ac output voltage track the reference value
is the same as state O. The line-to-line voltage will not be
accurately, which is developed in the synchronous reference
affected in this way.
frame. The functions of these two control loops are different.
Similarly, switching sequences of the proposed scheme in The outer loop control is focused on the ac output voltage
other sectors can also be obtained in this way. Shoot-through control objective, while the inner loop is used to improve
phase can be selected from Fig. 2, and switching sequences the dynamic performance. The PI controllers are employed to
are summarized in Table III. It can be seen that each phase is eliminate the steady-state error. The guidance for controller
selected as shoot-through phase in one-third of all sectors, so parameters design is given in [31], and this methodology
relatively balanced losses of power devices can be guaranteed. is adopted. The outputs of controllers are used as the input
variables of the proposed modulation scheme.
C. Implementation of the Control Scheme In the proposed modulation scheme, the sector number can
be determined by Fig. 2, and shoot-through phase can be
The overall control block diagram is shown in Fig. 4. The
judged. In sectors 1, 4, 7, and 10, Phase C is selected as the
quasi-Z-source 3LT2 I system operates in the voltage control
shoot-through phase, while in sectors 2, 5, 8, and 11, Phase A
mode, so as to supply a constant ac output voltage to the load.
is selected as the shoot-through phase. In other sectors, shoot-
The dc-side and ac-side of the quasi-Z-source 3LT2 I system
through states are inserted in Phase B. According to the
are controlled separately [29], [30]. The structure of the overall
volt-second balance principle, dwell times of selected voltage
control system is divided into two parts, control of dc-link
vectors are calculated. After these calculations, the shoot-
voltage and control of ac output voltage. #»
through interval is inserted within zero vector V 0 , and three-
The control of dc-link voltage is realized by controlling the
phase turn-on time can be accordingly modified. Finally,
shoot-through duty cycle. It should be noted that the dc-link
switching sequences should be decided, and the generated
voltage of quasi-Z-source 3LT2 I is pulse voltage waveform
PWM signals are used to control the power switches in quasi-
due to the adoption of shoot-through states, which cannot be
Z-source 3LT2 I.
directly utilized as feedback variable. Therefore, an indirect
In the proposed scheme, the shoot-through states are equally
control scheme is adopted to control the dc-link voltage. The
distributed in one switching cycle to guarantee the lowest rip-
voltages across capacitors C2 and C3 are sampled, and the ac-
ple in the dc-link voltage. As described in [17], the modulation
tual magnitude of dc-link voltage (Vdc link ) can be calculated
index m and the shoot-through duty cycle dST should satisfy
by using Eq. (1) and Eq. (2). The calculated magnitude of dc-
link voltage is compared with the reference magnitude of dc-
link voltage (Vdc ref ). Then the error between the actual value m + dST  1 (21)

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TABLE IV

Voltage (V)

Voltage (V)
400 400

DC-link

DC-link
PARAMETERS FOR S IMULATIONS AND E XPERIMENTS 200 200
0 0
Parameters/components Values 400 400

Voltage (V) Voltage (V)

Voltage (V) Voltage (V)

Common-mode Line-to-line

Common-mode Line-to-line
200 200
DC input voltage (Vdc ) 160 ∼ 400 V 0
-200
0
-200
-400 -400
Inductors (L1 , L2 , L3 , L4 ) 1.5 mH
100 100
Capacitors (C1 , C4 ) 2350 μF
0 0
Capacitors (C2 , C3 ) 1410 μF -100 -100
LC filter Lf = 2 mH, Cf = 4.7 μF 0.55 0.56 0.57 0.58
Time (s)
0.59 0.6 0.55 0.56 0.57 0.58
Time (s)
0.59 0.6

Load resistance (Rload ) 12 Ω

(a) (b)
Load inductance (Lload ) 5 mH
Switching frequency (fsw ) 12.5 kHz 250

Voltage (V)
400 vC2 vC3

DC-link
Fundamental output frequency (f ) 50 Hz 200 200
IGBTs for high-side and low-side switches IKW40T120

Capacitor Voltage (V)

0
IGBTs for bidirectional switches IKW50N60T 400 150

Voltage (V) Voltage (V)

Common-mode Line-to-line
200
0
Diodes in the quasi-Z-source network DSEI 30-06A -200 100
-400
Nominal output phase voltage 130 V (RMS)
100 50
0 vC1 vC4
-100 0
0.55 0.56 0.57 0.58 0.59 0.6 0.55 0.56 0.57 0.58 0.59 0.6
Considering the simulation and experimental conditions in Time (s) Time (s)

this paper, the maximum shoot-through duty cycle is set to (c) (d)
0.3, and a modulation index higher than 0.7 can be used to
Fig. 5. Simulation results of dc-link voltage, line-to-line voltage,
guarantee the good quality of output waveforms. common-mode voltage, and capacitor voltages in non-boost case (Vdc =
400 V). (a) Method-1. (b) Method-2. (c) Method-3. (d) Capacitor voltages
of Method-3.
IV. S IMULATION R ESULTS
Simulations have been performed using Matlab/Simulink. 200 va vb vc 200 va vb vc
Voltages (V)

Voltages (V)
As is described in [17], parameters of passive devices can
Phase

Phase
0 0
be determined by considering constant currents through the
-200 -200
inductors, and this methodology is adopted here. The cutoff 20 ia ib ic 20 ia ib ic
Currents (A)

Currents (A)
Phase

Phase
frequency of LC filter is set about 1.64 kHz to mitigate 0 0

ripples of switching frequency. The power devices are se- -20

0.55 0.56 0.57 0.58 0.59 0.6
-20
0.55 0.56 0.57 0.58 0.59 0.6
lected according to the maximum voltage stress. Parameters Time (s) Time (s)

for simulations and experiments are listed in Table IV, and (a) (b)
three methods are compared. Method-1 is conventional SVM 200 va vb vc
Voltages (V)

scheme. Method-2 is conventional phase-shifted sinusoidal

Phase

0
PWM scheme. Method-3 is the proposed scheme. -200
First, the dc input voltage of 400 V is considered. In this 20 ia ib ic
Currents (A)
Phase

case, the dc input voltage is high enough to produce the desired 0

ac output voltage, and the shoot-through state is not utilized. -20

0.55 0.56 0.57 0.58 0.59 0.6
Time (s)
Simulation results of dc-link voltage, line-to-line voltage, and
(c)
CMV are shown in Fig. 5. The line-to-line voltage of Method-
1 changes from Vdc /2 to Vdc at the top part. Since small Fig. 6. Simulation results of phase voltages and phase current in non-
voltage vectors are used to synthesis the reference vector, the boost case (Vdc = 400 V). (a) Method-1. (b) Method-2. (c) Method-3.
magnitude of CMV is equal to Vdc /3. As shown in Fig. 5(b),
when Method-2 is used, the line-to-line voltage changes from
0 to Vdc at the top part. The magnitude of CMV is equal to 3.03%, and 3.12%, respectively. When Method-3 is adopted,
Vdc /6. The variation of CMV is from −Vdc /6 to Vdc /6. The THD of phase voltage is slightly higher, but the magnitude
line-to-line voltage of Method-3 also changes from 0 to Vdc and slew rate of CMV can be significantly reduced.
at the top part. The CMV changes from 0 to Vdc /6 in positive Second, the dc input voltage of 280 V is considered, and
half period, and from −Vdc /6 to 0 in negative half period, the shoot-through state is utilized. In order to maintain the
and the slew rate of CMV can be greatly reduced. Capacitor magnitude of dc-link voltage of 400 V, the shoot-through duty
voltages of Method-3 are shown in Fig. 5(d). In non-boost cycle should be increased to 0.15 from the theoretical analysis.
case, voltages across capacitor C1 and C4 are almost zero, The corresponding simulation results of three methods are
while voltages across capacitor C2 and C3 are about Vdc /2. shown in Fig. 7. It should be noted that upper shoot-through
Fig. 6 shows phase voltages and phase currents in non-boost and lower shoot-through operational modes proposed in [21]
case. It can be seen that the ripples of switching frequency are are adopted in Method-1, so the dc-link voltage changes
mitigated by the LC filter. Three-phase voltages and currents between 200 V and 400 V. When Method-2 or Method-3 is
with high quality can be obtained. THD values of phase adopted, dc-link voltage changes between 0 and 400 V. The
voltages for Method-1, Method-2, and Method-3 are 2.37%, CMV magnitude of Method-3 is limited within Vdc link /6, and

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2798611, IEEE
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Voltage (V) 200 va vb vc 200 va vb vc

Voltage (V)

Voltages (V)
Voltages (V)
400 400
DC-link

DC-link

Phase
Phase
200 200 0 0
0 0
-200 -200
400 400
Voltage (V) Voltage (V)

Voltage (V) Voltage (V)

Common-mode Line-to-line

Common-mode Line-to-line
20 ia ib ic 20 ia ib ic

Currents (A)
Currents (A)
200 200
0 0

Phase
Phase
-200 -200 0 0
-400 -400

100 100 -20 -20

0.55 0.56 0.57 0.58 0.59 0.6 0.55 0.56 0.57 0.58 0.59 0.6
0 0 Time (s) Time (s)

-100 -100
(a) (b)
0.55 0.56 0.57 0.58 0.59 0.6 0.55 0.56 0.57 0.58 0.59 0.6
Time (s) Time (s)
200 va vb vc

Voltages (V)
(a) (b)

Phase
0
250
-200
Voltage (V)

400
DC-link

20 ia ib ic

Currents (A)
200 200 vC2 vC3

Phase
0
Capacitor Voltage (V)

0
400 150
Voltage (V) Voltage (V)
Common-mode Line-to-line

-20
200 0.55 0.56 0.57 0.58 0.59 0.6
0 Time (s)
-200 100
-400
(c)
100 vC1 vC4
50
0
Fig. 8. Simulation results of phase voltages and phase current in boost
-100 0
0.55 0.56 0.57 0.58 0.59 0.6 0.55 0.56 0.57 0.58 0.59 0.6
case (Vdc = 280 V). (a) Method-1. (b) Method-2. (c) Method-3.
Time (s) Time (s)

(c) (d) 100

Method-1
90

CMV RMS value (V)

Method-2
Fig. 7. Simulation results of dc-link voltage, line-to-line voltage, 80 Method-3
common-mode voltage, and capacitor voltages in boost case (Vdc = 70
280 V). (a) Method-1. (b) Method-2. (c) Method-3. (d) Capacitor voltages
60
of Method-3.
50
40
30
the slew rate of CMV is also reduced. It is clear that voltage 20
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
boosting and CMV reduction are simultaneously realized. Modulation index
When Method-3 is adopted, simulated waveforms of capacitor
Fig. 9. CMV RMS values of different modulation indices.
voltages are shown in Fig. 7(d). In boost case, voltages across
capacitor C1 and C4 are not zero. The sum of the capacitor
4.0
voltages is almost equal to the magnitude of dc-link voltage. Method1
THD of phase voltage (%)

Method2
The neutral-point voltage has no drift and fluctuates little in 3.5 Method3
normal operating condition.
Fig. 8 shows phase voltages and phase currents in boost 3.0

case. The currents are not distorted even when shoot-through

2.5
states are inserted due to the existence of quasi-Z-source
network. The RMS value of phase voltage is equal to its 2.0
reference value. THD values of phase voltages for Method- 80 90 100 110 120 130
RMS value of output phase voltage (V)
1, Method-2, and Method-3 are 2.61%, 3.08%, and 3.29%,
respectively. Due to the adoption of three-level topology, the Fig. 10. THD comparisons of different output phase voltages.
THD values can satisfy the IEEE standards [32].
When the dc input voltage and shoot-through duty cycle
and the shoot-through duty cycle. When conventional SVM
are set as 360 V and 0.05, CMV RMS values of different
scheme is adopted, the THD is the minimum. Since no small
modulation indices are shown in Fig. 9. For Method-1, when
vectors are utilized to synthesis the reference voltage vector,
the modulation index is around 0.5, the dwell times of small
the THD of the proposed modulation scheme is slightly higher,
voltage vectors with high CMV are increased, and the CMV
but the advantages in terms of the THD reduction from a
RMS value is the highest. For Method-2 and Method-3, as the
three-level inverter is noticeable in comparison with a two-
modulation index increases, the CMV RMS values increase.
level inverter.
The CMV RMS value of Method-3 is lower than that of
Method-2.
In order to clearly show the performance of the proposed V. E XPERIMENTAL R ESULTS
scheme, full characteristics of THD for output voltage are An experimental prototype (Fig. 11) is built to further vali-
investigated, and the results are shown in Fig. 10. For three date the proposed scheme. This prototype consists of a control
PWM methods, the THD of phase voltage decreases with the board based on DSP28335, main circuit, gate drivers, LC filter,
increase of output phase voltage. However, a large modulation and a three-phase resistive-inductive (RL) load. Parameters
index should be utilized to increase the output voltage, which for experiments are the same as those for simulations, as
decreases the available shoot-through duty cycle. Consequent- shown in Table IV. Three methods are compared. Method-1 is
ly, a tradeoff should be made between the modulation index conventional SVM scheme. Method-2 is conventional phase-

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Three-level Load va (100V/div) vb (100V/div) va (100V/div) vb (100V/div)

T-type Inverter Resistor
Load
Inductor
SMPS
Quasi-Z-Source ia (10A/div) ib (10A/div) ia (10A/div) ib (10A/div)
Network Main Controller

Fig. 11. Photograph of the experimental prototype. Time (5ms/div) Time (5ms/div)

(a) (b)

vdc_link (250V/div) vdc_link (250V/div) va (100V/div) vb (100V/div)

vAB (250V/div) vAB (250V/div)

ia (10A/div) ib (10A/div)

vCM (150V/div) vCM (150V/div)

Time (5ms/div) Time (5ms/div) Time (5ms/div)

(a) (b) (c)
Capacitor voltages (50V/div)
vdc_link (250V/div) vC2 vC3 Fig. 13. Experimental results of phase voltages and phase currents in
vAB (250V/div) non-boost case ( Vdc = 400 V). (a) Method-1. (b) Method-2. (c) Method-
3.

vC1 vC4
Vdc (250V/div)
vCM (150V/div)

Time (5ms/div) Time (5ms/div)

(c) (d)
iIN (10A/div)
Fig. 12. Experimental results of dc-link voltage, line-to-line voltage,
common-mode voltage, and capacitor voltages in non-boost case (Vdc = Time (5ms/div)
400 V). (a) Method-1. (b) Method-2. (c) Method-3. (d) Capacitor voltages
of Method-3. Fig. 14. Experimental results of dc input voltage and input current in
boost case (Vdc = 280 V).

shifted sinusoidal PWM scheme. Method-3 is the proposed

scheme. Output waveforms in boost case are shown in Fig. 15. It
First, the experiment is conducted to validate the non-boost can be seen that the dc-link voltage is boosted. The difference
case. The dc input voltage is 400 V, and it is high enough to between experimental and expected values lies in the fact that
produce the desired ac output voltage. Output waveforms are saturation voltage of power switches and forward voltage of
shown in Fig. 12. When Method-3 is used, the magnitude of diodes are not taken into consideration in theoretical analysis.
CMV is limited to about 64.2 V, which is identical with the When Method-3 is used, the peak part of the line-to-line
theoretical value of Vdc /6. In addition, the CMV slew rate is voltage has values of Vdc link and 0, and the CMV can be
reduced. Experimental waveforms of capacitor voltages using restricted within one-sixth of dc-link voltage. The zoom-in
Method-3 are shown in Fig. 12(d). In this case, voltages across experimental waveforms of CMV in boost case are shown
capacitor C1 and C4 are almost zero, and voltage balance in Fig. 16. When Method-1 is used, the CMV magnitude is
between capacitor C2 and C3 can be realized in steady state. equal to one-third of dc-link voltage. The CMV magnitude
Fig. 13 shows experimental waveforms of phase voltages of Method-3 is restricted within one-sixth of dc-link voltage,
and phase currents in non-boost case. It can be seen that the which is only half of Method-1. When Method-2 is used, the
expected phase voltages can be obtained, and the ripples in waveform of CMV changes from −Vdc link /6 to Vdc link /6.
phase voltages and phase currents of switching frequency are The CMV of Method-3 changes from 0 to Vdc link /6 in
mitigated by the LC filter. THD values of phase voltages for positive half period, and from −Vdc link /6 to 0 in negative
Method-1, Method-2, and Method-3 are 2.86%, 3.52%, and half period. The change from −Vdc link /6 to Vdc link /6 in
3.74%, respectively. Even though the THD of the proposed CMV waveform is avoided by using the proposed scheme,
scheme is slightly higher than that of conventional SVM and the slew rate of CMV can be reduced. Capacitor voltages
method, the benefits in terms of the THD reduction from of Method-3 in boost case are shown in Fig. 15(d). Compared
a three-level inverter is noticeable in comparison with a to the waveforms in non-boost case, the voltage ripples in
two-level inverter. The THD value complies with the IEEE capacitors become larger. The experimental results accord well
standards [32]. with the simulation results, and the feasibility of the proposed
Second, the dc input voltage is set to 280 V to validate the scheme is verified.
operation of boost case. Fig. 14 shows waveforms of dc input Experimental waveforms of filtered phase voltages and
voltage and input current. Continuous dc input current can be phase currents in boost case are shown in Fig. 17. High-quality
obtained, which is suitable for applications like PV generation sinusoidal currents are also observed. THD values of phase
system, fuel cells, etc. voltages for Method-1, Method-2, and Method-3 are 2.91%,

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vdc_link (250V/div) vdc_link (250V/div) vdc_link (250V/div) Currents (10A/div)

vAB (250V/div) ia ib ic
vAB (250V/div) vAB (250V/div)

vCM (150V/div) vCM (150V/div) vCM (150V/div)

Time (5ms/div) Time (5ms/div) Time (5ms/div) Time (5ms/div)

(a) (b) (a) (b)

vdc_link (250V/div) Capacitor voltages (50V/div) Fig. 18. Experimental results in high boost case (Vdc = 200 V). (a) DC-
vC2 vC3 link voltage, line-to-line voltage, and CMV. (b) Three-phase currents.
vAB (250V/div)

vC1 vC4 91
90
vCM (150V/div)

Efficiency (%)
89
Time (5ms/div) Time (5ms/div)
88
(c) (d) 87
86
Fig. 15. Experimental results of dc-link voltage, line-to-line voltage, 85
common-mode voltage, and capacitor voltages in boost case (Vdc =
280 V). (a) Method-1. (b) Method-2. (c) Method-3. (d) Capacitor voltages 200 250 300 350 400
Input voltage (V)
of Method-3.
Fig. 19. Measured efficiency of the quasi-Z-source 3LT2 I prototype.
vCM (50V/div) vCM (50V/div) vCM (50V/div)
Vdc_link /6 Vdc_link /6
Vdc_link /3 0 able to boost the output line-to-line voltage to a value higher
than the available dc input voltage with sinusoidal three-phase
-Vdc_link /3 output current.
-Vdc_link /6 -Vdc_link /6
Time (500μs/div) Time (500μs/div) Time (500μs/div) The efficiency of the quasi-Z-source 3LT2 I has been mea-
(a) (b) (c)
sured by the WT3000 power analyzer. The measurements are
conducted on the experimental prototype with a fixed RL-load.
Fig. 16. The zoom-in experimental waveforms of CMV in boost case The magnitude of line-to-line voltage is equal to 400 V, while
(Vdc = 280 V). (a) Method-1. (b) Method-2. (c) Method-3.
the dc input voltage is changed. The efficiency curve is shown
in Fig. 19. It can be seen that the efficiency increases with
va (100V/div) vb (100V/div) va (100V/div) vb (100V/div) higher input dc voltage, up to 90.53%. When the dc input
voltage is low, a higher shoot-through duty cycle is required
to maintain the constant output voltage, which decreases the
ia (10A/div) ib (10A/div) ia (10A/div) ib (10A/div) efficiency.

Time (5ms/div) Time (5ms/div)

VI. C ONCLUSION
(a) (b)
This paper proposes a SVM scheme for quasi-Z-source
va (100V/div) vb (100V/div)
3LT2 I, which adopts large, medium, zero, and shoot-through
voltage vectors to synthesis the reference vector. By properly
ia (10A/div) ib (10A/div) selecting shoot-through phase according to sector number,
shoot-through states are inserted within zero vector to realize
voltage boosting. Dwell times of voltage vectors are calculated
Time (5ms/div) through the modified volt-second balance principle. Since no
(c) small vectors are utilized to synthesis the reference voltage
vector, both the magnitude and slew rate of CMV can be
Fig. 17. Experimental results of phase voltages and phase currents in
boost case ( Vdc = 280 V). (a) Method-1. (b) Method-2. (c) Method-3. reduced, and the neutral-point voltage has no drift and fluc-
tuates little in normal operating condition. Doing so, voltage
boosting and CMV reduction can be simultaneously realized.
3.89%, and 4.13%, respectively. Although the THD of the At the same time, the modulation index is not affected, and
proposed scheme is slightly higher, the IEEE standards can high dc voltage utilization can be maintained. A control system
be satisfied [32]. is developed for the quasi-Z-source 3LT2 I to supply a constant
Next, the dc input voltage of 200 V is used to test the output voltage for the load. Multiple cases are considered
high boosting performance with the proposed scheme, and to simulate the operation of renewable energy system, and
experimental results are shown in Fig. 18. The results show experimental results are in good agreement with theoretical
that the quasi-Z-source 3LT2 I, with the proposed scheme, is analyses and simulations.

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[12] O. Husev, C. Roncero-Clemente, E. Romero-Cadaval, D. Vinnikov,
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Changwei Qin was born in Shandong, China, in
[13] Y. Liu, B. Ge, H. Abu-Rub, and F. Z. Peng, “Overview of space vector
1990. He received the B.S. degree in automa-
modulations for three-phase Z-source/quasi-Z-source inverters,” IEEE
tion from Shandong University, Jinan, China, in
Trans. Power Electron., vol. 29, no. 4, pp. 2098-2108, Apr. 2014.
2012, and the M.S. degree in control science
[14] O. Husev, S. Stepenko, C. Roncero-Clemente, E. Romero-Cadaval, and and engineering from Anhui University, Hefei,
D. Vinnikov, “Single-phase three-level quasi-Z-Source inverter with a China, in 2015. He is currently working toward
new boost modulation technique,” in Proc. IEEE 38th Annu. Conf. Ind. the Ph.D. degree in electrical engineering in
Electron. Soc., Oct. 2012, pp. 5856-5861. the School of Control Science and Engineering,
[15] Y. Liu, B. Ge, H. Abu-Rub, and H. Sun, “Hybrid pulsewidth modulated Shandong University, Jinan, China. His current
single-phase quasi-Z-source grid-tie photovoltaic power system,” IEEE research interests include renewable power gen-
Trans. Ind. Informat., vol. 12, no. 2, pp. 621-632, Apr. 2016. eration and control of multi-level inverters.
[16] Y. Zhou, H. Li, and H. Li, “A single-phase pv quasi-z-source invert-
er with reduced capacitance using modified modulation and double-
frequency ripple suppression control,” IEEE Trans. Power Electron.,
vol. 31, no. 3, pp. 2166-2173, Mar. 2016.
[17] O. Husev, C. Roncero-Clemente, E. Romero-Cadaval, D. Vinnikov, and
S. Stepenko, “Single phase three-level neutral-point-clamped quasi-Z- Chenghui Zhang (M’14-SM’18) was born in
source inverter,” IET Power Electron., vol. 8, no. 1, pp. 1-10, Jan. 2015. Shandong, China, in 1963. He received the B.S.
[18] V. Fernao Pires, A. Cordeiro, D. Foito, and J. F. Martins, “Quasi-Z- and M.S. degrees in automation engineering
Source inverter with a T-type converter in normal and failure mode,” from Shandong University of Technology, Chi-
IEEE Trans. Power Electron., vol. 31, no. 11, pp. 7462-7470, Nov. 2016. na, in 1985 and 1988, respectively, and the
[19] M. Sahoo and S. Keerthipati. “A three level LC-switching based voltage Ph.D. degree in control theory and operational
boost NPC inverter,” IEEE Trans. Ind. Electron., vol. 64, no. 4, pp. 2876- research from Shandong University, China, in
2883, Apr. 2017. 2001. In 1988, he joined Shandong University,
[20] F. B. Effah, P. Wheeler, J. Clare, and A. Watson, “Space-vector- where he is currently a Full Professor with the
modulated three-level inverters with a single Z-source network,” IEEE School of Control Science and Engineering, and
Trans. Power Electron., vol. 28, no. 6, pp. 2262-2271, Jun. 2013. the director of Research Center of Power Elec-
[21] X. Xing, C. Zhang, A. Chen, J. He, W. Wang, and C. Du, “Space- tronics Energy-Saving Technology & Equipment of the Chinese Educa-
vector-modulated method for boosting and neutral voltage balancing in tion Ministry. He was selected as a Changjiang Scholar of the Education
Z-source three-level T-type inverter,” IEEE Trans. Ind. Appl., vol. 52, Ministry in 2009, and a Taishan Scholar of Shandong Province in 2009,
no. 2, pp. 1621-1631, Mar./Apr. 2016. respectively. His current research interests include optimal control of
[22] J. Shang and Y. W. Li, “A space-vector modulation method for common- engineering, power electronics and motor drives, and energy-saving
mode voltage reduction in current-source converters,” IEEE Trans. techniques.
Power Electron., vol. 29, no. 1, pp. 374-385, Jan. 2014.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2798611, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Alian Chen (M’14) was born in Shandong, Chi- Xiangyang Xing (S’16) was born in Rizhao, Chi-
na, in 1976. She received the B.S. and M.S. na, in 1985. He received the B.S. degree in au-
degrees in electrical engineering from Shan- tomation and M.S. degree in control theory and
dong University, Shandong, China, in 1998, and application degree from Qufu Normal University,
2000, respectively, and the Ph.D. degree in China, in 2009 and 2012, and the Ph.D. degree
electrical engineering from Zhejiang University, in electrical engineering from Shandong Univer-
Hangzhou, China, in 2005. In 2005, she joined sity, Shandong, China, in 2016. From 2017, he
the School of Control Science and Engineer- is a Post-doctoral Research Fellow with Shan-
ing, Shandong University, Shandong, China. In dong University, Shandong, China. His current
2013, she worked as a Visiting Scholar at the research interests include multilevel converters,
Center for Power Electronics Systems, Virginia power conversion, renewable power generation.
Tech, Blacksburg, VA, USA. She has been involved in researching on
multilevel converters, power electronics and industrial applications.

Guangxian Zhang was born in China in 1965.

He received the B.S., M.S. and Ph.D. degrees in
electrical engineering from Shandong University,
Jinan, China, in 1987, 1990, and 2004, respec-
tively. Since 1990, he has been a research staff
in Shandong University, where he is currently a
Full Professor with the School of Control Science
and Engineering. His current research interests
include power electronics technology and spe-
cial power.

0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See [Link] for more information.