IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO.
2, FEBRUARY 2016 691
Enhanced-Boost Z-Source Inverters With
Switched Z-Impedance
Hossein Fathi and Hossein Madadi, Member, IEEE
Abstract—This paper proposes a new topology for an
enhanced-boost Z-source inverter (ZSI) with combined two
Z-impedance networks. By two Z-impedance networks and
low shoot-through duty cycle, the proposed inverter pro-
duces high output voltage gain. In traditional ZSIs for
high boosting voltage, a low modulation index is required;
hence, under these conditions, the output voltage will have
low quality with high total harmonic distortion. Compared
with the conventional high-boost ZSI topologies, the pro-
posed inverter uses shorter shoot-through duration and a
larger modulation index to improve the output waveform
quality. Comparison between the proposed topology and
previously proposed schemes, in terms of inductor num-
bers, voltage and current stresses on elements, sizes of
inductors and capacitors, efficiency, and switching device
product (SDP) factors of diodes, is made, and the results
verify the priority of the proposed topology. The operating
principle of the proposed topology is analyzed in detail.
Both simulation and experimental results verify the high
performance of the proposed inverter.
Index Terms—Buck–boost, high boost, impedance net-
work, total harmonic distortion (THD), Z-source inverter
(ZSI).
I. I NTRODUCTION
T RADITIONAL voltage-source inverter (VSI) and current-
source inverter (CSI) are known to have only buck or
boost conversion ability, respectively. For applications where
both voltage buck and boost operating capabilities are needed,
before the VSI, an additional dc–dc converter is required, that
this two-stage configuration, increases the cost and reduces
the efficiency of the system. In addition, the shoot-through
problem in VSIs and the open-circuit problem in CSIs are the
main concern in the system’s reliability. The structure proposed
for overcoming the aforementioned problems was a Z-source
inverter (ZSI) [1], which, unlike the VSIs and CSIs, with single-
stage power conversion, has buck–boost voltage abilities. Thus,
buck–boost capability is achieved with a single-stage power
conversion. This unique feature also increases the immunity
of the inverters to electromagnetic noise, which may cause
uncontrolled shoot-through zero (or open circuit) that destroys
Manuscript received November 22, 2014; revised March 18, 2015 and
June 9, 2015; accepted July 25, 2015. Date of publication September 9,
2015; date of current version January 8, 2016.
The authors are with the Renewable Energy Research Center,
Sahand University of Technology, Tabriz, Iran (e-mail: hmadadi64@
yahoo.ca).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2015.2477346
0278-0046 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
the conventional VSIs and CSIs, respectively. Meanwhile, in a
ZSI, both switches in a leg can be turned on simultaneously
to eliminate deadtime and to improve the quality of the output
waveform. Because of these flexibilities, ZSIs have already
been investigated for a number of applications, such as motor
drives [2], electric vehicles [3], distributed generation [4], pho-
tovoltaic generation [5], [6], uninterruptible power supply [7],
and fuel-cell converters [8]. Moreover, others have focused on
their modeling and control [9], [10], operating modes [11], and
new Z-network topologies [12]–[25].
Despite these advantages, the ZSI has some obvious draw-
backs, such as discrete input current, which leads to low utiliza-
tion and lifetime damage of the dc source, large voltage stress
across the switches and capacitors, huge inrush current, and a
lower modulation index for high-gain output voltage that leads
to poor output voltage waveform quality. With the introduction
of quasi-ZSIs (QZSIs) [12], the classical ZSI’s shortcomings
were solved. This topology improves the input current profiles
and reduces the passive component ratings.
In recent years, new topologies have been introduced for
high-boost ZSIs. To achieve high dc-link voltage with a low
shoot-through duty cycle, the new topologies have added induc-
tors, capacitors, and diodes to the Z-impedance network. For
high-boost ZSIs, new topologies include continuous-current
diode/capacitor-assisted extended-boost QZSIs [13], switched-
inductor (SL) Z-source/QZSIs [14], [15], generalized multi-
cell SL ZSIs [16], tapped-inductor (TL) ZSIs [17], trans-ZSIs
[18]–[23], the alternate-cascading technique presented in [24],
and the alternate-cascaded SL and TL ZSIs in [25].
The concept of extending the QZSI gain without increasing
the number of switches was proposed by Gajanayake et al. in
[13]. These new converter topologies are commonly referred to
as the extended-boost QZSI or the cascaded QZSI and could be
generally classified as capacitor- and diode-assisted topologies.
These new topologies introduce some excellent features, such
as low or no inrush current during startup, low common-mode
noise, and continuous input current. In [14] and [15], for high
boosting capability, a switched inductor (SL) voltage-type ZSI
was proposed, where the inductors, i.e., L1 , L2 , were replaced
by two SL cells assembled using inductors and diodes. The
switched-capacitor cell and the inductor cell have also been
applied to the current-type ZSI, as demonstrated in [16].
For even greater voltage boosting, the trend subsequently
drifted toward using two-winding coupled inductors, which are
named TL ZSIs [17], and or transformers, which are named
trans-ZSIs [18]–[23]. Qian et al. in [18] and Strzelecki et al. in
[19] introduced coupled transformers in place of the inductors
692 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 2, FEBRUARY 2016

found in the original Z-source network. The inverter voltage

gain can then be raised by increasing the transformer turns ratio,
but at the expense of chopping input current even if the quasi
or embedded variants are used. To smooth the input current, a
number of asymmetrical transformer-based embedded Z-source
(EZ-source) inverters are proposed [20], whose gain is higher
and input current is smoother.
To reduce the voltage stress on switches and passive compo-
nents in greater high boosting, cascaded multicell trans-ZSIs
are proposed in [21], where multiple small transformers are
used to replace a high-power-rating transformer. In comparison
with the noncascaded inverter, the cascaded multicell trans- Fig. 1. SL-ZSI.
ZSI has higher efficiency with lower component stresses. The
common feature of cascaded topologies is the distribution of
the stresses on passive components, such as the inductor, the
transformer, the capacitor, and the diode. Combined switched-
inductor and transformer-cell ZSIs have been presented in [22].
By changing the transformer turns ratio and the number of
SL cells, the proposed inverter can produce very high output
voltage gains. With the same number of transformers and turns
ratios, the proposed inverter can produce the same output volt-
age gains as other high-boost ZSIs by using a higher modulation
index.
The significant feature of the trans-ZSI is the use of trans-
former turns ratio for even higher voltage boosting. How- Fig. 2. Proposed ZSI with switched Z-impedance.
ever, during switching, any lack in magnetic coupling of the
transformers will definitely cause huge transient over volt-
ages, which would damage the active switches. Higher voltage where T0 is the interval of the shoot-through state during the
boosting is the flow of high currents and appearance of high switching period T , and D is the duty cycle of shoot-through.
voltages across some components. Such stresses, if not lowered, An SL voltage-type ZSI is shown in Fig. 1, where the inductive
will lead to shorter life span and unexpected damages, which blocks were replaced by two SL cells assembled using inductors
are avoided by proposing the alternate-cascading technique and diodes. Since the dc-link voltage appearing across the
presented in [24] and the alternate-cascaded SL and TL ZSIs external ac loads during a non-shoot-through state is the sum
in [25]. of voltages across the two SL cells and input source, a series
This paper presents a family of high-boost ZSIs based on connection of L1 and L3 will boost it further. The boost factor
switched Z-impedance. The proposed ZSI can produce very B for the SL-based ZSI can be expressed as follows:
high output voltage gains. With the same duty ratio, the pro- 1+D
posed topology produces a higher boost factor than diode- B= . (2)
1 − 3D
assisted QZSIs, alternate-cascaded ZSIs, and SL-ZSIs. In other
words, the new topology requires a lower duty ratio for the same Higher gain can be achieved by using a new form of SL cells.
boosting voltage. The proposed inverter has lower voltage stress As shown in Fig. 2, the proposed ZSI consists of four inductors
across active switching devices compared with diode-assisted (L1 , L2 , L3 , and L4 ), four capacitors (C1 , C2 , C3 , and C4 ),
QZSIs, alternate-cascaded ZSIs, SL-ZSIs, and conventional and four diodes (D1 , D2 , D3 , and D4 ). The combination of
ZSIs. Although the number of inductors in the proposed scheme L1 , C1 , and L2 , C2 is the first Z-impedance network, and the
is higher than those in the alternate-cascaded ZSI (N = 2), the combination of L3 , C3 , and L4 , C4 is the second Z-impedance
inductor size is smaller in the proposed method and, hence, network.
cheaper than those in the alternate-cascaded ZSI (N = 2, 3).
Meanwhile, in the proposed method, the diodes have less SDP
A. Operation Principles
factor compared with the alternate-cascaded ZSI (N = 3), and
hence, this leads to a less expensive inverter. The operation principles of the proposed inverter are sim-
ilar to those of the classical ZSI. Therefore, the state of the
Z-impedance network in two operating states will be discussed.
II. P ROPOSED ZSI W ITH S WITCHED Z-I MPEDANCE Shoot-Through State: In the shoot-through state, as shown
Boost factor B for traditional ZSIs can be expressed as in Fig. 3(a), the dc link is short circuited. To reduce conducting
follows [1]: losses of switches and the symmetrical heating distribution
between them, usually, three legs are simultaneously turned on.
Vdc 1 1 Inductors L3 and L4 are paralleled with C3 and C4 , respec-
B= = = (1)
Vin 1 − 2T
T
0 1 − 2D tively; hence, D1 and D2 will turn on, and D3 and D4 are
FATHI AND MADADI: ENHANCED-BOOST Z-SOURCE INVERTERS WITH SWITCHED Z-IMPEDANCE 693

where VL1−OFF and VL3−OFF are the corresponding voltage

across L1 and L3 during the non-shoot-through state. Hence,
the inductors’ voltage in the non-shoot-through state can be
written as [15], [29]
D
VL1−OFF = VL2−OFF = − VC1 (7)
1−D
D
VL3−OFF = VL4−OFF =− VC3 (8)
1−D

Fig. 3. Equivalent circuits. (a) Shoot-through zero state. (b) Non-shoot-

VL1−OFF + VC3 − VC1 = 0. (9)
through state.
The inductors’ current iL1 and iL3 linearly increase during
the shoot-through state and linearly decrease during the non-
reverse biased and will turn off during this state. The sum of two shoot-through state. The corresponding voltages across L1 are
capacitors’ voltage of C1 and C2 is greater than supply voltage equal to Vc1 and −(Vc3 − Vc1 ) and those across L3 are equal
(Vc1 + Vc2 > Vin ); hence, Din is reverse biased. Inductors L1 , to Vc3 and −(Vdc − Vc3 ). Hence, the inductors’ voltage is an
L2 , L3 , and L4 are charged by capacitors C1 , C2 , C3 , and C4 in instantaneous square waveform, with a positive constant value
parallel, respectively. The inductors’ current linearly increases, in the shoot-through state and a negative constant value in the
assuming that the capacitors’ voltage is kept constant during non-shoot-through state.
this state. By using (7) and (9), Vc1 can be expressed as
Non-Shoot-Through State: In this state, the inverter bridge
is in active state. During the non-shoot-through state, as shown VC1 = (1 − D)VC3 . (10)
in Fig. 3(b), Din , D3 , and D4 are on, and D1 and D2 are off due
to the reversed voltage of L3 and L4 across them, capacitors In Fig. 3(b), we have
C1 , C2 , C3 , and C4 are charged, and the energy required by
Vin = VL1−OFF + VL3−OFF + VC2 . (11)
the main circuit is injected by inductors L1 , L2 , L3 , and L4
and the dc voltage source. Therefore, by using more inductors, Using (3), (7), (8), (10), and (11), the voltage across capacitor
the more energy will be transferred, and as a result, higher gain C3 can be further expressed as
will be obtained. In this state, the voltage polarity of inductors
will be reversed; thus, the inductors’ current linearly decreases, 1−D
VC3 = Vin . (12)
assuming that the capacitors’ voltage is kept constant during 2D2− 4D + 1
this state. If the number of inductors in series is high, the energy In Fig. 3(b), we also have
that transfers from the source to the load will be larger, and this
will lead to a higher boosting ratio. Vdc + VL3−OFF − VC3 = 0. (13)

Substituting (8) and (12) into (13), the peak dc-link voltage Vdc
B. Boost Ability Study can be expressed as
Assuming that all the capacitors, i.e., C1 , C2 , C3 , and C4 , 1
have the same capacitance and is sufficiently large, two net- Vdc = Vin = B.Vin (14)
2D2 − 4D + 1
works become symmetrical, and in this case, we will have
where
VC1 = VC2 (3) 1
B= (15)
VC3 = VC4 . (4) 2D2 − 4D + 1

Shoot-Through State: In Fig. 3(a), we can notice that C1 is the boost factor.
is parallel with L1 , C2 is parallel with L2 , C3 is parallel with The peak ac output phase voltage of the inverter can be
L3 , and C4 and is parallel with L4 ; hence, we can write expressed as

Vdc
VL1 = VL2 = VC1 = VC2 (5) Vac = M. (16)
2
VL3 = VL4 = VC3 = VC4 . (6)
where M is the modulation index. Substituting (14) into (16),
In steady state, the average voltage of the inductors in the we obtain
switching period is zero; hence, by applying the volt-second Vin Vin
balance principle to inductors, we have [15], [29] Vac = M.B. = G. (17)
2 2
DVL1 + (1 − D)VL1−OFF = 0 where

DVL3 + (1 − D)VL3−OFF = 0 G = M.B = (0 ∼ ∞) (18)

694 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 2, FEBRUARY 2016

is the buck–boost factor. The buck–boost factor (G) can be

controlled by changing D and M . The duty cycle of shoot-
through, i.e., D, is limited by the modulation index by the
following relation:

D ≤ 1 − M. (19)

The boost factor from (15) indicates that when D is between

0 and 0.29, B varies in (1, ∞). However, the infinite value
of B is not accessible due to parasitic effects of physical
components. Even if a large value of D is used to produce
the high boost gain, the modulation index must be small, as
indicated in (19). However, a low modulation index M will
result in poorer spectral performances and low total harmonic Fig. 4. Boost factor against the duty cycle of shoot-through.
distortion (THD). Small M is generally not preferred since it
leads to low output waveform quality and high power losses
The average capacitor current is zero in one period; hence,
due to lower-order harmonics at output waveforms.
based on Fig. 3(b), we have
Compared with the conventional ZSI with the same modula-
tion index, the proposed ZSI provides higher voltage boosting. iL3(AV ) = (1 − D)iL1(AV ) (28)
Thus, for the same voltage conversion ratio, this ZSI uses
a higher modulation index M to improve the output voltage Ts D(1 − D)iL1(AV )
C3 = . (29)
quality. Hence, with a very low shoot-through duty ratio D, a ΔVC3 Ksh
very high value of M is obtainable.
For the constant value of Ts , iL(AV ) , ΔVc , and Ksh , the
coefficient KC will be defined as
C. Inductor and Capacitor Design
KC1 = D (30)
In shoot-through, the inductors will be charged by capacitors.
Hence, we will have KC3 = D(1 − D). (31)

diL1 It can be seen that the capacitance has direct relation with
VL1 = VL2 = VC1 = VC2 = L1 (20) average inductor current; hence, the more capacitor (inductor)
dt
current will lead to higher capacitor size and increased cost.
diL3
VL3 = VL4 = VC3 = VC4 = L3 . (21)
dt
D. Intrinsic Components’ Effect on Boost Factor
The inductors can be designed by
By considering the intrinsic components of inductors and
Ts Vin D(1 − D)2 capacitors, (15) can be modified as
L1 = (22)
ΔiL1 Ksh 2D2 − 4D + 1
1
Ts Vin D(1 − D) B=  
L3 = (23) rinductor −2D3 +6D2 −7D+2
ΔiL3 Ksh 2D2 − 4D + 1 2D2 − 4D + 1 4 Req−load 2D −4D+1
2

 
rcapacitor (2D3 − 5D2 + 7D − 2)D
where Ksh is the number of shoot-through states in one switch- ···+ 4 (32)
ing period. For the constant value of Ts , Vin , ΔiL , and Ksh , the Req−load (2D2 − 4D + 1)(1 − D)
coefficient KI can be defined as
where rinductor and rcapacitor are the inductor and capacitor
D(1 − D) 2 series resistances, respectively, and Req−load is the equivalent
KI1 = (24) resistance of the load at the dc-link side. It can be seen that with
2D2 − 4D + 1
higher values of series resistances of inductors and capacitors,
D(1 − D) the boost factor reduces.
KI3 = . (25)
2D2 − 4D + 1

In shoot-through, the capacitors’ current is equal to the induc- III. T HEORETICAL C OMPARISON B ETWEEN
tors’ current; hence, the capacitors can be calculated as VARIOUS TOPOLOGIES

Ts DiL1(AV ) Topologies can be compared based on output voltage gain,

C1 = (26) passive components used, and voltage stress on active and pas-
ΔVC1 Ksh
sive components. Fig. 4 shows that with the same duty ratio, the
Ts DiL3(AV ) proposed topology produces a higher boost factor than diode-
C3 = . (27)
ΔVC3 Ksh assisted QZSIs, alternate-cascaded ZSIs, conventional ZSIs,
FATHI AND MADADI: ENHANCED-BOOST Z-SOURCE INVERTERS WITH SWITCHED Z-IMPEDANCE
Fig. 5. Buck–boost factor against the modulation index.
TABLE I
PASSIVE C OMPONENT C OMPARISON
and SL-ZSIs. In other words, the new topology requires a lower
duty ratio for the same boosting voltage. Fig. 5 shows the output
voltage gain against the modulation index for five topologies.
To produce the same output voltage gain, the proposed topology
uses a higher modulation index than the other two traditional
methods. As a result, the output waveform has high quality with
low THD.
Table I shows the comparison of passive components among
five topologies. Although the proposed topology has a higher
boost factor, it requires the same or less numbers of inductors
or diodes compared with diode-assisted QZSIs and traditional
SL-ZSIs.
Voltage stress across switches can be defined as the ratio of
the peak dc-link voltage to G · Vin [22]. As shown in Fig. 6(a),
for the same buck–boost factor, the proposed inverter has a
lower voltage stress across the active devices than the other
four ZSI topologies. Lower stress on switches will lead to in-
expensive devices and, finally, a cheaper inverter. The capacitor
voltage stress is the ratio of capacitor voltage to G · Vin [22].
Fig. 6(b) shows that the capacitor voltage stress for our pro-
posed inverter is higher than the same value in diode-assisted
QZSIs, alternate-cascaded ZSIs, and SL-ZSIs. Moreover, the
maximum voltage stress on a diode can be defined as the ratio
of the maximum voltage stress on the diode to G · Vin [22], as
shown in Fig. 6(c). This fact suggests that in the proposed ZSI,
maximum voltage stresses on diodes are less than those in the
conventional ZSI and the alternate-cascaded ZSI. However, this
value for our circuit for some diodes is higher than the same
value in diode-assisted QZSIs and SL-ZSIs.
The coefficient of KI versus buck–boost factor is shown
in Fig. 7. According to (22)–(25), the KI is a good mea-
sure for inductor volume for the same output power. In
this figure, it is shown that the proposed scheme has lower
695
inductor volume (inductance) compared with conventional ZSI
and SL-ZSI methods. This is due to the fact that the pro-
posed scheme requires smaller D to produce a high boost
factor B. Smaller D will result in lower inductances. How-
ever, due to lower capacitor voltage in alternate-cascaded
ZSIs, it has lower inductance than our proposed method.
The coefficient of KC versus buck–boost factor is shown in
Fig. 8. According to (26)–(31), the KC is a powerful tool
for capacitor volume (capacitance) in ZSIs. As indicated in
Fig. 8, for the same buck–boost factor, the proposed scheme
has lower capacitance than those of the alternate-cascaded ZSI
(N = 2, 3), conventional ZSI, and SL-ZSI topologies. This is
due to the fact that the proposed inverter has a high boost factor
with lower D.
The SDP of a switching device is expressed as the product of
voltage stress and current stress. The total SDP of an inverter
system is defined as the aggregate of SDP of all the switching
devices used in the circuit. Total SDP is a measure of the
total semiconductor device requirement, thus an important cost
indicator of an inverter system. The definitions are summarized
as follows [26], [27]:

N
Total Average SDP = SDPav = Vm Imaverage (33)
m=1

N
Total peak SDP = SDPpk = Vm Impeak (34)
m=1
where N is the number of active devices used; Imaverage and
Impeak are the average and peak current through the device,
respectively; and Vm is the peak voltage induced on the devices.
The average and peak SDPs (for diodes) of the proposed ZSI are

SDPav = Pout B 1 + 2D2 + 2(1 − D)2 (35)
 
1
SDPpk = Pout B 2 + . (36)
(1 − D)
The SDPav and SDPpk factors of the proposed scheme and
alternate-cascaded ZSI (N = 2, 3) have been shown in Figs. 9
and 10, respectively. It is clear that for the same buck–boost
factor, the proposed method has lower SDPav and SDPpk
factors compared with alternate-cascaded ZSI (N = 3). Lower
SDPav and SDPpk factors result in cheaper elements and an
inexpensive inverter. We should mention that based on (33) and
(34), the diode number has a direct effect on the SDPav and
SDPpk factors, and so, the proposed method has higher factors
than alternate-cascaded ZSI (N = 2). However, because of
lower maximum voltage impressed and the lower peak and
average current going through diodes, the proposed method
has lower SDPav and SDPpk factors compared with alternate-
cascaded ZSI (N = 3).
IV. E FFICIENCY C OMPARISON
The calculated losses of the ZSI are based on the loss-
related parameters that are summarized in Table II. The effi-
ciency of the proposed method will be compared with SL-ZSI
and alternate-cascaded ZSI schemes, due to the boost
696 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 2, FEBRUARY 2016

Fig. 6. Voltage stress comparison. (a) Switches. (b) Capacitors. (c) Input diode.

Fig. 8. KC versus buck–boost factor.

Fig. 7. KI versus buck–boost factor.

factor closeness of the three methods. According to the losses of metal–oxide–semiconductor field-effect transistors
parameters listed in Table II, the power losses of the (MOSFETs), core and copper losses of inductors, and conduct-
inverter can be classified as conducting and switching ing losses of diodes and capacitors.
FATHI AND MADADI: ENHANCED-BOOST Z-SOURCE INVERTERS WITH SWITCHED Z-IMPEDANCE
Fig. 9. SDPav of diodes versus buck–boost factor.
Fig. 10. SDPpk of diodes versus buck–boost factor.
Before calculating the power losses of the proposed ZSI,
some assumptions are made.
• The capacitors’ voltage ripples and inductors’ current
ripples are neglected.
• The turn-on loss of diodes is small enough to be
neglected.
• Off-state blocking losses of switches and diodes are
neglected.
• The ripple loss of capacitors is small enough to be
neglected.
A. MOSFET Losses
The power losses of active switches can be classified into
switching loss occurring during the ON and OFF periods of
switching states and conduction loss. The total switching losses
of MOSFETs can be calculated by
Psw = (ton + toff )fsw Vout (2 − D)iin (37)
where fsw is the switching frequency, Vout is the inverter’s
output voltage, iin (= iL1 ) is the average current of dc power
supply, and ton , toff are the turn-on and turn-off delays of
MOSFETs, respectively.
697
TABLE II
PARAMETERS U SED FOR E FFICIENCY C OMPUTATION
The total conduction loss of switches is calculated as
2 1.08(1 − D)3 Pout2
Pconsw = Rds D(2 − D) iin + 2 2
(38)
3 M 2 B 2 cos ϕ2 Vin2
where Rds is the drain-to-source resistance of MOSFETs, Pout
is the inverter’s output power, and cos ϕ is the load power factor.
B. Inductor Losses
The power losses of inductors can be classified into core loss
and conduction loss. Due to small inductor current ripples, the
core loss is very small compared with the total power loss of
inductors. However, the core losses per unit volume of T184-26
can be obtained from the Micro-metal provided datasheet. The
total conduction loss of inductors can be calculated as
Plc = 2RL i2in + 2RL i2in (1 − D)2 (39)
where RL is the equivalent series resistance (ESR) of inductors
that is provided in Table II.
698 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 2, FEBRUARY 2016
Fig. 11. Efficiency versus buck–boost factor.
Fig. 12. Percentage losses versus buck–boost factor in the proposed method.
C. Capacitor Losses
By using the ESR of capacitors in Table II, the total conduc-
tion losses of the capacitor can be calculated as
 
D The ratio of MOSFET losses to output power for the afore-
Pc = 2Rc iin2
+ D(1 − D) + D (1 − D)
2 2
(40)
1−D
where Rc is the ESR of the capacitor.
D. Diode Losses
By assuming that the inductor currents are ripple free, the
total conduction losses of diodes can be calculated as
Pdloss = 3Vf iin (41)
where Vf is the forward voltage drop of each diode, and
iin (= iL1 ) is the average current of dc power supply.
The calculated efficiencies of the proposed inverter, SL-ZSI,
and alternate-cascaded ZSI schemes versus boost factor are
shown in Fig. 11. From these results, it is clear that for the
same buck–boost factor, the proposed scheme provides higher
efficiency than those of SL-ZSI and alternate-cascaded ZSI
schemes. To verify the claimed results in Fig. 11, each loss
will be analyzed individually. The percentage losses of each
component in the proposed method are summarized in Fig. 12.
It can be seen that for higher values of the boost factor, the
losses are mainly contributed by the inductor and capacitor.
Among them, the inductor loss is largest. Hence, the higher
inductance in the power loop will result in the inverter’s higher
losses and, finally, lower efficiency.
mentioned methods is shown in Fig. 13. It can be seen that
the proposed method has lower MOSFET losses compared with
other methods, due to lower shoot-through current in the pro-
posed method than those in SL-ZSI and alternate-cascaded ZSI
schemes. The ratio of diode losses to output power for the three
schemes is shown in Fig. 14. Since the alternate-cascaded SZI
(N = 2) has lesser diode numbers, it has lower diode losses.
Fig. 15 indicates the ratio of inductor losses to output power.
Although the number of inductors in the proposed scheme
is higher than those in the alternate-cascaded SZI (N = 2),
it has lower inductors’ losses compared with the alternate-
cascaded SZI (N = 2). Due to lower capacitors’ current in the
proposed ZSI compared with SL-ZSI and alternate-cascaded
ZSI schemes, the proposed ZSI has lower capacitors’ losses
than the other mentioned methods, as shown in Fig. 16. Since
the proposed ZSI has lower capacitor currents, it provides
higher reliability with lower losses, size, and cost.
From the results in Figs. 13 and 14, it can be seen that
the proposed method has lower current stress (for MOSFETs
and diodes) than those of SL-ZSI and alternate-cascaded ZSI
schemes.
FATHI AND MADADI: ENHANCED-BOOST Z-SOURCE INVERTERS WITH SWITCHED Z-IMPEDANCE 699

Fig. 13. MOSFET loss/Pout versus buck–boost factor.

Fig. 14. Diode loss/Pout versus buck–boost factor.

Fig. 15. Inductor loss/Pout versus buck–boost factor.

V. S ELF -B OOST P HENOMENA
According to [27], without the shoot-through, the ZSI has a
voltage boost when operated at a low modulation index and a
low power factor. This phenomenon is called “self boost.” We
can define a critical M such that for lower values of Mcritical,
the uncontrolled shoot-through will occur. For traditional ZSIs,
Mcritical can be defined as [27]
2 same voltage conversion ratio, the proposed scheme uses a
Mcritical = . (42)
3 ∗ cos ϕ
Hence, for the proposed method, Mcritical can be obtained as
2
Mcritical = . (43)
3 ∗ cos ϕ ∗ (2) − D
Based on (43), the Mcritical for the proposed method is much
lower than that for the traditional ZSI. Hence, the acceptable
interval of M is much higher than that for the traditional ZSI.
Due to high boosting capabilities of the proposed ZSI for the
higher M to improve the inverter’s output quality.
700
Fig. 16. Capacitor loss/Pout versus buck–boost factor.
Fig. 17. Simulation results for the proposed ZSI, i.e., M = 0.82 and D = 0.18.
VI. S IMULATION AND E XPERIMENTAL R ESULTS
A. Simulation Results
The proposed topology shown in Fig. 2 has been simulated
by the PSIM software platform. The main circuit parameters for
the proposed topology are as follows:
1) L1 = L2 = L3 = L4 = 700 μH, C1 = C2 = C3 =
C4 = 500 μF;
2) switching frequency Fs = 10 kHz;
3) three-phase load R = 60 Ω, L = 5 mH;
4) dc input voltage Vin = 100 V.
Fig. 17 shows the simulation results for the proposed ZSI
with a shoot-through duty cycle of D = 0.18 and a modulation
index of M = 0.82. From (10), (12), (15), and (18), the boost
factor is B = 2.9, and the buck–boost factor is G = 2.38. From
the simulation results, one can observe that the capacitors’
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 2, FEBRUARY 2016
voltage Vc1 and Vc3 are, respectively, boosted to 195 and 237.5 V
in the steady state, and the peak dc-link voltage Vdc is boosted
to 290 V. Hence, the boosted factor can be calculated to be
290/100 = 2.9. Meanwhile, the peak ac output phase voltage
V̂ac has been boosted to 119 V.
These results clearly verify the high boosting capability of
the proposed ZSI. The simulation results clearly show that the
dc-link voltage and the phase voltage are boosted with the boost
factor 290/100 = 2.9 and 119/50 = 2.38, respectively, which
are consistent with the calculated values from (15) and (18)
when substituting D = 0.18 and M = 0.82. Hence, it has been
seen that in steady state, there is a good agreement between
simulation results and theoretical analysis. Fig. 18 shows the
dc-side response where the shoot-through is changed from 0.1
to 0.18. This will demonstrate the boosting capability in the
transient condition. At 0.3 s, D has a step change and Vdc
would change from 160 to 290 V. After some transients, Vc3
also increases from 145 to 237.5 V.
FATHI AND MADADI: ENHANCED-BOOST Z-SOURCE INVERTERS WITH SWITCHED Z-IMPEDANCE
Fig. 18. Transient behavior of the proposed ZSI.
Fig. 19. Experimental setup.
B. Experimental Results
The proposed ZSI was built in laboratory with the same pa-
rameter used in simulation. Fig. 19 shows the experimental setup.
As depicted, this setup includes the power MOSFETs, driver
boards, Z-impedance networks, and high-performance micro-
controller Atxmega128A3U. Fig. 20 shows the experimental
results for the proposed ZSI when the shoot-through duty
cycle is D = 0.18 and the modulation index is M = 0.82. The
dc-link voltage is boosted from 100 to 268 V, which is slightly
less than the calculated value (2.9∗ 100 = 290 V) from (15) due
to the voltage reduction on the passive components, diodes,
and switching devices. Capacitor voltages Vc1 and Vc3 are
boosted to 186 and 219 V, respectively. Substituting D = 0.18
and Vin = 100 V into (12), the calculated voltage for Vc3 is
237.5 V, which is slightly higher than the measured value.
Meanwhile, the root-mean-square value of line-to-line output
voltage is 193 V. Fig. 20 further shows the dc-link voltage,
inductor current, and load current, which are clearly similar
to simulations except for some spikes and switching noise su-
perimposed. These spikes and noise are not seen in simulation
and are thus likely picked up from the hardware semiconductor
switching. Because of proper snubber design, the MOSFETs
have enough protection against the spikes and noise. In Fig. 20,
it is very clear that the peak dc-link voltage maintains a
constant value during the non-shoot-through states, and it is
701
Fig. 20. Experimental results of the proposed ZSI with D = 0.18 and
M = 0.82.
quite consistent with the theoretical value. The experimental
and simulation results in Figs. 17 and 20 match well with each
other and those of the theoretical analysis for the proposed
inverter. Fig. 21 indicates the THD of output current under
D = 0.18 and M = 0.82 and with series load of L = 5 mH,
and R = 60 Ω. It is clear that the THD is at an acceptable
level. According to (43), with D = 0.18, L = 5 mH, and
R = 60 Ω, Mcritical = 0.36. Fig. 22 shows the experimental
results for the proposed method with D = 0.18, and M = 0.36.
It can be seen that the ZSI inverter works in normal operating
mode, and the dc-link voltage is 286 V, which is slightly higher
than that by M = 0.82. Fig. 23 shows the THD of output
current under D = 0.18 and M = 0.36 and with series load of
L = 5 mH, and R = 60 Ω. Because of lower M , it can be seen
that the current THD is higher than that of Fig. 21. In Fig. 24,
M = 0.2 (M < Mcritical ), and it can be seen that the dc-link
voltage has been boosted to 312 V, which is higher than that
obtained from (15). The waveforms of load current under
L = 5 mH, and R = 60 Ω, and various values of M are shown
in Figs. 20, 22, and 24. It can be seen that by decreasing the
modulation index, the quality of the inverter’s output current
will be distorted.
702 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 63, NO. 2, FEBRUARY 2016
Fig. 21. THD of output current with D = 0.18 and M = 0.82.
Fig. 22. Experimental results of the proposed ZSI with D = 0.18 and
M = 0.36.
Fig. 23. THD of output current with D = 0.18 and M = 0.36.
Table III shows the simulation and experimental results of the
peak dc-link and capacitor voltages for the proposed inverter.
From Table III, we can observe that the simulated dc-link volt-
age and capacitor voltages Vc1 and Vc3 are, respectively, 7.59%,
4.46%, and 7.5% higher than the experimental values. This is
due to the fact that the voltage drop on passive components,
switches, and diodes was ignored in simulation, whereas it
cannot be ignored in real passive components, switches, and
diodes.
Fig. 24. Experimental results of the proposed ZSI with D = 0.18 and
M = 0.2.
TABLE III
P EAK DC L INK AND C APACITOR VOLTAGE IN
S IMULATION AND E XPERIMENT
Although this topology provides high step-up inversion with
high efficiency, it also suffers from the following limitations
and drawbacks.
• The current drawn from the dc source is discontinuous
due to the input diode.
• It has greater size and cost due to extra passive compo-
nents compared with the traditional ZSI.
• Because the initial voltage across the Z-source capacitors
is zero, a huge inrush current flows to the Din and capac-
itors that lead to output voltage and current spikes.
• The boost factor has been limited by various parameters,
such as THD, losses, and parasitic effects of components.
VII. C ONCLUSION
Enhanced-boost ZSI based on switched Z-impedance has
been presented. Compared with the conventional ZSI, diode-
assisted QZSI, alternate-cascaded ZSI (N = 2), and SL-ZSI,
the proposed inverter has the highest boosting ability and lowest
voltage stress on active components. Comparison between the
proposed topology and previously proposed schemes, in terms
of inductor numbers, voltage and current stresses on elements,
efficiency, sizes of inductors and capacitors, and SDP factors
of diodes, has been made, and the results verify the priority of
the proposed topology. Both the simulation and experimental
results verify the advantages and effectiveness of the pro-
posed ZSI.
FATHI AND MADADI: ENHANCED-BOOST Z-SOURCE INVERTERS WITH SWITCHED Z-IMPEDANCE
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Hossein Fathi received the B.Sc. degree from
Hadaf Institute, Tabriz, Iran, in 2011 and the
M.Sc. degree from Sahand University of Tech-
nology, Tabriz, Iran, in 2014.
His main research interests include power
electronic converters.
Hossein Madadi (M’15) received the Ph.D. de-
gree in electrical engineering from the University
of New Brunswick, Fredericton, NB, Canada, in
2003.
Since 1993, he has been a faculty member
with Sahand University of Technology, Tabriz,
Iran. During 2003–2004, he was a Postdoctoral
Fellow with the University of New Brunswick.
He is currently the Managing Director of the
Renewable Energy Research Center, Sahand
University of Technology. He has published over
100 papers in technical journals and conference proceedings and two
books. His principal research interests and experience include renew-
able energy conversion, power electronic converters, and variable-
speed drives.