Received February 27, 2020, accepted March 9, 2020, date of publication March 16, 2020, date of current version

March 26, 2020.

Digital Object Identifier 10.1109/ACCESS.2020.2981126

DC-Link Quasi-Switched Boost Inverter With

Improved PWM Strategy and Its
Comparative Evaluation
MINH-KHAI NGUYEN 1,2 , (Senior Member, IEEE), TRUONG-DUY DUONG 3 ,
YOUNG-CHEOL LIM 3 , (Member, IEEE), JOON-HO CHOI 3 , (Member, IEEE),
D. MAHINDA VILATHGAMUWA 1 , (Fellow, IEEE), AND
GEOFFREY R. WALKER 1 , (Member, IEEE)
1 Schoolof Electrical Engineering and Computer Science, Queensland University of Technology, Brisbane, QLD 4000, Australia
2 Facultyof Electrical and Electronics Engineering, Ho Chi Minh City University of Technology and Education, Ho Chi Minh City 700000, Vietnam
3 Department of Electrical Engineering, Chonnam National University, Gwangju 61186, South Korea

Corresponding author: Young-Cheol Lim (yclim@chonnam.ac.kr)

This work was supported in part by the Korea Electric Power Corporation under Grant R18XA04, and in part by the Korea Institute of
Energy Technology Evaluation and Planning(KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea
under Grant 2019381010001B.

ABSTRACT Low voltage stress on the impedance source network devices is the main reason for the advent of
DC-linked type quasi-switched boost inverters (DqSBIs). However, the DqSBI has become less attractive due
to its low voltage gain. This paper presents a novel PWM control strategy for the DqSBI and its comparative
performance evaluation to the conventional inverters. The modified PWM control strategy based DqSBI
improves the voltage gain and reduces the conduction loss and the inductor current ripple. Circuit analysis
and comparison study between the DqSBI, the quasi-Z-source inverters, and the two-stage inverter with a
boost DC-DC converter are presented. 1-kVA three-phase inverter prototypes were set up to compare and
evaluate the performance of the DqSBI with the improved PWM method for voltage gains of 0.85 to 1.6.
The measured efficiency and total harmonic distortion (THD) values are also presented.

INDEX TERMS Quasi-switched boost inverter, quasi-Z-source inverter, two-stage inverter, shoot-through,
DC-linked type.
I. INTRODUCTION
Industry has been embracing green energy sources such as
photovoltaic (PV), wind power, and fuel cell stacks as power
generation becomes more environmental-friendly. DC-AC
power converters play an essential role for these renewable
energy sources are to be inserted to the distributed power
system. Conventional voltage source inverters (VSIs) and
current source inverters (CSIs) are most commonly in the
inverter topologies. However, they have some limitations, for
instance, the peak value output voltage in traditional VSIs is
always lower than the DC input voltage source. Thus, VSIs
are only operated in buck mode. In the same way, traditional
CSIs only operate in boost mode. When the voltage buck
and boost applications are required, a DC-DC power con-
version stage is added to the traditional VSI to step-up the
low DC input voltage [1], [2] which means such a topology
The associate editor coordinating the review of this manuscript and
approving it for publication was Chi-Seng Lam . DC-AC power conversion systems. The single-stage
forms a two-stage power converter. For example, a two-
stage miniboost inverter proposed in [3] has only a fraction
of the PV inverter nominal power processed by traditional
boost converters called miniboost with the use of smaller
components. In [3], two separate miniboost converters are
connected in front of the VSI to enhance the system conver-
sion efficiency. In the conventional two-stage boost converter
based inverter (TBI), the shoot-through (ST) state, where both
power switches in one-leg are turned on at the same time,
is forbidden. To prevent the ST phenomenon in the TBI,
a dead-time is inserted into the gating signals of the upper
and lower switches in each phase leg. As a result of using
dead-time, the total harmonic distortion (THD) of the output
waveform is increased. Some dead-time effect compensation
techniques have been introduced in [4], [5] at the expense of
increased complexity of the control system.
During the last few years, single-stage power conver-
sion systems have been introduced along side the two-stage

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 M.-K. Nguyen et al.: DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and Its Comparative Evaluation
impedance- or Z-source inverter (ZSI) was firstly introduced
in [6] with the buck-boost voltage ability and ST immunity.
In the ZSI, the ST state is inserted to give the high AC voltage
from the low input sources. The inconvenient features of the
classical ZSI such as the large inrush current problem, a high
capacitor voltage stress, and a discontinuous source current
can be solved by using a family of quasi-ZSIs (qZSIs) as
suggested in [7]. The continuous input current qZSI (CqZSI)
and DC-link qZSI (DqZSI) are two basic single-stage qZSI
topologies.
Recently, the comparison of the single-stage ZSIs with the
conventional TBI have been carried out in [8]–[13]. In [8], the
comparison between the classical ZSI and TBI for fuel-cell
vehicles was discussed. In this study, the power switches are
operated in high switching loss and high power applications.
Reference [8] reveals that ZSI is very emulative with good
reliability and improved efficiency when the AC voltage ratio
is not higher than 2. In the same way, the simulated power
losses of both ZSI and TBI were compared in [9]. On the other
hand, the work in [10] compared CqZSI with TBI for the same
DC-link voltage operation. For the same DC-link voltage or
modulation index, CqZSI shows a lower THD and a higher
efficiency than TBI. The objective criteria for comparing the
conventional electric traction TBI with the original ZSI or
CqZSI was presented in [11]. Furthermore, a comparison
between CqZSI and TBI based on wide band-gap devices was
presented in [12]. The three-level CqZSI was compared with
the three-level VSI with additional DC–DC boost converter at
the same operating voltage gain of 1.33 [13]. The compared
results from [8]–[13] show that ZSIs have a higher perfor-
mance than TBI at the voltage gain range of (1 – 1.5). When
the voltage gain is more than 1.5, the efficiency of ZSIs is
significantly reduced in comparison to that of TBI. This is
because the main H-bridge switches of ZSIs must conduct
a very large ST current that is equal to double of the input
current and that results in a high conduction loss. Because
TBI uses an unity modulation index, it has a lower power loss
and a lower voltage DC-link voltage stress than ZSIs when
the voltage gain is high. In fact, most works based on ZSIs
for electric vehicle [14], [15], PV [16]–[18], and integrated
system [19] applications are only implemented at a low volt-
age gain. The single-stage ZSIs have been recommended for
applications where the high reliability is required due to ST
immunity.
However, the size and weight of ZSIs are increased because
two inductors and two capacitors are used in the impedance-
source network. To reduce the size and weight of the inverter,
a class of quasi-switched boost inverters (qSBIs) such as
embedded types and DC-link types was proposed in [20].
QSBIs overcome qZSIs with reducing size, weight, and low
power losses [21]. To enhance the performance of the con-
tinuous input current qSBI (CqSBI), several PWM control
strategies have been introduced as presented in [22]–[25].
A PWM control strategy was employed to the single-phase
CqSBI in [22] to obtain a higher modulation index. Simi-
larly, a modified PWM scheme to improve performance of
53858
the single-phase current-fed switched inverter was presented
in [23]. With the PWM methods in [22] and [23], the input
inductor current ripple of the inverter cannot be controlled
compared to the method in [24]. By turning on the additional
switch at a different time of the ST state, a low inductor
current ripple and a high modulation index are achieved for
CqSBI as presented in [24]. However, the switching loss of
the additional switch is increased under the PWM control
methods in [24]. In addition, a maximum boost PWM con-
trol technique was used in [25] to improve voltage gain of
CqSBI by modifying the ST control signal. As presented
in [21]–[24], CqSBI can be used to replace CqZSI when
a high boost voltage gain of 2 to 3 is needed. When the
buck mode operation and a low voltage gain are required,
a low modulation index can be used in CqSBI while a high
DC-link voltage with large ST duty cycle is retained as pre-
sented in [26]. As a result of using a low modulation index
at a high boost factor for the buck mode operation, CqSBI
performs with lower efficiency and higher current distortion.
To prevent unexpected operating modes of CqSBI at a high
modulation index and a small boost voltage, one active switch
is used to replace the diode in the switched-boost network as
discussed in [25]. That solution is not effective because two
additional switches are needed in the Z-source network, and
the ST immunity feature of CqSBI is not guaranteed.
The qSBI topologies have been extended to cascaded
H-bridge inverter [27], three-level inverter [28], isolated
DC-DC converter [29], and half-bridge inverter [30].
Although DC-link qSBIs (DqSBIs) were introduced at the
same time as CqSBIs, they are less attractive due to their
low voltage gain. Compared to CqSBI topologies, how-
ever, DqSBIs can give lower voltage stress on components
in Z-network. This reduce the size, weight, and loss of
the impedance-source inverter. A study on DqSBIs with
improved voltage gain has been presented in [31] without
detail analysis and comparative performance evaluation.
This paper analyses and verifies the comparative perfor-
mance of the three-phase DC-link qSBI with a improved
PWM strategy for low voltage gain applications. In the intro-
duced PWM strategy, the duty cycle of the additional active
switch is constant, while the ST duty cycle is a control vari-
able. In the next section, the conventional three-phase inverter
topologies including the two-stage inverter with a boost con-
verter, CqZSI, and DqZSI are reviewed. The operational
principle of DqSBI with improved PWM control technique
is presented in Section III. A comprehensive comparison
study is given in Section IV. Finally, experimental results are
provided in Section V to verify the analysis.
II. THREE-PHASE INVERTER TOPOLOGIES
A. TWO-STAGE BOOST CONVERTER BASED
INVERTER (TBI)
Fig. 1(a) shows the well-known TBI. The boost DC-DC
converter is added to the front end of the three-phase inverter
to boost the source voltage to the desired DC-link voltage.
In TBI, a dead-time should be used to avoid the short circuit of
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M.-K. Nguyen et al.: DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and Its Comparative Evaluation
FIGURE 1. Three-phase inverter topologies. (a) Conventional two-stage
inverter with a boost converter (TBI), (b) CqZSI, (c) DqZSI, (d) CqSBI and
(e) DqSBI.
the H-bridge inverter. Consequently, the efficiency and output
waveform quality are affected by the dead-time.
The DC-link voltage of TBI is calculated as
1 the reference value of VST with the carrier frequency vtri2 ,
VPN _TBI = VC1 = Vg ,
1 − D0
where D0 is the duty cycle of switch S0 . The voltage stress of
the switch S0 is equal to the DC-link voltage.
B. QUASI-Z-SOURCE INVERTERS (qZSIs)
Figs. 1(b) and 1(c) respectively show single-stage CqZSI and
DqZSI where a passive impedance-source network is used to
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decouple the DC source and the H-bridge inverter. Because
the inductor L1 is directly connected to the voltage source,
the input current of CqZSI is continuous. The capacitor C1
voltage stress in CqZSI is high. By changing the connection
of the negative node of the C1 capacitor, DqZSI is obtained
with the benefit of a lower voltage stress on both capacitors.
Then, the source current of DqZSI flows to the main H-bridge
circuit with a high ripple. Both CqZSI and DqZSI have the
same DC-link voltage as
1
VPN _qZSI = Vg , (2)
1 − 2DST
where DST is the ST duty cycle.
C. QUASI-SWITCHED BOOST INVERTERS (qSBIs)
Figs. 1(d) and 1(e) show the circuit diagram of CqSBI and
DqSBI [20], respectively. An active impedance-source net-
work including one inductor, one capacitor, one switch, and
two diodes is used in the qSBIs to boost the input volt-
age. CqSBI and DqSBI have the same features as CqZSI
and DqZSI such as buck-boost voltage, ST immunity, and
single-stage power conversion. When a PWM method in [20]
is used where the additional switch, S0 is only turned on
during the ST state of the H-bridge inverter, the DC-link
voltage of CqSBI is the same as that of qZSIs in (2), while
the DC-link voltage of DqSBI is expressed as
1 − DST
VPN _DqSBI = VC1 = Vg . (3)
1 − 2DST
By comparing (3) to (2), DqSBI has a lower voltage boost
than CqSBI and qZSIs.
III. IMPROVED PWM CONTROL STRATEGY FOR DqSBI
Fig. 2 shows the conventional PWM control method in [20]
and improved PWM control strategy based on the maximum
constant boost control method with a third harmonic injec-
tion [8] for single-stage DqSBI. The control signals for lower
switches S4 , S6 , and S2 in the H-bridge are complementary
to those for upper switches S1 , S3 and S5 , respectively. The
ST control signal is inserted into the H-bridge switch signals
through an OR logic gate. Fig. 3(a) represents an equivalent
circuit of DqSBI, where the three-phase inverter and load are
modeled as a current source. Unlike the conventional PWM
method for DqSBI in [20] as shown in Fig. 2(a), where the
additional switch S0 is simultaneously turned on during the
ST state, the proposed PWM control method triggers switch
S0 outside the ST time interval. As shown in Fig. 2(b) for the
improved PWM strategy, the ST state is formed by comparing
(1) while the turn-on state of switch S0 is a result of the com-
parison between the reference value of V0 and vtri2 . In this
case, S0 can be turned on during the non-ST modes of the
H-bridge circuit with the duty cycle of D0 . During the ST time
interval of DST ·T , where DST is s duty cycle in one-switching
period T , all H-bridge switches are turned on at the same time.
Consequently, DqSBI with the proposed PWM strategy has
three operating modes as shown in Figs. 3(b)-3(d).
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FIGURE 3. Operating modes of DqSBI. (a) Equivalent circuit, (b) ST mode,

(c) non-ST mode 1, and (d) non-ST mode 2.

C. NON-ST MODE 2
In the non-ST mode 2 as shown in Fig. 3(d), S0 is turned off,
while the H-bridge switches operate in either active state or
zero state. Both diodes D1 and D2 are forward-biased. The
inductor releases energy, while the capacitor is charged. The
time interval in this mode is (1–DST –D0 ) · T . The equations
can be given
di

L1 L = −VC1

FIGURE 2. PWM control strategies for DqSBI. (a) Conventional PWM dt
method in [20], (b) improved PWM method, (c) an enlargement of (a), and (6)
dv
C1 C = IL − IPN ,

(d) an enlargement of (b).
dt
A. ST MODE where IPN is the average DC-link current in non-ST modes.
In the ST mode, the H-bridge switches are turned on at the In the steady state, applying the volt and ampere-second
same time, while S0 is turned off. Diode D1 is forward- balance principle to the inductor and the capacitor over one
biased, whereas diode D2 is reverse-biased. The inductor switching period are zero. From (4) to (6), the equations are
stores energy, while the capacitor is idle. The equivalent obtained
circuit of DqSBI in the ST mode is shown in Fig. 3(b). The  DST
time interval in this mode is DST · T . The equations can be VC1 =
 Vg 1−DST
1 − D0 − DST and IL = IPN .
derived 1 − D 0 1−D 0 −DST
VPN = Vg ,

di

1−D0 −DST
L1 L = Vg

dt (7)
(4)
dv
C1 C = 0,

The boost factor and the peak AC output phase voltage of
dt
DqSBI can be rewritten as
VPN 1 − D0

B. NON-ST MODE 1 B =
 =
During non-ST mode 1 in Fig. 3(c), S0 is turned on during Vg 1 − D0 − DST (8)
the time interval of D0 · T , and the H-bridge switches turn V̂o = M · VPN = M · B · Vg = G · Vg ,

on and off in either active state or zero state. Diode D1 2 2 2
is reverse-biased whereas diode D2 is forward-biased. The where G is the voltage gain.
stored energy in the inductor in the ST mode is maintained, Fig. 4 shows the relationship between the boost factors and
while the capacitor is restored. The equations are obtained as the ST duty cycle at several values of D0 . Fig. 5 shows the

di voltage gain versus the modulation index when M = 1.15×
L1 L = 0

(1 – DST ). In these figures, the duty cycle of the additional
dt (5)
dv switch, D0 is changed from 0.3 to 0.8. In the impedance-
C1 C = −IPN ,

dt source inverter, the modulation index is limited by the ST

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M.-K. Nguyen et al.: DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and Its Comparative Evaluation
TABLE 1. Overall comparison between TBI, qZSIs and DqSBI.
FIGURE 4. Comparison of (a) voltage boost factor vs. ST duty cycle and
(b) inductor current stress (IL /IPN ) vs. ST duty cycle of qZSIs, CqSBI, DqSBI
with PWM method in [20] and DqSBI with improved PWM method.
FIGURE 5. Comparison of voltage gain vs. modulation index of qZSIs,
CqSBI, DqSBI with PWM method in [20] and DqSBI with improved PWM
method.
duty cycle value as 1.15×(1 – DST ) since the ST state is
only inserted into the zero states of the H-bridge inverter.
To generate the high voltage gain from the same M and DST ,
a large value of D0 can be used. However, the large value
of D0 will result in high current stress on the inductor as
shown in Fig. 4(b). In Fig. 4(a) at D0 = 0.5, the boost
factor and voltage gain of DqSBI are the same as those of
the qZSI. It can be seen that the boost factor, inductor current
VOLUME 8, 2020
stress and voltage gain of the DqSBI with improved PWM
method is higher than that of qZSIs, CqSBI and DqSBI with
conventional PWM method in [20] when D0 > 0.5. To keep
a low voltage stress on semiconductors and capacitor and to
improve the voltage gain, the value of D0 should be in range
of (0.5, 0.7). In this paper, the value of D0 is selected as 0.6.
Then, the control variable of DqSBI is the ST duty cycle.
When the ST duty cycle is zero, DqSBI operates in buck
mode.
IV. COMPARISON STUDY
In this section, DqSBI with improved PWM method at
D0 = 0.6 is compared to the other buck-boost inverter con-
figurations including TBI, CqZSI, DqZSI, CqSBI and DqSBI
with conventional PWM method in [20]. Table 1 presents
a comprehensive comparison between DqSBI and the other
inverters. When D0 = 0.6, DqSBI with improved PWM
method has a higher boost factor than the other inverters
for the same ST duty cycle as shown in Fig. 4(a). Fig. 6(a)
compares the capacitor voltage stress of the inverters. The
DqSBI with the improved PWM control method has the
lowest capacitor voltage stress. The diode D1 voltage stress
of the DqSBI with improved PWM method is lowest as
shown in Fig. 6(b). The diode D2 voltage stress of DqSBI
with improved PWM method is lower than that of CqZSI,
DqZSI, CqSBI and DqSBI with conventional PWM method
in [20]. The switch voltage stress comparison is shown in
Fig. 6(c). Among them, the additional switch S0 of DqSBI
with improved PWM method is lowest. The voltage stress of
the H-bridge switches S1 -S6 of DqSBI with improved PWM
method is lower than that of qZSIs, CqSBI and DqSBI with
conventional PWM method in [20]. It is worth noting in this
comparison that the voltage stress of H-bridge switches S1 -S6
of the TBI is lower than that of DqSBI with improved PWM
method since the modulation index of TBI is always kept at
the maximum value, while it is changed corresponding to G
in DqSBI.
DqSBI uses one more diode than TBI. However, the volt-
age stress on the switch and capacitor of DqSBI is
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FIGURE 6. Comparison of (a) capacitor voltage stress, (b) diode voltage stress, (c) switch voltage stress, (d) inductor and ST current stresses, and
(e) inductor current ripple.

significantly reduced in comparison with that of the TBI. where Rl is the simplified equivalent DC load of the inverter’s
When compared with qZSIs, DqSBI saves one inductor and AC side circuit, fs is the switching frequency of H-bridge
one capacitor but uses one more switch and one more diode inverter.
with very low voltage rating. Therefore, the size and weight The inductor L1 current ripple of TBI is given as
of DqSBI are reduced. Like qZSIs, DqSBI has a high relia-
D0 (1 − D0 )2 · Rl
bility because of ST immunity that TBI lacks. Consequently, rL1_TBI % = . (10)
the dead-time effect in the main H-bridge switches can be L1 · 2fs
ignored in qZSIs and DqSBI. This results in increased output The current ripple of inductors L1 and L2 in qZSIs is
quality and reduced power loss of the inverter. The ST current determined as
and inductor current of DqSBI with improved PWM method D (1 − 2D) · Rl
are higher than those of TBI, qZSIs, CqSBI and DqSBI with rL1_qZSI % = rL2_qZSI % = . (11)
(1 − D) L1 · 2fs
conventional PWM method in [20] as shown in Fig. 6(d). This
disadvantage makes DqSBI with improved PWM method less The inductor L1 current ripple of CqSBI is given as
attractive for high voltage gain and high-power applications. 2D (1 − 2D) · Rl
Therefore, DqSBI with improved PWM method is highly rL1_CqSBI % = . (12)
(1 − D) L1 · 2fs
recommended for scenarios similar to miniboost inverter
The inductor L1 current ripple of DqSBI with conventional
in [3].
PWM method in [20] is given as
Under the improved PWM control method, the induc-
tor current waveform of DqSBI is shown in Fig. 2. When D (1 − 2D) · Rl
rL1_DqSBI [20] % = . (13)
D0 = 0.6, the inductor L1 current ripple of DqSBI can be (1 − D)2 L1 · 2fs
evaluated based on the slope of the inductor L1 current in the
Fig. 6(e) presents the relationship between the inductor
time interval of DT as in (9).
current ripple versus the voltage gain of TBI, qZSIs, CqSBI,
D (0.4 − D)2 · Rl and DqSBIs when all inverters are operated in the same
rL1_DqSBI % = , (9)
0.4 (1 − D)2 L1 · 2fs values of inductance, switching frequency, and output power.

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TABLE 2. List of parameters.

As shown in Fig. 6(e), the inductor current ripple of DqSBI

with improved PWM method is the lowest and as such the
size of inductor can be significantly minimized.

V. RESULTS
A. HARDWARE SETUP
The 1-kVA three-phase inverter prototypes were built to
validate the performance of DqSBI and compare with the
conventional inverters for low voltage gains of 0.85 to 1.6.
Because CqSBI has a low performance at low voltage gains,
it is not tested in the experiments. Table 2 shows the param-
eters of five inverter prototypes: TBI, CqZSI, DqZSI, DqSBI
with conventional PWM method in [20], and DqSBI with
improved PWM method in the experiment. 1.5 mH/10-A
inductors, a three-phase low-pass filter, a DSEC60-06A
diode, and six FGH75T65SQD insulated-gate bipolar tran-
sistors (IGBTs) were used in TBI, qZSIs, and DqSBI with
improved PWM method, while DSEI30-10A diode and
FGL60N100BNTD IGBTs and are used in DqSBI with
conventional PWM method. The 680 µF/450-V electrolytic
capacitor was used for C1 in TBI and CqZSI, while the
680 µF/200-V electrolytic capacitor was used in DqSBI,
DqZSI, and CqZSI for C2 . An IPW60R045CPA CoolMOS
MOSFET from Infineon was used in the TBI, whereas an
IRFP4668PbF MOSFET with a low drain-source resistance
was used in DqSBI with improved PWM method. A Schottky
STPS60SM200C diode with a low forward voltage drop was
used in DqSBI with improved PWM method. A Tektronix
TDS3014B digital oscilloscope was used to capture wave-
forms. The input power was measured by a YOKOGAWA
WT230 power meter, while the HIOKI PW3360 power ana-
lyzer was used to measure the output power and harmonics.
The measured efficiency of the four inverters is a ratio of the
output power over the input power. Fig. 7 shows a test bench
of the experimental setup.
FIGURE 7. A photo of the experimental setup.
B. EXPERIMENTAL WAVEFORMS FOR DqSBI WITH
IMPROVED PWM METHOD
Fig. 8 introduces the experimental waveforms of DqSBI with
improved PWM strategy at the voltage gain of 1.27 when the
modulation index and the ST duty cycle are 0.94 × 1.15 and
0.06, respectively. In this experiment, the value of D0 is kept
at 0.6. The load power in this test is 910 W. The DC-link
and capacitor voltage of DqSBI are respectively boosted to
290 V and bucked to 43 V from the 250 V input voltage.
The experimental values of the DC-link and capacitor voltage
are slightly lower than the theoretical values of 294 V and
44 V. As shown in Fig. 8(b), both switch S0 and diode D1
experience an identical blocking voltage of 43 V that is equal
to the capacitor C1 voltage. The experimental results match
the theoretical analysis.
C. COMPARATIVE EVALUATION
In TBI, the switching frequency of switch S0 is set to 20-kHz.
The dead-time between two switches on each phase leg is kept
to 1 µs in TBI, while it is zero in DqSBIs, CqZSI, and DqZSI.

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FIGURE 8. Experimental results for DqSBI when Vg = 250 V, D0 = 0.6,
DST = 0.06, and M = 0.94 × 1.15. From top to bottom: (a) Inductor
current, output phase A and B currents, and unfiltered line voltage;
(b) DC-link voltage, switch S0 voltage, diode D1 voltage, and capacitor
voltage; (c) zoom out of inductor current, diode D2 voltage, inductor
voltage, and input voltage; and (d) harmonic spectrum of output phase-A
current.
The control parameters of four inverters for the comparative
evaluation are shown Table 3. In the buck mode, the ST is
disabled and the output voltage is dependent on modulation
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TABLE 3. Control parameters of the inverters.
index M . However, in the boost mode, M = 1.15(1 – DST )
for all inverters. A separate comparison with M kept at its
maximum value of 1 × 1.15 is also carried out for TBI. Like
CqSBI presented in [25], DqSBI with the conventional PWM
method in [20] cannot operate with a small ST duty cycle.
Thus, the high ST duty cycle of 0.36 and a low modulation
index are set in the experiment for DqSBI with the conven-
tional PWM method in [20]. In buck mode, DqSBI with the
conventional PWM method in [20] cannot operate because
the modulation index is very small. To operate in buck mode,
one of the diodes in the switched-boost network of DqSBI
with the conventional PWM method in [20] can be replaced
by an active switch as presented in [25].
Figs. 9(a)-9(g) compare the efficiency of the DqSBI with
improved PWM method, DqSBI with conventional PWM
method in [20], TBI, CqZSI, and DqZSI at different voltage
gains. In Figs. 9(a)-9(d) for buck mode, CqZSI, DqZSI, and
DqSBI with improved method operate without a ST state,
while the additional S0 switch in the TBI are fully turned
off. In buck mode, the efficiency of TBI is highest, while the
efficiency of DqSBI with improved method is slightly lower
than that of the TBI. The efficiency of DqSBI with improved
method is higher than that of CqZSI and DqZSI because a
lower power loss of the additional switch S0 and diode D1
is found in the switched-boost network of DqSBI. In boost
mode as shown in Figs. 9(e)-9(g), the efficiency of DqSBI
with improved method is respectively lower and higher than
that of TBI, the qZSIs, and DqSBI with conventional method
in [20]. Because a large ST duty cycle is used at the voltage
gain of 1.6 in DqSBI, CqZSI, and DqZSI, their efficiency is
substantially decreased and lower than that of TBI. However,
the efficiency of DqSBI with improved PWM method is still
higher than that of CqZSI, DqZSI, and DqSBI with conven-
tional PWM method in [20], as shown in Figs. 9(e)-9(g).
Note that, the efficiency of DqSBI with conventional PWM
method in [20] was added 4% and 2 % in Figs. 9(e) and 9(f),
respectively. In the case of using the same modulation index
as DqSBI, the efficiency of TBI is still higher than that of
the impedance source inverters. The efficiency of DqSBI with
conventional PWM method in [20] is lowest because the high
ST duty cycle of 0.36 is used to avoid unwanted operating
modes in DqSBI.
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M.-K. Nguyen et al.: DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and Its Comparative Evaluation
FIGURE 9. Efficiency comparison at (a) G = 0.85, (b) G = 0.92,
(c) G = 1.05, (d) G = 1.15, (e) G = 1.27, (f) G = 1.4, and (g) G = 1.6 and
(h) THD comparison.
FIGURE 10. Power loss distribution of DqSBI under the conventional
PWM method in [20] and improved PWM method at G = 1.6 and
Po = 1037 W.
Fig. 10 shows a calculated power loss of DqSBI under
the improved PWM method and conventional PWM method
in [20] for DqSBI when Vg = 200 V, Vo = 110 Vrms,
fs = 10 kHz and Po = 1037 W. The parameter for power
loss calculation is listed in Table 4. As shown in Fig. 10,
the inductor loss of DqSBI with improved PWM method is
higher than that of DqSBI with PWM method in [20]. This is
because the inductor current of DqSBI with improved PWM
method is higher than that with PWM method in [20]. Under
the improved PWM method, DqSBI uses the semiconductor
and capacitor with a low voltage rating. Thus, the power
loss of the capacitor, diodes and switches of the DqSBI with
improved PWM method is lower than that with conventional
PWM method in [20]. As shown in Fig. 10, the total power
VOLUME 8, 2020
TABLE 4. Parameters for power loss calculation.
TABLE 5. Voltage and current stresses at G = 1.27, Po = 910 W.
TABLE 6. Effect of Dead-Time to THD and efficiency of TBI at 910 W.
loss of DqSBI with improved PWM method is lower than that
with PWM method in [20].
Table 5 shows the experimental results of the voltage and
current stresses of four inverters when the voltage gain is
1.27 at a load power of 910 W. Compared to TBI, qZSIs
and DqSBI with PWM method in [20], DqSBI with improved
PWM method has many merits such as lower voltage stress
on capacitor and additional switch and lower inductor current
ripples. Because a low ST duty cycle is used in DqSBI with
improved PWM method, the peak-to-peak inductor current
ripple is very low. The inductor current ripple from the exper-
imental results matches with the theoretical analysis results
presented in Fig. 6(e). However, the current stress on the
inductor of DqSBI is high. This disadvantage of DqSBI with
the improved PWM method can be compensated by its low
inductor current ripple.
Fig. 9(h) shows the THD value of the output phase-A
current at different voltage gains. In this experiment, the dead-
time is set to 1 µs in TBI, while it is zero in DqSBI, CqZSI,
and DqZSI. As shown in Fig. 9(h), DqSBI, CqZSI, and DqZSI
offer a low THD of the output phase current, while a high
THD of the output phase current is found in TBI. The effect of
the dead-time in the output voltage quality and the efficiency
of TBI is shown in Table 6. Subsequently, the dead-time
value of TBI was changed from 1 µs to 5 µs, while it was
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 M.-K. Nguyen et al.: DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and Its Comparative Evaluation
zero for DqSBI, CqZSI, and DqZSI. When a large dead-time
is applied for safe requirement in TBI, a THD increment
and a slight efficiency reduction are found in TBI. In this
experiment, the load power is 910 W, while the voltage gain
is 1.27. The measured THD value and efficiency of DqSBI at
the zero dead-time are 1.16% and 96.1%, respectively.
VI. CONCLUSION
This paper presents a modified PWM control strategy for
DqSBI and its comparative evaluation. DqSBI with improved
PWM method has a lower voltage stress on devices and a
lower inductor current ripple but higher inductor and ST
current stresses when compared to DqSBI with conventional
PWM scheme. As a result, the power conversion efficiency of
DqSBI under modified PWM method is improved. Moreover,
DqSBI has one fewer inductor and one fewer capacitor, but it
uses one more diode and one more switch with a low voltage
rating when compared with qZSIs. As a result, the size and
weight of the Z-source network of DqSBI are reduced. The
comparative results show that the efficiency of DqSBI with
improved PWM method is higher than that of qZSIs over
a wider range of voltage gain. On the other hand, DqSBI
with improved PWM method has a lower efficiency and a
better output quality in comparison with TBI. The operating
principle and circuit analysis for DqSBI were shown. The
experimental results in both buck and boost modes were
presented. DqSBI with improved PWM method can be used
to replace the conventional qZSIs. Moreover, it can also play a
significant role in situations where requirement of miniboost
is essential.
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M.-K. Nguyen et al.: DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and Its Comparative Evaluation
MINH-KHAI NGUYEN (Senior Member, IEEE)
received the B.S. degree in electrical engineering
from the Ho Chi Minh City University of Tech-
nology, Ho Chi Minh City, Vietnam, in 2005, and
the M.S. and Ph.D. degrees in electrical engineer-
ing from Chonnam National University, Gwangju,
South Korea, in 2007 and 2010, respectively.
He was a Lecturer with the Ho Chi Minh City
University of Technology and Education, Ho Chi
Minh City, and an Assistant Professor with Chosun
University, Gwangju, South Korea. He is currently with the School of
Electrical Engineering and Robotics, Queensland University of Technology,
Australia. His current research interests include impedance-source inverters
and power converters for renewable energy systems. He had served as a Guest
Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS Special
Issue on the Impedance Source Converter Topologies and Applications. He is
currently an Associate Editor of the Journal of Power Electronics and the
International Journal of Power Electronics.
TRUONG-DUY DUONG received the B.S. degree
in electronic telecommunication engineering from
the Ho Chi Minh City University of Technol-
ogy and Education, Ho Chi Minh City, Vietnam,
in 2015, and the M.S. degree in electrical engineer-
ing from Chonnam National University, Gwangju,
South Korea, in 2018. He is currently pursuing
the Ph.D. degree with the Department of Elec-
trical Engineering, Chonnam National University,
Gwangju. His current research interests include the
topologies and control of dc-dc converters and dc-ac inverters.
YOUNG-CHEOL LIM (Member, IEEE) was born
in Chonnam, South Korea, in 1953. He received
the B.S. degree in electrical engineering from
Chonnam National University, Gwangju, South
Korea, in 1975, and the M.S. and Ph.D. degrees
from Korea University, Seoul, South Korea,
in 1977 and 1990, respectively.
In 1981, he became a Professor at Chonnam
National University, where he was the Director
of the Research Center for High-Quality Electric
Components and Systems, from 1998 to 2007. He is the coauthor of three
books. He has authored or coauthored more than 200 published technical
articles. His current research interests include power electronics, control
instruments, and neurofuzzy control. He was the President of the Korea
Institute of Power Electronics (KIPE), in 2009. He has been involved in var-
ious academic societies, such as the KIPE, the Korean Institute of Electrical
Engineers, and the Institute of Control, Automation, and Systems Engineers,
South Korea. He has received a number of awards, including the 2000 KIPE
Best Paper Award, and 2001 KIPE Academic Award.
VOLUME 8, 2020
JOON-HO CHOI (Member, IEEE) received the
B.S., M.S., and Ph.D. degrees in electrical engi-
neering from Soongsil University, Seoul, South
Korea, in 1996, 1998, and 2002, respectively.
Since 2003, he has been a Professor with Chonnam
National University, Gwangju, South Korea. His
research interests include operation and integra-
tion and control strategies of distributed genera-
tion, distribution automation, and modeling and
operation algorithms of the smart grid. He is a Life
Member of the KIEE and The Korean Institute of Illuminating and Electrical
Installation Engineers, and a Committee Member of IBS Korea. Since 2004,
he has been an Associate Editor of the Transactions of the KIEE.
D. MAHINDA VILATHGAMUWA (Fellow,
IEEE) received the B.Sc. degree in electrical
engineering from the University of Moratuwa,
Moratuwa, Sri Lanka, in 1985, and the Ph.D.
degree in electrical engineering from Cam-
bridge University, Cambridge, U.K., in 1993.
He joined the School of Electrical and Electronic
Engineering, Nanyang Technological University,
Singapore, in 1993. He is currently a Professor
of power engineering with the Queensland Uni-
versity of Technology, Brisbane, QLD, Australia. He has published over
275 research papers in refereed journals and conferences. His research
interests include wireless power, battery storage, power electronic converters,
electrical drives, and electromobility.
GEOFFREY R. WALKER (Member, IEEE)
received the B.E. and Ph.D. degrees from The
University of Queensland (UQ), Brisbane, QLD,
Australia, in 1990 and 1999, respectively. From
1998 to 2007, he was the Power Electronics
Lecturer with UQ. From 2008 to 2013, he was
a Senior Electrical Engineering Consultant with
Aurecon’s Transmission and Distribution Group,
Brisbane, across various areas, including rail trac-
tion, grounding studies, electricity transmission
planning, and renewable energy project design and review. In 2013, he joined
the Electrical Power Engineering Group, Queensland University of Tech-
nology, Brisbane, as an Associate Professor. His current research interests
include applying power electronics to applications in renewable energy
(especially photovoltaic), power systems, and electric vehicles.
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