Received 10 December 2022, accepted 21 December 2022, date of publication 4 January 2023, date of current version 10 January 2023.

Digital Object Identifier 10.1109/ACCESS.2023.3234040

A New Non-Isolated Active Quasi Z-Source

Multilevel Inverter With High Gain Boost
SOHRAB NADERI AND HASAN RASTEGAR
Department of Electrical Engineering, Amirkabir University of Technology, Tehran 15875-4413, Iran
Corresponding author: Hasan Rastegar (rastegar@aut.ac.ir)

ABSTRACT This paper proposes a three-level diode clamped active impedance source inverter (AIS-TLI)
based on the quasi Z-source inverter (qZSI). Apart from having minimal components and the inherent
benefits of three-level qZSIs, such as single-stage buck-boost capability, shoot-through (ST) immunity, and
continuity of input current, the proposed topology has a higher boost capability and excellent efficiency.
In addition, the inverter bridge has a higher modulation index, which improves the quality of the output
waveform and necessitates less inductance. The proposed topology provides common ground between input
and output terminals, which effectively eliminates leakage current in PV-powered single-phase systems.
This paper describes the different operating modes principle, dynamic analysis, steady-state analysis, and
parameter selection instructions for the proposed in-depth. Furthermore, the suggested inverter’s benefits
and limitations are compared to the traditional (q)ZSIs and some other AIS-TLIs. Finally, modeling and
experimental results are used to confirm the effectiveness of the suggested topology.

INDEX TERMS Active impedance source, common ground, modified quasi Z-source inverter, three-level
inverter.

I. INTRODUCTION in its future implementation, another topology based on the

Three-level diode-clamped inverters offer several advantages
versus traditional two-level voltage source inverters (VSIs),
including two times lower voltage stress on semiconductors,
higher power capacity, and lower switching losses that
result in higher switching frequency, better output waveform
quality, smaller filter size, reduced dv/dt, improved harmonic
performance, and the lack of a transformer required at the
level of the distribution voltage [1], [2], [3], [4], [5], [6].
Typically, an additional DC-DC step-up converter employed
to enhance the inverter voltage boosting capability. Refer-
ence [1] proposes a high step-up DC-DC converter based on
the Cockcroft-Walton (CW) voltage multiplier. The proposed
converter does not require a step-up transformer and is well
suited for DC generation systems with low input levels.
Reference [2] discusses a new three-level uninterruptible
power supply (UPS), which uses a push-pull boost circuit to
interface with the battery bank and the DC bus. Compactness
The associate editor coordinating the review of this manuscript and
approving it for publication was Javier Moreno-Valenzuela
Cuk-derived buck-boost method presented in [3].
Although [1], [2], [3] present some beneficial topologies
of traditional TL boost inverters, none of them can provide
shoot-through (ST) immunity. Hence, employing dead time
between the switching control signals is inevitable, but this
additional dead time distorts the output AC voltage and
degrades the inverter’s output waveform quality. To cover this
shortcoming, the impedance network solution is one of the
creative ideas which can be added to the three-level Neutral
point clamped inverter (TL-NPC).
Combining the Z-source or quasi-Z-source (q)ZSIs topo-
logical notion with the TL-NPC, [4], [5], [6], [7], [8], [9],
[10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20],
[21], [22], [23] yields a bunch of single-stage buck-boost
inverters. Some of the more common topologies, depicted
in Fig. 1. As an attempt to apply Z-source to the three-level
inverters, [4] combines a three-level inverter with a passive
impedance source (1PIS-TLI). Using this topology, [5]
suggests a new carrier-based modulation technique that
uses the effective large, medium, small, and zero vectors
. as opposed to the invalid vectors to produce constant

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 S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost
FIGURE 1. Topologies of some three-level impedance source Inverters
introduced in (a) [4], (b) [18], (c) [12], (d) [16], (e) [19], (f) [17].
common-mode voltage and leakage current suppression.
Since the traditional space vector modulation (SVM), is
unable to address the problem of neutral-point potential (NP)
balancing, [6] presents an improved SVM approach based on
modifying the time of the classic symmetric SVM.
Although the single LC-TLI has a minimal passive
component, it has several disadvantages, including high
voltage stress across switches and capacitors, significant
inrush current, and restricted boost factor. To mitigate some
of these drawbacks, [7] introduces another type of ST
immune, single-stage impedance source topology by using a
combination of a three-level inverter with two symmetrical
Z-source networks (2PIS-TLI). Trying to form another
topology with continuous input current characteristic, [8]
introduces a different 2PIS-TLI by combining two quasi
Z-source inverters.
In [9] and [10], some other 2PIS-TLI have been presented,
which can effectively decrease the stress voltage of the
Z-source capacitor and prevent starting inrush current,
especially in [9], thanks to applying level shifted and
SVM method, the neutral-point voltage will also balance.
As seen in Fig. 1, 2PIS-TLI utilizes a significant number of
passive elements, increasing the inverter’s weight, cost, and
volume. One way to reduce the number of passive elements
in traditional PIS topologies is incorporating some active
switches. Compared to PIS-TLIs, active impedance source
(AIS) inverters have a smaller inductance and capacitance
but implement more switches and diodes. In [11], a new
topology based on the inverse Watkins–Johnson topology is
introduced for low-power applications, where the topology
is called the switched boost inverter (SBI). Inspired by this
topology, [12] proposes a new topology for a three-phase
NPC inverter. The proposed topology offers all the features
of a multilevel quasi-Z-Source inverter with the benefit of
fewer passive parts. Since multilevel inverters contain more
power semiconductor components, the failure rate increases
that results lowering reliability; hence in [13] and [14], two
different SBI topologies are applied to a fault-tolerant TLI.
The main contribution of these topologies counted as high
2942
FIGURE 2. Proposed topology with reduced component count (AqZS-TLI),
with (a) single midpoint, (b) separated midpoint.
gain boost and operating safely even if the inverter’s power
switches are open-circuited. Enhancing voltage gain despite
lowering capacitor voltage stress, two new quasi switch boost
(qSB) based inverters have been presented in [15] and [16],
which their benefits achieved through the application of a
modified PWM control approach.
By examining these topologies, it is concluded that the
most shortcomings they share are the higher ST duty ratio,
lower modulation index availability, and lesser boosting
capabilities. Furthermore, the majority of these topologies
use two distinct impedance networks, which means deploying
single split or two independent DC voltage sources with many
other components. To address most of these shortcomings,
this paper proposes two new configurations of a single-stage
AIS-TLI. The proposed topologies have a single non-split
source with lower passive elements, which is based on the
qZSI definition, so they called active quasi Z-source neutral
point clamped (AqZS-NPC) inverter. Compared to [16], [17],
and [12], the proposed topologies save one switch. They
have higher voltage gain than traditional PIS-TLI and most
of AIS-TLIs, meaning a better DC-link utilization factor.
They also have a continuous input current and an adjustable
midpoint, which is beneficial for using in asymmetric NPCs.
II. CONFIGURATION OF THE PROPOSED TOPOLOGY
Fig. 2 illustrates the proposed inverter configuration. Both
topologies provide the same function. However, the second
one saves a diode. Since the topology with separated midpoint
is inconvenient for commercially available NPC modules,
in this paper, the study is made on the topology depicted in
Fig, 2(a).
This topology consists of two inductors (L1 , L2 ), two
capacitors (C1 , C2 ), three diodes (D1 , D2 , D3 ), an additional
active switch (Sd ), twelve switches (Sij , where i= 1 to 4 and
j=a, b, c) to form a three-phase three-level diode clamped
inverter bridge, and a three-phase filter (Lf , Cf ). Compared
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TABLE 1. Switching status and system output during different modes.

FIGURE 3. Equivalent circuits of the Proposed Topology.

(a) Non-shoot-through-d1 state, (b) Non-shoot-through-d2 state,
(c) Shoot-through state type 1, (d) Shoot-through state type 2.

to the traditional qZSI, additional passive and active elements

(D2 , D3 , Sd ), improve the specification of qZSI and make
the proposed configuration suitable for TL-NPC inverters.
Therefore, as discussed later, the obtained inverter will have
a better boost capability, resulting in a higher modulation
index with a lower ST duty ratio. Furthermore, unlike
traditional PIS-TLIs, the proposed inverter employs lower FIGURE 4. Steady State Waveforms of the proposed topology.
inductances as well as a single non-split DC source. It shares
a common ground between input and output terminals while
the qZS-based impedance network, ensures continuity of the simultaneously. As evidenced, in ST-mode, the voltage of Sd
DC source current. is zero and there is no change in the circuit function, if Sd
is turned on or off. Under these conditions, power is not
III. OPERATION PRINCIPLE OF THE SUGGESTED transferred to the load, and the input voltage source along
INVERTER with capacitor C2 energize inductor L1 , while capacitor C1
In this section, the operating principle of these two topologies discharges energy to the inductor L2 . The current flow across
is thoroughly outlined and discussed. For the sake of diodes (D1 , D2 ) reduced to zero, and all of them are reverse-
analysis simplicity, we assume that all the components of biased. The time interval of ST-mode is dst.Ts, where dst is
the AqZS-NPCs are ideal and all of the passive components the inverter bridge’s ST time duty ratio and Ts is the switching
are time-invariant, linear, and frequency-independent. The period. When KVL and KCL are applied to Fig. 3(c) or 3(d),
dead time intervals are short enough to be ignored, and the following equations are obtained:
the impedance network’s capacitances are large enough
to keep the capacitor’s voltage constant. The suggested 
diL1 
inverter can operate in two distinct states: non-ST and ST.
 L = Vin + Vc2 d
 1 dt  C1 Vc1 = −iL2

 
Fig. 3 depicts the suggested scheme’s corresponding circuits diL2 and dt (1)
L2 = Vc1 d
in these modes. As evidenced in Fig. 3(a) and 3(b), in non-ST 
 dt  C2 Vc2 = −iL1

dt

V̂PN = 0

mode, capacitor C1 is in charge or discharge mode depending
on the state of switch Sd . The switching states indicated in
Table 1, describe the operational principles of the suggested B. NON-SHOOT-TRHOUGH OPERATING MODE
AqZS-NPC. Fig. 4 indicates the proposed inverter’s steady- 1) d1-state
state voltage and current waveforms. As shown in Fig. 4, The operation principle of this mode is similar to that of
because of d2 implementation, the frequency of capacitors a traditional qZS impedance network. Fig. 3(a) depicts the
and L2 increased, which results in more smooth voltage and equivalent circuit for the d1-state. In this mode, there is
current waveforms of them respectively. no short circuit in the bridges, and switch Sd is turned off.
Diodes D1 , D2 , and D3 conducted, and Capacitor C1 is fed
A. SHOOT-TRHOUGH OPERATING MODE by Inductor L1 and the input source. In contrast, Inductor L2
Fig. 3(c) and 3(d) show the ST-mode. In this mode, all discharges energy to capacitor C2 . The time interval of this
of the power switches (Sij ) are turned on and conducted operating mode is d1·Ts. By applying KVL and KCL, for this

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 S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost

state, voltage and current relations can be extracted as The inverter’s inversion voltage gain G is defined as
diL1

V̂o

 L = Vin − Vc1 d
 1 dt  C1 Vc1 = iL1 − iPN G = M .B =

  (10)
diL2 and dt (2) Vin
L2 = −Vc2 dVc2

 dt 
 C2 = iL2 − iPN
dt where V̂o represents the peak load voltage, and M repre-

V̂PN = VC1 + VC2

sents the modulation index. Applied PWM control strategy
In which a simple current source IPN is used to represent determines the relationship between M and B. In this paper,
the external load. like [21], we use the simple boost control (SBC), so the
modulation index is limited by the ST duty ratio, as shown
2) d2-state below
Fig. 3(b) shows the equivalent circuit of the d2-state.
Throughout the active d2-state, switch Sd is turned on, and M ≤ 1 − dst (11)
like d1-state, there is no short circuit in the bridges. In this
mode, both diodes D1 and D2 are conducting while diode By considering the highest modulation index, the maxi-
D3 is reversed-biased. Capacitor C1 continues to charge mum peak load voltage can be extracted as
by inductor L1 and the input source while simultaneously
discharges energy to Inductor L2 . The time interval of this V̄PN V̂PN
V̂o_max = = (1 − dst ) (12)
operating mode is d2·Ts, where d2 is the time which Sd is 2 2
conducting. During non-shoot-through-d2 state, it is possible
where V̄PN is the mean voltage of the inverter DC-link.
to extract inductor voltages and capacitor currents as
Although in the proposed AqZS, capacitor voltages are
diL1

 different and depend on the values of d1 and dst , as it can be
 L = Vin − Vc1 d
 1 dt  C1 Vc1 = iL1 − iL2 − iPN

  seen in Fig. 4(a), the voltage of capacitor C1 should be equal
diL2 and dt to the half of V̂PN to make a suitable midpoint for the NPC
L2 = Vc1 dVc2

 dt 
 C2 = −iPN inverter. Therefore from (7), (8), and (12), the value of d1 for
dt

V̂PN = VC1 + VC2

a balanced DC-link AqZS-TLI should be as follow
(3)
1
d1 = (13)
C. BOOST FACTOR CALCULATION 2
Since each period is divided into three parts d1, d2, and dst, By having the above consideration, the voltage of capacitor
as it is evidenced from Fig. 4, we have C1 is set to half of the peak value of the DC-link, but the boost
d1 + d2 + dst = 1 (4) factor’s degree of freedom reduced to one, and the gain factor
is modified as
By considering the volt-second balance property of
inductors L1 and L2 , the average steady-state voltage of the V̂PN 2 1
B= = where 0 ≤ dst ≤ (14)
inductors over one switching period Ts is zero. Since each Vin 1 − 2dst 2
period is divided into three parts d1, d2, and dst, from (1) to
According to (14), although the proposed topology is only
(4), we have
made up of traditional qZS, a switch and extra one or two
VC1 (dst + d2 ) = d1 VC2 (5) diodes, it has a better boost factor than other topologies
(Vin + VC2 ) dst + (Vin − VC1 ) (d1 + d2 ) = 0 (6) which use two or more combinations of qZS. Furthermore,
as can be deduced from (7) and (14), the proposed AqZS
Considering (4)–(6), we can calculate the voltage of the offers an adjustable midpoint voltage. Equation (7) shows,
capacitors as follows by changing d1, without a necessity of changing dst or any
d1 1 − d1 active or passive devices, the midpoint voltage can change
VC1 = Vin and VC2 = Vin (7) easily, which shows the benefit of utilizing this topology
d1 − dst d1 − dst
for unbalanced NPC as well as fault-tolerant inverters.
As a consequence, in non-ST state, the maximum voltage Fig. 5 depicts the wide boosting ability of the suggested
of the DC-link is topology with two special cases, where the peak value of the
Vin midpoint is 1/3 and 1/2 of the peak value of the DC-link are
V̂PN = (8) highlighted.
d1 − dst
As a result, the suggested inverter’s boost factor B can be
IV. INDUCTOR AND CAPACITOR DESIGN
calculated as
Due to the operation principles, inductor currents are
0 ≤ dst ≤ 21

V̂PN 1 influenced by the ST state and rise rapidly. The current ripple
B= = where (9)
Vin d1 − dst dst ≤ d1 ≤ 1 − dst of inductors and the associated value of inductors can be

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S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost

calculated using (1-3), (7), and (9) as below.

 dst
 1iL1 =
 (Vin + Vc2 )
nfs L1 and
(d + d2 )
 1iL2 = st
 VC1
nfs L2

d st (1 − dst )
 L1 = Vin
(d1 − dst )nfs 1iL1




d1 (1 − d1 ) (15)
L2 = Vin



 (d1 − dst )nfs 1iL2 FIGURE 5. Block diagram of the proposed control method for DC-link

voltage and capacitor voltage balance.

where n is the number of shoot-through states that happen

in one switching period, substituting (13)-(14) into (15), the Substituting (13)-(14) into (19), the capacitance values of
inductance values of L1 and L2 can be designed as follows. C1 and C2 , are calculated as
4(1 − dst )2 dst

 2dst (1 − dst )
 L1 =
 Vin

 C 1 = Vin
(1 − 2d st )nfs 1iL1 (1 − 2d st )2 nfs 1V C1 RL


where

1 (1 − dst ) where
 L2 =
 Vin C2 = Vin
2(1 − 2dst )nfs 1iL2 (1 − 2d st ) nfs 1V C2 RL
2





dst


 1t L1 =
nfs
 
 dst
1t C1 =

dst + d2

(16)

1t L2 = nfs




 nfs d1 (20)
1t


 C2 =



 nfs

Unlike conventional qZS networks, as it is clear from
Fig. 3, in AqZS-NPC, the charging time of inductors are
different. Same as capacitors voltage, by applying the amp- V. CONTROL METHODOLOGY
second balance property of capacitors C1 and C2 , the average Fig. 5 depicts the block diagram of the dc-side control
current across inductors in steady-state is calculated as method, which performed independently of the ac-side. Two
follows. distinct control sections comprise the dc-side controller:
1 − dst 1 − dst the dc-link controller and the capacitor voltage balance
IL1 = IL2 = IPN and IPN = V̂PN (17)
d1 − dst RL controller. Although the suggested Aqzs has two independent
degrees of freedom, d1 and dst , for the special application of
where RL is the ac side circuit’s simplified equivalent, d1 = 0.5, it degrades to a single degree of freedom, allowing
DC load [20] and IPN is corresponding the average DC-link the dc-link voltage to be controlled by adjusting dst. Due
current. By these considerations, the average inductors’ to the shoot-through states, Aqzs-NPC’s dc-link voltage is a
current which is equal to the average current of the input pulse voltage waveform, which cannot be used as a feedback
source, can be derived as follows. variable. Since the dc-link peak voltage equals the sum of
(1 − dst )2 the capacitors’ voltage, dc-link voltage control realized by
IL1 = IL2 = Vin (18) controlling the voltage of capacitors. The Aqzs’ transfer
(d1 − dst )2 RL
function reveals that capacitors’ voltage, unlike inductors’
Further, concerning (1-3), (9) and (18), the capacitors’ current, cannot be directly controlled due to their non-
voltage ripple and therefore, the corresponding capacities can minimum phase feature. To determine the reference value of
be extractad as follows the inductor current, the computed dc-link voltage initially

IL2 dst compared to its reference value. Once an error generated,

 1V C1 = it fed into a PI controller, which then outputs the necessary
nfs C1



(I L2 − IPN )d1 inductor current reference value. The dst then formed by
1V C2 = passing the results of a comparison between the inductor’s


 nfs C2

 reference value and its actual current through a second PI
controller. Based on (4), the value of d2 is not considered an
(1 − dst )2 dst


 C 1 = Vin independent parameter. According to (7), changing dst does
(d1 − dst )2 nfs 1V C1 RL


 not affect on the voltage ratio of the capacitors, and these
(1 − d1 )(1 − dst )d1 (19) voltages remain equal under all circumstances; however,
C2 = Vin
(d )2
1V



 1 − d st nfs C2 RL if there is a slight difference between the voltages, it can be

adjusted using a PI controller. For this purpose, the capacitor

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 S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost
voltage difference is fed into the new controller, and 1d is
output, but only within certain bounds so as not to conflict
with dst. As a result, the corrected value of d2 is obtained.
For ac-side control, the proposed topology is compatible
with conventional voltage regulation techniques. Commonly,
d-q transformation used to convert fundamental frequency
components to dc components. This approach enables the use
of fewer and simpler PI compensators. One more possibility
is to use a stationary frame and design the appropriate
controller for it. Among the advantages of this technique is
its applicability in single-phase systems. This paper employs
the traditional controller in a stationary frame to achieve
the desired outcome of regulating the output voltage. In this
context, [24] provides more detail about the controller
parameter designing process.
VI. PERFORMANCE COMPARISON
This section compares the proposed topology with traditional
non-isolated high boost ZSIs, qZSIs, and qSBs to validate its
benefits
A. COMPARISON OF THE NUMBER OF ELEMENTS
Table 2, illustrates the number of elements in the impedance
network of the proposed topology and other three-level ZSI,
qZSI and qSB topologies. As is obvious, compared to the
others, the suggested topology has a less or equal number of
capacitors. However, although the same is true for inductors,
it has one more inductor compared to [22]. Although [22] has
a lower passive component, it has one more switch, making
it costly and more complex for control. Furthermore, the
proposed inverters, employs far fewer diodes than [17] and
along with [19] and [22], use a single DC source, while
the other inverters use two. Amongst all, only the proposed
topology offers the benefit of the common ground.
B. COMPARISON OF THE BOOST ABILITY
Comparing the relationship between the boost factors shows
the proposed topology has higher voltage gain through the
whole shoot-through duty cycle dst range than the others
except [16] and [17], which have better boost ability, but
they suffer from discontinuity of input current. The boost
ability and gain comparison of the proposed topologies with
other TL boost inverters are illustrated in Fig. 6(a) and 6(b)
respectively.
C. COMPARISON OF THE DC-LINK UTILIZATION
Compared to the traditional impedance source three-level
inverters, AqZS-NPC provided better DC-link utilization.
To compare fairly, the inverter topologies’ input and output
voltages, as well as their power ratings, must be identical.
As shown in Table 2, when the same shoot-through duty
cycle is used, the voltage gain of the suggested inverter is
higher than the values proposed in [19]. Suppose [19] has a
ST duty cycle of dst1 . In that case, for a proper boost factor,
the suggested inverter’s ST duty cycle should be (4dst1 -1)/2,
which is less than dst1 and results in a higher utilization factor
2946
for the proposed topology. This feature can be formulated as
below.
1 − dst2 1 − 4d st1
α= = >1 (21)
1 − dst1 2(1 − dst1 )
D. COMPARISON OF THE CAPACITOR AND INDUCTOR
VALUES
In order to compare the value of capacitors and inductors,
in addition to the proper input voltage, proper DC-link
utilization condition should be taken into account. To provide
the exact DC-link utilization, if the ST time duration of [12]
is dst1 , the equivalent value in the suggested topology would
be 3/2 -1/2dst1 , which is lower than dst1 . This causes the
proposed inverter’s peak-to-peak inductor current to be less
than that of [12], implying that the inductor size of the
proposed inverter can be reduced. Repeating the same process
for [16] with the assumption of d0=0.6, the equivalent
value in the suggested topology would be 4/3 -1/3dst1 ,
which proves that the inductances of the proposed topology
is higher than that in [16]. Although the current ripple
in [16] is less than that of proposed, Fig. 6(e) shows the
inductor current is much higher, making it much more
costly. Fig. 6(f) compares the inductor current ripple of
all different topologies. As indicated, the current ripple in
Aqzs is less than all of them except [16] and portions
of [19], but [16] has higher current rate and [19] uses
two more inductor which makes them more expensive than
the proposed. Continuing this procedure to compare the
capacitor values reveals that compared to [12], the proposed
topology has smaller capacitors. Moreover, although in [19]
the values of capacitors C1 and C4 are nearly half the value
of Aqzs capacitors, C2 and C3 have the same value as the
proposed capacitors. Given that [19] uses two more capacitors
than Aqzs, a general comparison reveals that the introduced
topology uses lower capacitor values overall.
E. COMPARISON OF THE CURRENT AND VOLTAGE STRESS
In general, the capacitors’ voltage stress of the proposed
topology are not equal to each other but for d1=1/2, both of
them have the same voltage. Fig. 6(c) compares the capacitor
voltage stress versus gain for the proposed Aqzs-NPC and
the other topologies. As Fig. 6(c) shows, the Aqzs-NPC is
superior in capacitor voltage stress compared to [16], [17],
and [19], but it has lower voltage stress than [4], [12], [22],
and [23] which makes the proposed reasonable. Similar to
the capacitors, Fig. 6(d) shows the stress voltage comparison
results for diodes. Evidently, for the proposed Aqzs-NPC,
although diodes d1 and d2 have the same stress voltage, the
stress voltage of diode d3 is different. For the same condition,
the voltage stress of d1 and d2 is higher than [16] and [17]
while they are lower than the others. This is even though diode
d3 has a much higher voltage and its voltage is only lower
than [23].
Fig. 6(e) compares the current stress of inductors. As indi-
cated, all topologies have the same current stress except
for [17] and [16], which have lower and higher current stress
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TABLE 2. Comparison of the proposed topology with some other inverters.
respectively. This means although the proposed Aqzs-NPC
uses lower values of capacitors and inductors, it still has an
acceptable voltage and current stress compared to the other
alternating topologies.
Fig. 6(g) and 6(h) compares the voltage and current stress
of extra switch respectively. As shown, despite the fact that
it has a higher voltage stress than [16] and [17], but it has
only one extra switch and its current is much lower than them,
which makes the total loss of the switches not significantly
different.
F. COMPARISON OF THE EFFICIENCY
For efficiency comparison, it assumed that the values of
components and variables are identical across all topologies.
Additionally, the type and model of diodes and IGBT
switches (if utilized) regarded as identical. Each topology’s
efficiency calculated in relation to the overall voltage gain.
As depicted in Fig. 7(a), for the special case of d1=0.5, the
suggested Aqzs-NPC is more efficient than the topologies
provided in [16], [17], and [19], but it is comparable
to [4], [12], and [23] with a minor difference. The topology
given in [22] is the most efficient, but includes more diodes
and active parts. As previously stated, the presented topology
is applicable to numerous applications, including asymmetric
NPCs. In such cases, the capacitor voltages do not have to be
identical, and d1 can have a variety of values. Fig. 7(b) shows
VOLUME 11, 2023
the comparison of all topologies efficiency for d1 = 0.3.
As illustrated, the proposed topology is the most efficient in
this case, especially for larger gains.
VII. SIMULATION AND EXPERIMENTAL RESULTS
In verify the presented theoretical analysis, the performance
of the proposed topology is demonstrated with simulation
and experimental results. The simulations are done with
MATLAB Simulink, and the experimental validation is
carried out by building a laboratory prototype. We assume
that the conduct resistance of switches is 45 m. S1j and S4j
(j = a, b, or c) have a 2 V saturation voltage, whereas the
drop voltage of diodes D1 , D2 , and D3 is 1.5V. A variable DC
supply of 50 ∼ 150 V is also included, and the Aqzs-TLI’s
switching frequency is set to 20 kHz. Table 3 illustrates the
circuit parameters used for simulation.
A. SIMULATION RESULTS
The results of current and voltage waveforms shown in Fig. 8,
where a resistance of 15 per phase used at the inverter’s
output. Moreover, the input voltage is set to 90 volts, and the
output peak AC voltage of each phase (Vm) across the load
considered 155 Volts (110 Volts r.m.s.).
According to equation (14), the required shoot-through
duty ratio (dst ) and modulation index (M) for the above
specification can be set to 0.32 and 0.62, respectively,
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 S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost
FIGURE 6. (a) Boosting ability of the proposed AqZS-NPC inverter,
Topologies comparison of: (b) gain voltage, (c) capacitors stress voltage,
(d) diode stress voltage, (e) inductor stress voltage and (f) peak-peak
inductor current fluctuation, (g) extra switch stress voltage and (h) extra
switch stress current.
FIGURE 7. Topologies efficiency comparison for: (a) d1=0.5, (b) d1=0.3.
resulting in a peak DC-link voltage of 500 Volts. As shown
in Fig. 8(a), the voltage across capacitors is well balanced.
BothVC1 and VC2 are observed to be the same as the
theoretical value (i.e., 250 Volts) with a negligible ripple. The
currents of both inductors are approximately identical. The
average currents of inductors for IL1 and IL2 are 15.7 and
15.5 A, respectively, which is close to the value obtained from
the theoretical. The peak midpoint voltage is half of the peak
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TABLE 3. System specification.
FIGURE 8. Simulation results with a resistive load of 1400 w when
Vin=90; dst=0.32 and M=0.62.
voltage of the DC-link. Exactly as expected, diodes D1 , D2
are forward biased during all states except ST-state. However,
diode D3 is reverse biased during ST-state and d2-state.
To verify the performance of the proposed topologies in the
dynamic states, the input voltage, and the load increased by
step. Fig. 9 shows the operation of the inverter in this mode.
As shown in Fig. 9(a), input voltage increases at 0.2 and
0.4 seconds from 60 V to 100 V and then 140 V, respectively.
In addition, the load increases from 1000 w to 1400 w at
0.3 seconds and decreases to 1000 again at 0.5. Fig. 9 shows
that the inverter is stable despite changes in input voltage
and output load, and the output waveform agrees with the
theoretical results.
B. EXPERIMENTAL RESULTS
To validate the simulation results of the proposed topology,
a laboratory prototype is developed and evaluated by
connecting a resistive load. Fig. 10 depicts a photo of the
hardware setup, including the inverter circuit, DSP controller,
Measuring unit, driver board, output filter, and a controllable
1.4-kVA load. For more compatibility and coordination, three
VOLUME 11, 2023
S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost
FIGURE 9. Simulation results with a step-change in input voltage and the
load. (a), dst, d2, and IL1 variation due to input and load step change,
(b) capacitor voltage and dc-link and midpoint voltage change, (c) load’s
current and voltage, and phase to neutral and line to line unfiltered
output voltage for 1400w resistive load when Vin=90; dst=0.32 and
M=0.62.
FIGURE 10. Prototype of the AqZS-NPC system.
F3L50R06W1E3_B11 IGBT modules used in favor of the
NPC switches, an FP40R12KT3 module are used in the role
of D1 , D2 , D3 , and an additional switch, Sd .
PWM control signals are generated using a DSP
TMS320F28335 controller, which has a triangle frequency
of 20kHz. The drive circuit uses the Texas Instrument’s
ISO5852 smart and high-performance gate driver IC with a
VOLUME 11, 2023
FIGURE 11. Experimental results with a resistive load of 1400 w when
Vin=60; dst=0.38, d2=0.12. (a) inductors voltage (VL1 , VL2 ), (b) DC-link
voltage (VPN ), (c) diodes voltage (VD1 , VD2 ), (d) additional switch and
diode voltage (Vsd, VD3 ), (e) capacitor voltage (VC1 ), (f) the AC part of
inductors current (IL1 , IL2 ).
very high common-mode immunity of 100 kV/us. The duty
cycle of the ST is between [0.05 and 0.4].
Fig. 11 illustrates the experimental results of inductors
voltage (VL1 , VL2 ), DC-link voltage (VPN ), diodes voltage
(VD1 and VD2 ), additional switch and D3 voltage (Vsd and
VD3 ), capacitor voltage (VC1 ), inductors current (IL1 , IL2 ), for
input voltage of 60 volts. As shown in Fig. 11(e), the voltage
of C1 is half of the V̂PN , but there are a small differences
with the simulation, which are related to parasitic found
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 S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost

FIGURE 12. Experimental results of the dynamic response of the

AqZS-NPC when Vin=140 and load changes from 1000 to 1400 w;
(a) capacitor voltage (VC1 , VC2 ), (b) DC-link voltage (VPN ), (c) Inductor
current (IL1 ) (d) Output line voltage (VRS ) before and after filter,
(e) Output current (VA ). FIGURE 13. Experimental results of the dynamic response of the
AqZS-NPC when output power is 1000w and input voltage changes from
90V to 140V; (a) capacitor voltage (VC1 , VC2 ), (b) DC-link voltage (VPN ),
in the experiment. The current and voltage pattern of all (c) Inductor current (IL1 ) (d) Output line voltage (VRS ), (e) Output
components agree with simulation results. However, spikes current (VA ).
are seen in the voltage and currents of AqZS components,
which should be lowered by designing an appropriate snubber
circuit.
Fig. 12 depicts the experimental waveform of the output
voltages before and after the LC filter, the input and output
current, and the voltages of two capacitors during the
transient state when the load power increases from 1000 w
to 1400 w while the input voltage and dc-link voltage are
set to 140 V and 500 V, respectively. In accordance with
the applied control policy, the voltage of the capacitors
remains constant. Since the input voltage and dc-link have
not changed, there is no need for a significant change in
dst; however, the load current increases as a result of the
FIGURE 14. Experimental results of efficiency in different output power.
increasing load.
Fig. 13 depicts the dynamic response of the system when
the input voltage stepped from 100 V to 140 V and the load The voltage of the capacitors stays the same, so the voltage
remains constant at 1000 w. As expected, since the dc-link of the neutral point remains constant and the experimental
voltage is set to 500 V, the values of dst and d2 decreased and results are found to be consistent with the computational
increased, respectively, when the input voltage stepped up. results.

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S. Naderi, H. Rastegar: New Non-Isolated Active Quasi Z-Source Multilevel Inverter With High Gain Boost
Fig. 14 shows the measured efficiency of AqZS-NPC in
terms of output power. Due to the lack of optimal components
employed in the construction of the prototype, the measured
efficiency is slightly different from the theoretical results.
VIII. CONCLUSION
This paper introduced a new active quasi Z-source three-level
NPC inverter with a lower component count. The suggested
inverter presented in two alternative configurations, all of
which offer the same results. Besides having outstanding
features such as power conversion in single-stage, ST immu-
nity, continuous input current, and improved modulation
index, the main contributions of proposed inverters are lower
component count, enhanced voltage gain, and require smaller
inductances. The simulation and experimental prototype
developed to confirm the feasibility and reliability of the
proposed topology. The hardware results corroborated the
simulation and analytical results.
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SOHRAB NADERI received the B.S. degree in
electronic engineering from Shiraz University,
Shiraz, Iran, in 2000, and the M.S. degree in
electrical engineering from the Ferdowsi Univer-
sity of Mashhad, Mashhad, Iran, in 2002. He is
currently pursuing the Ph.D. degree in power
electronics for renewable energy applications with
the Amirkabir University of Technology, Tehran,
Iran. From 2002 to 2009, he was a Research
Engineer in the field of oil and gas with Advanced
Technology. Since 2009, he has been participated in different power
system and power electronic projects in the field of renewable energy,
metro system, and railways electrification. Since 2007, he has also been
a Consultant of many famous industry companies for various industrial
concerns. His research interests include power converters, renewable energy
systems, control techniques, electric vehicles, and SIC modules. He received
several awards and honors, including the Outstanding Students Award from
Ferdowsi University.
HASAN RASTEGAR was born in Gorgan, in 1962.
He received the B.Sc., M.Sc., and Ph.D. degrees
in electrical engineering from the Amirkabir Uni-
versity of Technology, Tehran, Iran, in 1987, 1989,
and 1998, respectively. He is currently a Professor
with the Amirkabir University of Technology.
He has published many papers in journals and
conferences. His research interests include power
system control, application of computational intel-
ligence in power systems, simulation and analysis
of power systems, and renewable energy.
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