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Enhanced-Boost Z-Source Inverters with
Switched Z-Impedance
H. Fathi Kivi, and H. Madadi Kojabadi, Member, IEEE
Abstract—This research work proposes a new topology for
Enhanced-boost Z-source inverter with combined two Z-
impedance networks. By two Z-impedance networks and low
shoot-through duty cycle, the proposed inverter produces high
output voltage gain. In traditional Z-source inverters for high
boosting voltage, low modulation index is required, so under
these conditions output voltage will have low quality with high
total harmonic distortion. Compared with the conventional high-
boost ZSI topologies, the proposed inverter uses shorter shoot-
through duration and larger modulation index to improve the
output waveform quality. Comparison between the proposed
topology and previously proposed schemes in terms of inductor
numbers, voltage and current stresses on elements, sizes of
inductors and capacitors, efficiency, and SDP factors of diodes,
has been made and the results verify the priority of the proposed
topology. The operating principle of the proposed topology is
analyzed in detail. Both simulation and experimental results
verify the high performance of the proposed inverter.
Index Terms—Buck-boost, impedance network, high-boost, Z-
source inverter, total harmonic distortion
I. INTRODUCTION
T RADITIONALvoltage source inverter (VSI) and current
source inverter (CSI) are known to have only buck or
boost conversion ability, respectively. For applications where
both voltage buck and boost operating capabilities are needed,
before VSI an additional dc–dc converter is required, that this
two stage configuration, increases the cost and reduces the
efficiency of the system. In addition, shoot-through problem in
VSI and open-circuit problem in CSI is the main concern in
the system’s reliability. Structure proposed for overcome the
above mentioned problems was Z-source inverter (ZSI) [1],
that, unlike the VSI and CSI inverters, with single-stage power
conversion, have buck–boost voltage abilities. Thus, buck–
boost capability is achieved with a single-stage power
conversion. This unique feature also increases the immunity of
the inverters to the EMI noises, which may cause uncontrolled
shoot-zero (or open circuit) to destroy the conventional VSIs
and CSIs, respectively. Meanwhile, in ZSI, both switches in a
leg can be turned-on simultaneously to eliminate dead-time
and to improve the quality of output waveform. Because of
these flexibilities, Z-source inverters have already been
investigated for a number of applications such as; motor
drives [2], electric vehicles [3], distributed generation [4],
Manuscript received November 22, 2014; revised March 18, 2015 and June
9, 2015; accepted July 25, 2015.
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photovoltaic generation [5, 6] , uninterruptible power supplies
(UPS) [7], and fuel cell converters [8]. Also others have
focused on their modeling and control [9, 10], operating
modes [11], and new Z-network topologies [12-25].
Despite these advantages, the Z-source inverter has some
obvious drawbacks, such as discrete input current which
would leads to low utilization and also lifetime damage of the
dc source, large voltage stress across the switches and
capacitors, huge inrush current and lower modulation index
for high gain output voltage that would leads to poor output
voltage waveform quality. With the introduction of quasi-ZSIs
[12], the classical ZSI’s shortcomings were solved. This
topology improves the input current profiles and reduces the
passive component ratings.
In recent years, new topologies are introduced for high-boost
Z-source inverter. In order to achieve high DC-link voltage
with low shoot-through duty cycle the new topologies have
added inductors, capacitors and diodes to the Z-impedance
network. For high-boost Z-source inverter can be pointed to
continuous-current diode/capacitor-assisted extended-boost
quasi-ZSIs [13], switched-inductor (SL) Z-source/quasi-ZSIs
[14, 15], generalized multi-cell SL ZSI [16], tapped-inductor
(TL) Z-source inverters [17], trans-ZSI [18-23], alternate-
cascading technique presented in [24] and the alternate-
cascaded SL and TL Z-source inverters in [25].
The concept of extending the quasi-ZSI gain without
increasing the number of switches was proposed by [13].
These new converter topologies are commonly referred to as
the extended boost quasi-ZSI or cascaded quasi-ZSIand could
be generally classified as capacitor assisted and diode assisted
topologies. These new topologies introduce some excellent
features such as low or no inrush current during start up, low-
common mode noise, and continuous input current. In [14,
15], for high boosting capability a switched inductor (SL)
voltage-type Z-source inverter was proposed, where the
inductors, , , were replaced by two SL cells assembled
using inductors and diodes. The switched-capacitor cell (SC)
and inductor cell have also been applied to the current-type Z-
source inverter, as demonstrated in [16].
For even greater voltage boosting, the trend subsequently
drifted toward using two-winding coupled inductors, named
tapped-inductor(TL) Z-source inverter [17], and or
transformers, named trans-ZSI [18-23]. The authors of [18,
19] introduced coupled transformers in place of the inductors
found in the original Z-source network. The inverter voltage
gain can then be raised by increasing the transformer turns
ratio, but at the expenses of chopping input current even if the
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quasi or embedded variants are used. In order to smooth the
input current a number of asymmetrical transformer-based
embedded Z-source (EZ-source in short) inverters are
proposed [20], whose gain is higher and input current is
smoother.
In order to reduce the voltage stress on switches and passive
components in greater high boosting, cascaded multi-cell
trans-z-source inverters proposed in [21], where multiple
small transformers are used to replace a high power rating
transformer. In comparison with the non-cascaded inverter, the
cascaded multi-cell trans-ZSI has higher efficiency with lower
component stresses. The common feature of cascaded
topologies is distribution of the stresses on passive
components such as the inductor, transformer, capacitor and
diode. Combined switched-inductor and transformer cells Z-
source inverter has been presented in [22]. By changing the
transformer turns ratio and the number of SL cells, the
proposed inverter can produce very high output voltage gains.
With the same number of transformers and turn ratios, the
proposed inverter can produce the same output voltage gains
as other high-boost ZSIs by using a higher modulation index.
The significant feature of trans-ZSI is the use of transformer
turns ratio for even higher voltage boosting. However, during
switching, any lack in magnetic coupling of the transformers
will definitely cause huge transient over voltages, which,
would damage the active switches. Higher voltage boosting
are the flow of high currents and appearance of high voltages
across some components. Such stresses, if not lowered, will
lead to shorter life span and unexpected damages, which are
avoided by proposing the alternate-cascading technique
presented in [24] and the alternate-cascaded SL and TL Z-
source inverters in [25].
This paper presents a family of high-boost ZSI based on
switched Z-impedance. The proposed Z-source inverter can
produce very high output voltage gains. With the same duty
ratio the proposed topology produces higher boost factor than
diode assisted QZSI, alternate cascaded ZSI, and SL-ZSI. In
other word the new topology requires lower duty ratio for the
same boosting voltage. The proposed inverter has lower
voltage stress across active switching devices compared to
diode assisted QZSI, alternate cascaded ZSI, SL-ZSI, and
conventional ZSIs. Even though the number of inductors in
proposed scheme is higher than those in alternate cascaded
ZSI (N = 2), but the inductor size is smaller in proposed
method and so cheaper than those in alternate cascaded ZSI (N
= 2, 3). Meanwhile, in proposed method the diodes has less
SDP factor in compare to alternate cascaded ZSI (N = 3) and
so this leads to less expensive inverter.
II. PROPOSED Z-SOURCE INVERTER WITH SWITCHED
Z-IMPEDANCE
Boost factor B for traditional Z-source inverter can be
expressed as follows [1]:
1 1
1 capacitors
1 2 / 1 2
where is the interval of the shoot-through state during the
switching period T and D is the duty cycle of shoot-through. A
switched inductor (SL) voltage-type Z-source inverter is
shown in Fig. 1, where the inductive blocks were replaced by
two SL cells assembled using inductors and diodes. Since the
dc-link voltage appearing across the external ac loads during a
non-shoot-through state, is the sum of voltages across the two
SL cells and input source, series connection of and will
Fig. 1. SL-Z-source inverter.
Fig. 2. Proposed Z-source inverter with switched Z-impedance.
boost it further. The boost factor B for SL based ZSI can be
expressed as follows:
1
2
1 3
Higher gain can be achieved by using a new form of SL
cells. As illustrated in Fig. 2, the proposed Z-source inverter
consists of four inductors ( , , and ), four capacitors
( , , and ), and four diodes ( , , and ). The
combination of , and , is the first Z-Impedance
network, , and , is second Z-Impedance network.
A. Operation Principles
The operation principles of the proposed inverter are similar
to those of the classical Z-source inverter. Therefore, the state
of Z-impedance network in two operating states will be
discussed.
Shoot-through state: In the shoot-through state, as shown in
Fig. 3(a), dc-link is short circuited. In order to reduce
conducting losses of switches and also symmetrical heating
distribution between them usually three legs are turn on
and
simultaneously. Inductors are paralleled
with and , respectively, so and will turn on, and
the and reverse biased and will turn off during this state.
The sum of two capacitors’ voltage of , , is greater
! "
than supply voltage ( ! ) so the is reverse
biased.The inductors , , and are charged by
, , and in parallel, respectively. The
inductors’ current linearly increasing, assuming that the
capacitors’ voltage are kept constant during this state.

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Non-shoot-through state: In this state, the inverter bridge is in 1

! 12
active state. During the non-shoot-through state as shown in 2 4 1
Fig. 3(b), , and are on, and , are off due to From Fig. 3(b) also we have
reversed voltage of and across them, capacitors $ '()) ! 0 13
, , and are charged and energy required by main Substituting (8) and (12) into (13), the peak dc-link voltage
circuit is injected by the inductors , , and and dc 5 can be expressed as:
1
voltage source. Therefore, by using more inductors the more 5 . 14
energy will be transferred, as a result, higher gain will be 2 4 1
obtained. In this state the voltage polarity of inductors will be where
1
15
reversed thus the inductors’ current linearly decreases,
assuming that the capacitors’ voltage are kept constant during 2 4 1
this state. If the number of inductors in series are more, the is the boost factor.
energy that transfers from source to load will be larger and this The peak ac output phase voltage of the inverter can be
will lead to higher boosting ratio. expressed as:

:
9
B. Boost Ability Study 57 8. ;< 16
Assuming that the all capacitors, , , and have the where M is the modulation index. Substituting (14) into (16)
same capacitance, and also sufficiently large, two networks we obtain
become symmetrical and in this case we will have:
! ! 3
! ! 4
In Shoot-through state:
From Fig.3(a), we can notice that, is parallel with , is
parallel with , is parallel with , and is parallel with
, and so we can write:
$ $ ! ! 5
$ $ ! ! 6
In steady state the average voltage of the inductors in
switching period is zero, so by applying the volt-second Fig. 3. Equivalent circuits, (a) Shoot-through zero state, (b) Non-
shoot-through state.
balance principle to inductors we have [15, 29]:

D $ (1- D) $ '()) = 0 57 8. . =. 17
2 2
D $ 1 $ '()) 0 where
where $ '()) and $ '()) are the corresponding voltage = 8. 0~∞ 18
across and during Non-shoot through state. So, the is buck–boost factor. The buck–boost factor (=) can
inductors’ voltage in Non-shoot-through state can be written becontrolled by changing D and M. Duty cycle of shoot-
as [15, 29]:
D
through, D, is limited by modulation index by the following
V, '-.. V, '-.. V 7 relation:
1 D 0 D@1 8 19
$ '()) $ '()) ! 8 The boost factor from (15) indicates that when D is between
1
0 and 0.29, B varies in (1, ∞). However, the infinite value of B
$ '()) ! ! 0 9 is not accessible due to parasitic effects of physical
The inductors' current 4$ and 4$ increase linearly during components. Even if a large value of D is used to produce the
Shoot through and decrease linearly during Non-shoot through high boost gain, the modulation index must be small as
state. The corresponding voltages across are equal to Vc1 indicated in (19). However, low modulation index, M will
and -(Vc3-Vc1) and across are equal to Vc3 and -(Vdc– result in poorer spectral performances and low THD. Small M
Vc3). So, the inductors' voltage is instantaneous square is generally not preferred since it leads to low output
waveform, with positive constant value at Shoot-through state, waveform quality and high power losses due to lower order
and negative constant value at Non-shoot-through state. harmonics at output waveforms.
By using (7), and (9), the can be expressed as: Compared with conventional ZSI with the same modulation
! 1 ! 10 index, the proposed ZSI provides higher voltage boosting.
From Fig. 3(b) we have: Thus, for the same voltage conversion ratio, this ZSI uses a
$ '()) $ '()) ! 11 higher modulation index M to improve the output voltage
Using (3), (7), (8), (10), and (11) the voltage across capacitor quality. So with very low shoot-through duty ratio, D, very
can be further expressed as: high value of M is obtainable.

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C. Inductor and Capacitor Design Topologies can be compared based on, output voltage gain,
In shoot through the inductors will be charged by capacitors. passive components used and voltage stress on active and
So we will have: passive components. Fig. 4 shows that with the same duty
4$ (20) ratio the proposed topology produces higher boost factor than
$ $ ! !
A diode assisted QZSI, alternate cascaded ZSI, conventional
4$ (21) ZSI, and SL-ZSI. In other word the new topology requires
$ $ ! !
A lower duty ratio for the same boosting voltage. Fig. 5 shows
So the inductors can be designed by:
the output voltage gain against modulation index for five
1
topologies. In order to produce the same output voltage gain,
B (22)
the proposed topology uses higher modulation index than
∆4$ DBE 2 4 1
1
other two traditional methods. As a result, the output
B (23)
waveform has high quality with low THD.
∆4$ DBE 2 4 1
Table I shows the comparison of passive components among
whereDBE is the number of shoot-through states in one switching
five topologies. Even though the proposed topology has higher
period. For the constant value of B , , ∆4$ DBE , the
coefficient KI can be defined as:
boost factor but it requires the same or less numbers of
1 (24) inductors or diodes in compare to diode assisted QZSI and
DF traditional SL-ZSI.
2 4 1
1 (25) Voltage stress across switches can be defined as the ratio of
DF the peak DC-link voltage to =.
2 4 1 [22]. As shown in Fig.
In shoot through the capacitors’ current are equal to inductors’ 6(a), for the same buck-boost factor, the proposed inverter has
current so the capacitors can be calculated as: a lower voltage stress across the active devices than other four
B 4$ G9 (26) ZSI topologies. Lower stress on switches will lead to
∆ ! DBE inexpensive devices and finally cheaper inverter. The
B 4$ G9 (27) capacitor voltage stress is the ratio of capacitor voltage to
∆ ! DBE =. [22].Fig. 6(b) shows that the capacitor voltage stress for
The average capacitor current is zero in one period so based on our proposed inverter is higher than the same value in diode
Fig. 3(b) we have: assisted QZSI, alternate cascaded ZSI, and SL-ZSI. Also, the
4$ G9 1 4$ G9 (28) maximum voltage stress on a diode can be defined as the ratio
B 1 4$ G9 (29) of the maximum voltage stress on the diode to =. [22], that
∆ ! DBE it is shown in Fig. 6(c). This fact suggests that in the proposed
For the constant value of B , 4$ G9 , ∆ ! DBE , the coefficient ZSI, maximum voltage stresses on diodes are less than those
KC will be defined as: in the conventional ZSI, and alternate cascaded ZSI. However,
D (30) this value for our circuit for some diodes is higher than the
D 1 (31) same value in diode assisted QZSI, and SL-ZSI.
It can be seen that the capacitance has direct relation with The coefficient of KI versus buck-boost factor is shown in
average inductor current, so the more capacitor (inductor) Fig. 7. According to (22), (23), (24), and (25) the KI is a good
current will lead to higher capacitor size as well as increased measure for inductor volume for the same output power. From
cost. this figure it can be seen that the proposed scheme has lower
inductor volume (inductance) in compare to conventional ZSI
E. Intrinsic Components Effect on Boost Factor and SL-ZSI methods. This is due to the fact that the proposed
By considering the intrinsic components of inductors and scheme requires smaller D in order to produce high boost
capacitors, the (15) can be modified as: factor, B. Smaller D will result in lower inductances. However
due to lower capacitor voltage in alternate-cascaded ZSI it has
1 (32) lower inductance than our proposed method. The coefficient
IJK;L<MNO ' VW XYVZ '[VX
2 4 1 H4 \ of KC versus buck-boost factor is shown in Fig. 8. According
PQRSTNU; VZ ' VX
to (26), (27), (28), (29), (30), and (31), the KC is powerful tool
I<U]U<JMNO VW '^VZ X[V' V
.. 4 for capacitor volume (capacitance) in Z-source inverters. As
PQRSTNU; VZ ' VX 'V
indicated in Fig. 8, for the same buck-boost factor, the
where _ ` abI , and _ 7c7 abI are the inductor and capacitor
proposed scheme has lower capacitance than those of alternate
cascaded ZSI (N=2, 3), conventional ZSI, and SL-ZSI
series resistances, respectively, and def'gb7 is the
topologies. This is due to the fact that the proposed inverter
equivalent resistance of the load at dc-link side. It can be seen has a high boost factor with lower D.
that with higher values of series resistances of inductors and The SDP of a switching device is expressed as the product
capacitors the boost factor reduces. of voltage stress and current stress. The total SDP of an
inverter system is defined as the aggregate of SDP of all the
III. THEORETICAL COMPARISON BETWEEN VARIOUS switching devices used in the circuit. Total SDP is a measure
TOPOLOGIES of the total semiconductor device requirement, thus an

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important cost indicator of an inverter system. The definitions
are summarized as follows [26-27]:
u oB}
hA i jkl_ ml n o n o7p q r FrUsQOUtQ
rv
and
u
hA i wl x n o n ocy q
r Fr]QUz
rv
where N is the number of active devices used,Fr_7peI7|e , and
Fr_ce7y are the average and peak current through the device,
respectively and r is the peak voltage induced on the
devices. The average and peak SDPs (for diodes) of proposed
ZSI are:
n o7p ob`a 1 2 2 1 35
1 and conduction loss. Due to small inductor current ripples, the
n ocy ob`a 2 36
1 core loss is very small in compare to total power loss of
The n o7p , and n ocy factors of proposed scheme and
alternate cascaded ZSI (N = 2, 3) have been shown in Fig.
9and Fig. 10, respectively. It is clear that for the same buck-
boost factor the proposed method has lower n o7p and n ocy
factors in compare to alternate cascaded ZSI (N = 3). Lower
n o7p and n ocy factors results in cheaper elements and
inexpensive inverter. We should mention that based on (33)
and (34) the diode number has direct effect on n o7p and
n ocy factors and so the proposed method has higher factors
than alternate cascaded ZSI (N = 2). But because of lower
maximum voltage impressed and the lower peak and average
current going through diodes, has lower n o7p and n ocy
factors in compare to alternate cascaded ZSI (N = 3).
IV. EFFICIENCY COMPARISON
The calculated losses of the ZSI are based on the loss –
related parameters that are summarized in Table II. The
efficiency of proposed method will be compared with SL-ZSI
and alternate cascaded ZSI schemes, due to boost factor
closeness of three methods. According to parameters listed in
the Table II, the power losses of the inverter can be classified
as; conducting and switching losses of MOSFETS, core and
copper losses of inductors, and conducting losses of diodes
and capacitors.
Before calculating the power losses of proposed ZSI, some
assumptions are done:
• The capacitors' voltage ripples and inductors' current
ripples are neglected.
• The turn on loss of diodes is small enough to be
neglected.
• Off state blocking losses of switches and diodes are
neglected.
• The ripple loss of capacitors is small enough to be
neglected.
A. MOSFET losses
The power losses of active switches can be classified into
switching loss occurs during the ON and OFF period of
switching states, and conduction loss. The total switching
losses of MOSFETs can be calculated by:
Ab Ab~~ •B} b`a 2 4 (37)
33 where,•B} is switching frequency, b`a is inverter’s output
voltage, 4 (=4$ is average current of dc power
supply, andAb , Ab~~ are turn on and turn off delays of
MOSFETs, respectively.
34
The total conduction loss of switches is calculated as:
2 1.08 1 ob`a (38)
o b B} d B € 2 4 ƒ
3 8 h•‚
whered B is drain to source resistance of MOSFET,ob`a is
inverter’s output power, and h•‚is the load power factor.
B. Inductor losses
The power losses of inductors can be classified into core loss
inductors. However, the core losses per unit volume of T184-
26 can be obtained from Micro-metal provided data sheet. The
total conduction loss of inductors can be calculated as:
og 2d$ 4 2d$ 4 1 (39)
where d$ is the equivalent series resistance (ESR) of inductors
that is provided in Table II.
C. Capacitor losses
By using the equivalent series resistance (ESR) of capacitor s
in Table II the total conduction losses of capacitor can be
calculated as:
(40)
o 2d 4 1 1
1
where d is the equivalent series resistance (ESR) of
capacitor.
D. Diode losses
By assuming that the inductor currents are ripple free, the total
conduction losses of diodes can be calculated as:
o gbBB 3 ~ 4 (41)
where ~ is forward voltage drop of each diode, and
4 (=4$ is average current of dc power supply.
The calculated efficiencies of proposed inverter, SL-ZSI,
and alternate cascaded ZSI schemes versus boost factor are
shown in Fig. 11. From these results it is clear that for the
same buck boost factor, the proposed scheme provides higher
efficiency than those of SL-ZSI and alternate cascaded ZSI
schemes. In order to verify the claimed results in Fig. 11, each
loss will be analyzed individually. The percentage losses of
each component in proposed method are summarized in Fig.
12. It can be seen that for higher values of boost factor the
losses are mainly contributed by the inductor and capacitor.
Among them, the inductor loss is largest. So the higher
inductance in the power loop will result in inverter’s higher
losses and finally lower efficiency.
The ratio of MOSFET losses to output power for
aforementioned methods is shown in Fig. 13. It can be seen
that the proposed method has lower MOSFET losses in
compare to other methods, due to lower shoot through current
in proposed method than those in SL-ZSI and alternate
cascaded ZSI schemes. The ratio of diode losses to

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outputpower for three schemes are shown in Fig. 14. Since the
alternate cascaded SZI (N=2) has lesser diode numbers, so it
has lower diode losses. Fig. 15 indicates the ratio of inductor
losses to output power. Even though the number of inductors
in proposed scheme is higher than those in alternate cascaded
SZI (N=2), it has lower inductors’ losses in compare to
alternate cascaded SZI (N=2). Due to lower capacitors’
current in proposed ZSI in compare to SL-ZSI and alternate
cascaded ZSI schemes, the proposed ZSI has lower capacitors’
losses than other mentioned methods as shown in Fig. 16.
Since the proposed ZSI has lower capacitor currents so it
provides higher reliability with lower losses, size, and cost. Fig.4. Boost Factor against the duty cycle of shoot-through.
From results of Figs 13, and 14 it can be seen that the
proposed method has lower current stress (for MOSFETs and
diodes) than those of SL-ZSI and alternate cascaded ZSI
schemes.

V. SELF BOOST PHENOMENA

According to [27], without the shoot trough, the ZSI has a
voltage boost when operated at low modulation index and low
power factor. This phenomena is called” self boost”. We can
define a critical M such that for lower values of 8 Ia 7g the
uncontrolled shoot through will occure. For traditional ZSI the
8 Ia 7g can be defined as [27]:
2 (42)
Fig. 5.Buck-Boost factor against the modulation index.
8 I a 7g
3 ∗ …n‚
So for proposed method the 8 Ia 7g can be obtained as:

2 (43)
8 I a 7g
3 ∗ …n‚ ∗ 2
Based on (43) the 8 Ia 7g for proposed method is much
lower than that the traditional ZSI. So the acceptable interval
of M is much higher than that for traditional ZSI. Due to high
boosting capabilities of proposed ZSI for the same voltage
conversion ratio, the proposed scheme uses a higher M to
improve the inverter’s output quality.

TABLE I
PASSIVE COMPONENT COMPARISON
Con-ZSI SL Proposed Diode Alternate
ZSI ZSI assisted Cascade
QZSI d ZSI
(N=2)

Inductor 2 4 4 4 3

Capacitor 2 2 4 4 4

Diode 1 7 5 5 2

TABLE I I
PARAMETERS USED FOR EFFICIENCY COMPUTATION
ESR ind ESR cap
Diode MOSFET (mΩ) (mΩ) Core

ISL9R3060G2 STW45NM50 80 112 T184-26 Fig. 6. Voltage stress comparison, (a) Switches, (b) Capacitors, (c) Input
diode.

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Fig. 12. Percentage Losses vs buck-boost factor in proposed method

Fig. 7.KI vs buck-boost factor

Fig. 13. MOSFET loss/Pout vs buck-boost factor

Fig. 8. KC vs buck-boost factor

Fig. 14. Diode loss/Pout vs buck-boost factor

Fig. 9.n o7p of diodes vs buck-boost factor

Fig. 10.n ocy of diodes vs buck-boost factor Fig. 15. Inductor loss/Pout vs buck-boost factor

Fig. 16. Capacitor loss/Pout vs buck-boost factor

Fig. 11.Efficiency vs buck-boost factor

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2477346, IEEE Transactions on Industrial Electronics
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VI. SIMULATION & EXPERIMENTAL RESULTS
E. Simulation Results
The proposed topology shown in Fig. 2 has been simulated
by PSIM software platform. The main circuit parameters for
proposed topology are as follows:
1) = = = 700†‡, = = = = 500†ˆ
2) The switching frequency ˆB 10x‡‰
3) Three phase load R= 60Š , L= 5mH,
4) DC input voltage = 100 V
Fig. 17 shows the simulation results for the proposed ZSI
with shoot-through duty cycle of D = 0.18 and modulation
index of M = 0.82. From (10), (12), (15) and (18), the boost
factor, B = 2.9, and buck-boost factor, G = 2.38. From
simulation results one can observe that the capacitors’ voltage
and are, respectively, boosted to 195 and 237.5 V in the
steady state, and the peak dc-link voltage is boosted to 290
V. So the boosted factor can be calculated to be 290/100 =2.9.
Meanwhile, the peak ac output phase voltage 57 has been
boosted to 119 V.
These results clearly verify the high boosting capability of
the proposed ZSI. The simulation results clearly shows that
the dc-link voltage and phase voltage are boosted with the
boost factor 290/100 = 2.9, and 119/50 = 2.38 respectively
which are consistent with calculated values from (15) and (18)
when substituting the D = 0.18 and M = 0.82. So it has been
seen that in steady-state there is a good agreement between
simulation results and theoretical analysis. Fig. 18 shows the
dc side response where the shoot through is changed from 0.1
to 0.18. This will demonstrate the boosting capability in
transient condition. At 0.3 s the D has step change and
would change from 160 to 290 V. After some transients
! also increases from 145 to 237.5 V.
F. Experimental Results
Proposed ZSI was built in laboratory with the same
parameter used in simulation. Fig. 19 shows the experimental
setup. As depicted this setup includes the power MOSFETS,
driver boards, Z-impedance networks and high-performance
microcontrollerAtxmega128A3U.Fig. 20 shows the
experimental results for proposed ZSI when shoot-through
duty cycle D = 0.18 and modulation index M = 0.82. DC link
voltage is boosted from 100 V to 268 V, which is slightly less
than the calculated value (2.9*100 = 290 V) from (15) due to
the voltage reduction on the passive components, diodes, and
switching devices. Capacitor voltages and are boosted
to 186V, and 219 V, respectively. Substituting the D = 0.18
and = 100 V into (12) the calculated voltage for is
237.5 V that is slightly higher than the measured value.
Meanwhile, the rms value of line to line output voltage is
193V. Fig. 20 further shows the dc-link voltage, inductor
current, and load current which clearly are similar to
simulations except for some spikes and switching noises
superimposed. These spikes and noises are not seen in
simulation and are thus likely picked up from the hardware
semiconductor switching. Because of proper snubber design,
the MOFETs have enough protection against the spikes and
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noises. From Fig. 20 it is very clear that the peak dc-link
voltage maintains constant value during the non-shoot-through
states, and it is quite consistent with the theoretical value.The
experimental and simulation results of Figs. 17 and 20match
well with each other and those of the theoretical analysis for
the proposed inverter. Fig. 21 indicates the THD of output
current under D=0.18 and M=0.82 and with series load of L =
5 mH, and R = 60 Ω. It is clear that the THD is in acceptable
level. According to (43) with D=0.18, L=5 mH, and R=60 Ω
the 8 Ia 7g = 0.36. Fig. 22 shows the experimental results for
proposed method with D = 0.18, and M= 0.36. It can be seen
that the ZSI inverter works in normal operating mode and dc –
link voltage is 286 V that is slightly higher than that can be get
by M = 0.82. Fig. 23 shows the THD of output current under
D=0.18 and M=0.36 and with series load of L = 5 mH, and R
= 60 Ω. Because of lower M it can be seen that the current’s
THD is higher than that of Fig. 21. In Fig. 24 the M = 0.2
(M<8 Ia 7g ) and it can be seen that the dc-link voltage has
been boosted to 312 V that is higher than that can be obtained
from (15). The waveforms of load current under L=5 mH, and
R=60 Ω and various values of M are shown in Figs. 20, 22,
and 24. It can be seen that by decreasing the modulation index
the quality of inverter’s output current will be distorted.
Table III shows the simulation and experimental results
of the peak DC-link and capacitor voltages for the
proposed inverter. From Table III, we can observe that the
simulated DC-link voltage and capacitor voltages and
are, respectively, 7.59, 4.46 and 7.5% higher than the
experimental values. This is due to the fact that the voltage
drop on passive components, switches, and diodes were
ignored in simulation, while they cannot be ignored in real
passive components, switches, and diodes.
Even though, this topology provides a high step-up inversion
with high efficiency but it also suffers from following
limitations and drawbacks:
• The current drawn from the dc-source is discontinuous
due to input diode.
• It has greater size, and cost due to extra passive
components in compare to traditional ZSI.
• Because the initial voltage across the Z-source capacitors
is zero so a huge inrush current flows to the Din, and
capacitors that leads to output voltage and current spikes.
• The boost factor has been limited by various parameters
such as; THD, losses, and parasitic effects of components.
VI. CONCLUSION
Enhanced-boost Z-source inverter based on switched Z-
impedance has been presented. Compared with the
conventional ZSI, diode assisted QZSI, alternate cascaded
ZSI(N = 2), and SL-ZSI, the proposed inverter has the highest
boosting ability, and lowest voltage stress on active
components. Comparison between the proposed topology and
previously proposed schemes in terms of inductor numbers,
voltage and current stresses on elements, efficiency, sizes of
inductors and capacitors, and SDP factors of diodes, has been
made and the results verify the priority of the proposed
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2477346, IEEE Transactions on Industrial Electronics

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topology. Both the simulation and experimental results verify

the advantages and effectiveness of the proposed ZSI.

TABLE III
PEAK DC-LINK AND CAPACITOR VOLTAGE IN SIMULATION AND
EXPERIMENTAL
Simulation Experimental ∆ Experimental
%

Peak DC link 290 268 7.59

voltage

Capacitor 195 186 4.46

voltage ,

Capacitor 237.5 219 7.5

voltage ,

Fig. 20. Experimental results of proposed ZSI with D=0.18 and M=0.82
Fig. 17. Simulation results for the proposed ZSI, M=0.82 and D=0.18.

Fig. 18.Transient behavior of proposed ZSI.

Fig. 21. THD of output current with D=0.18 and M=0.82

Fig. 19. Experimental setup Fig. 22. Experimental results of proposed ZSI with D=0.18 and M=0.36

0278-0046 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2477346, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Fig. 23. THD of output current with D=0.18 and M=0.36
Fig. 24. Experimental results of proposed ZSI with D=0.18 and M=0.2
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Hossein Fathi Kivi received the B.Sc. from
Hadaf Institute in 2011 and the M.Sc. from Sahand
Univ. of Tech., Tabriz, Iran in 2014. His main
research interests include power electronic
converters.
Hossein Madadi Kojabadi (M’15) received the
Ph.D. degree in Electrical Engineering from
University of New Brunswick, Fredericton, N.B.,
Canada in 2003.
Since 1993, he has been a faculty member at
Sahand University of Technology, Tabriz, Iran.
During 2003-2004 he was Post-Doctoral Fellow
at University of New Brunswick, Fredericton,
N.B., Canada. He has published over 100 papers
in technical journals and conference proceedings
and two books. He is currently managing director
of Renewable Energy Research Center. His
principal research interests and experience include renewable energy
conversion, power electronic converters and variable-speed drives.