T5 Baiscs of ADPLL

ISSCC 2023 Tutorials
All-digital PLLs
From Fundamental Concepts to Future Trends
Akihide Sai
Toshiba Corporation
Live Q&A Session: Feb. 19, 2023,

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 1 of 77
© 2023 IEEE International Solid-State Circuits Conference

Self-introduction
 Akihide Sai
 M.D. in EE from Waseda Univ., Tokyo, 2004
 R&D Fellow with Toshiba Corp.

 Now within LiDAR R&D Group as Project Leader
 19 years in Toshiba Corp.
 Interests in high-performance mixed-signal circuit

 Digital/analog phase-locked loops(PLLs)
 Low power transceivers
 Automobile LiDAR SoCs

Motivation of Tutorial
Cyber
PLL PLL
5G/LTE/WiFi
PLL
PLL
Physical
 Recently, Phase-Locked Loop (PLL) has become more and more indispensable.
Almost all components for Cyber-Physical IoT systems (GPU/CPU, data center,
wireline/wireless…) need PLL for system clocking, data recovery, RF mixing!
 First of all, grasp basic of frequency synthesis including PLL, and then analyze
the principle and benefit of Digital-PLL, with the technique evolution trend.
 Finally, try to analyze and predict the future evolution trend.

Outline
 Background of Frequency Synthesis
 Design Challenges for Jitter, Phase noise, Lock up
 Basic All-Digital PLL
 Fractional-N Operation, Spurious Tones
 Digital Implementation
 Time-to-Digital Converter (TDC)
 Advanced Digital PLL
 Basic and Fundamentals
 High performance TDCs and Fractional Spur Cancellation Techniques
 Performance Trends Analysis
 Future Trend Prediction
 Summary & conclusions

Outline

Frequency synthesis: Applicative constraints
Mixing Sampling
111
fRF fBB 110 Error!
LNA LPF 101
100
fLO 011
010
Error!
PLL 001
000
Low noise in frequency domain Low noise in time domain
fBB fLO fRF Freq.

⇒Jitter Time
⇒Phase Noise
T5: All-digital PLLs : From fundamental concepts to future trends
A. Sai 6 of 77

Period Jitter and Frequency Noise
 Period Jitter : 1-cycle fluctuation expressed in time domain
 Frequency Noise : 1-cycle fluctuation expressed in frequency domain
Period jitter [sec rms] Frequency Noise [dBc/Hz]
TOUT
Time fOUT Freq.

𝟏𝟏
𝑻𝑻𝑶𝑶𝑶𝑶𝑶𝑶 =
𝒇𝒇𝑶𝑶𝑶𝑶𝑶𝑶

Phase Jitter and Phase Noise
 Phase Jitter : long-term fluctuation expressed in time domain
 Phase Noise : long-term fluctuation expressed in phase domain
Phase jitter [sec rms] Phase Noise [dBc/Hz]
2π
𝒕𝒕
・・・ φOUT = � 𝟐𝟐𝝅𝝅𝒇𝒇𝑶𝑶𝑶𝑶𝑶𝑶 𝒅𝒅𝒅𝒅
0 𝟎𝟎
・・・
fOUT fa fb Freq.
Time
𝒇𝒇𝒃𝒃
𝟏𝟏
𝑷𝑷𝑷𝑷𝑷𝑷𝑷𝑷𝑷𝑷 𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋 = � 𝑷𝑷𝑷𝑷𝑷𝑷 𝝓𝝓𝑶𝑶𝑶𝑶𝑶𝑶 𝒅𝒅𝒅𝒅 [𝒔𝒔𝒔𝒔𝒔𝒔𝒓𝒓𝒓𝒓𝒓𝒓 ]
𝟐𝟐𝝅𝝅𝒇𝒇𝑶𝑶𝑶𝑶𝑶𝑶 𝒇𝒇𝒂𝒂

Free-running Oscillator
 Open-loop free-running oscillator is most simple clock generation

 Voltage Controls Oscillator Frequency → VCO (Voltage Controlled Oscillator)
Vctl OUT
Vctl: High
Vctl: Medium
Vctl: Low

Free-running VCO
 Two major VCO types, LC/Ring,

have critical design trade-off
Vctl OUT Vctl Vctl
[Mitteregger,ISSCC’06]
LC VCO
for CLK PLL LC Ring
Phase Noise  
14bit ΔΣ ADC Chip Area  
LC VCO for sampling clock
may larger than ADC itself !!

Issues with Free-running Oscillator
 Poor phase noise and jitter performance of VCO

 No feedback controls enable jitter to diverge to infinity!
Vctl OUT
Tmeasure
・・・・・・
fOUT Time
Freq.
1/Tmeasure

Issues with Free-running Oscillator
 Poor frequency accuarcy

 Oscillation frequency can easily change with PVT variation
Transistor
Vctl OUT Freq. Transistor Typ. Corner
Fast Corner (Expected)
Transistor
Slow Corner
Time Vctl

Amplifier: How to Create Accurate Output?
 Negative feedback can generate accurate output in voltage domain

 Key points are large feedforward gain A, and feedback factor β
Input Output
Voltage Voltage Input Output
Gain Amp.
+ A
Voltage Voltage
-
Accurate Voltage
Reference Voltage
β Reference
𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶 𝟏𝟏 𝟏𝟏
= ≒
𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰 𝟏𝟏/𝑨𝑨 + 𝜷𝜷 𝜷𝜷
A>>1

PLL: How to Create Accurate Clock?
 Phase-domain negative feedback can generate accurate output ?

 ‘Accurate’ means low phase noise and high frequency accuracy
Input Output
Input Output
Phase
Gain Phase PLL
+ A
Phase Phase
-
Reference CLK Accurate
β Phase/Frequency Clocks
𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶 𝟏𝟏 𝟏𝟏
= ≒
𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰 𝟏𝟏/𝑨𝑨 + 𝜷𝜷 𝜷𝜷
A>>1

PLL: How to Create Accurate Clock?
 Feedback is constrained to clock division ratio

 Feedforward gain over the frequency spectrum determines PLL performance
Input Output
Input Feedforward Output
Phase Gain Phase
+ HOL(s)
Phase Gain HOL(s) Phase
-
Divider
Reference CLK Accurate
1/N Phase/Frequency Clocks
𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶 𝟏𝟏
= ≒ 𝑵𝑵
𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰 𝟏𝟏/𝑯𝑯𝑶𝑶𝑶𝑶 𝒔𝒔 + 𝟏𝟏/𝑵𝑵
HOL(s) >>1 N: Divider Ratio

Type-I Analog PLL
 Type-I PLL has one integrator of VCO frequency-to-phase conversion

𝒕𝒕
Phase-to-Voltage Voltage-to-Phase φOUT = � 𝟐𝟐𝝅𝝅𝒇𝒇𝑶𝑶𝑶𝑶𝑶𝑶 𝒅𝒅𝒅𝒅
Phase Detector 𝟎𝟎
Input Vctl Output
PD
+
Phase Phase
KPD LF(s) KVCO /s
Input - Output
Phase
Phase
Divider
1/N Gain
-20dB/dec 𝑲𝑲𝑷𝑷𝑷𝑷 𝑳𝑳𝑳𝑳(𝒔𝒔)𝑲𝑲𝑽𝑽𝑽𝑽𝑽𝑽
𝑯𝑯𝑶𝑶𝑳𝑳 𝒔𝒔 =
𝑵𝑵・𝒔𝒔
𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶 𝟏𝟏 𝜔𝜔
= ≒ 𝑵𝑵
𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰 𝟏𝟏/𝑯𝑯𝑶𝑶𝑶𝑶 𝒔𝒔 + 𝟏𝟏/𝑵𝑵

Type-I Analog PLL
 PLL loop bandwidth(BW) is determined by unity gain frequency of HOL(s)

𝒕𝒕
 Type-I PLL suppress VCO phase noise by 1st-order HPF φ
OUT = � 𝟐𝟐𝝅𝝅𝒇𝒇𝑶𝑶𝑶𝑶𝑶𝑶 𝒅𝒅𝒅𝒅
φVCO Phase Detector 𝟎𝟎
Input Vctl Output
φin PD
+
Phase Phase
KPD LF(s) KVCO /s +
Input - Output
Phase
Phase
Divider
1/N Gain
PLL
loop BW
Signal Transfer Function Noise Transfer Function
(STF) (NTF)
𝜔𝜔
φOUT 𝟏𝟏 φOUT 𝑵𝑵・𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔) STF NTF
= =
φin 𝟏𝟏 + 𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔) φ𝑽𝑽𝑽𝑽𝑽𝑽 𝟏𝟏 + 𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔) 20dB/dec

Type-II Analog PLL
 Type-II PLL has additional integrator of charge pump and loop filter
Phase-to-Current Phase Frequency
Current-to-Voltage Detector
Voltage-to-Phase Vctl
Input Charge Output
PFD Phase
Phase Pump
+ KPFD KCP LF(s) KVCO/s
Input - Output
Phase
Phase
Divider
1/N Gain
𝑲𝑲𝑷𝑷𝑷𝑷𝑷𝑷 𝑲𝑲𝑪𝑪𝑪𝑪 𝑳𝑳𝑳𝑳(𝒔𝒔)𝑲𝑲𝑽𝑽𝑽𝑽𝑽𝑽
-40dB/dec 𝑯𝑯𝑶𝑶𝑳𝑳 𝒔𝒔 =
𝑵𝑵・𝒔𝒔
𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶 𝟏𝟏 𝜔𝜔
= ≒ 𝑵𝑵
𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰𝑰 𝟏𝟏/𝑯𝑯𝑶𝑶𝑶𝑶 𝒔𝒔 + 𝟏𝟏/𝑵𝑵 Zero for
Loop stability

Type-II Analog PLL
 Type-II PLL suppresses VCO phase noise by 2nd-order HPF

Phase Frequency
φVCO Detector
Charge Vctl Output
Input
PFD Phase
φin Phase Pump
+ KPFD KCP LF(s) KVCO/s +
Input - Output
Phase
Phase
Divider
1/N Gain
PLL
-40dB/dec loop BW
Signal Transfer Function Noise Transfer Function
(STF) (NTF)
𝜔𝜔
φOUT 𝟏𝟏 φOUT 𝑵𝑵・𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔) STF NTF
= =
φin 𝟏𝟏 + 𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔) φ𝑽𝑽𝑽𝑽𝑽𝑽 𝟏𝟏 + 𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔)
40dB/dec

Loop BW Design Consideration (1/3)
 Wide loop BW is effective for poor phase-noise VCO Ring

Phase LC
Noise
Reference
Noise
Clean signal
Narrow BW Wide BW
𝜔𝜔
Gain
from XO
NTF
40dB/dec
𝜔𝜔

PLL Jitter Figure-of-Merit(FoM)
 Definition
𝟐𝟐
RMS jitter Power
𝑭𝑭𝑭𝑭𝑭𝑭𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋𝒋 = 𝟏𝟏𝟏𝟏log𝟏𝟏𝟏𝟏 [dB]
𝟏𝟏sec 𝟏𝟏mW
Phase Noise [dBc/Hz]
Phase jitter [sec]
𝒇𝒇𝟎𝟎 Freq.

PLL Performance Trend(~2005)
Ring-VCO
Analog
LC-VCO
Analog
Jitter FoM
[dB]
Chip Area
[mm2]

Noisy Reference
Clock Data Recovery Gain
Noisy Reference
STF
Narrow BW Wide BW
Phase
Dynamic Voltage and Margin 𝜔𝜔
Frequency Scaling
180
Type-I
Freq. Wide BW
90 Type-II
Poor Loop
Narrow BW stability
Time 0
 Narrow-loop-BW PLL can behave as noise filter for dirty input signal
 Lock-up responsivity is proportional to loop BW
 Type-I has better stability than that of type-II PLL

Amplifier Design Trade-off
 Key factors are feedforward gain, gain BW, feedback factor.
Noise Volt. Step
Ampli-
fier
Area/Power Response

PLL Design Trade-off
 Key factors are loop gain & BW, Type-I/II & VCO selection.
Phase Noise Freq. Step

& Jitter
PLL
Area/Power Lock up time

-200.0
Ring-VCO
-210.0 Analog
LC-VCO
-220.0
Analog
LC-DCO
-230.0 All-
Jitter FoM Digital
[dB]
DTC- Divider-
-240.0
based based
Bang-
-250.0 bang Ring-VCO Analog LC-VCO Analog
LC-DCO All-Digital Divider-based
Digital DTC-based Bang-bang Digital
Digital MDLL
-260.0
0.01 0.1 1 10
Chip Area
[mm2]

Outline

Integer-N vs Fractional-N Operation (1/2)
Charge Vctl Output
Input
PFD Phase
Phase Pump
fREF=1/TREF fVCO=1/TVCO
DIVout
Divider: 4
Phase Input DIVout

phase phase Integer-locked case: N=4
2π
0
TREF =4xTVCO Time

Integer-N vs Fractional-N Operation (2/2)
Charge Vctl Output
Input
PFD Phase
Phase Pump
φSpur DIVout
Divider: 4/5
∆Σ Delta-Sigma Modulator
Phase Input DIVout
phase phase φSpur Fractional-locked case: N=4.5
2π
0
Time
N=4 N=5 N=4 N=5

 Narrow loop BW is effective for fractional spurs

 However, around 10kHz-cut-off analog filter is required,
if spur frequency and attenation are 100kHz and 20dB, respectively
Gain
Narrow BW Wide BW
STF
φSpur
Signal Transfer Function
(STF)
φOUT 𝟏𝟏
=
φin 𝟏𝟏 + 𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔) Spur. Freq.

Outline

Innovation: All-Digital PLL
FCW Digital OUT

+ Loop Filter
DCO
(Digitally Controlled Oscillator)
-1
Counter DCO output phase
1-Z +TDC is fully digitized!!
REF [Staszewski,ISSCC’05]
 Free from Analog-filter and Divider

 Great benefit from CMOS scalability
 Chip-area and Power shrinking, Low development cost
 Robustness to PVT variation

All-Digital PLL: Operation
 DCO phase quantization of TDC much mitigates spur periodicity
φOUT
M/M+1
Phase Phase φOUT φOUT

Input phase
(FCW ∫) Counter
N=M+1 Output
Input phase×N N=M TDC
Output
N=M+1
N=M Time Time

Outline

All-Digital PLL: TDC Operation (1/3)
T delay
FCW Digital OUT
REF + Loop Filter
-1
Counter
1-Z +TDC
OUT
REF
REF
OUT
𝝓𝝓𝑬𝑬
𝝓𝝓𝑬𝑬 = 𝟏𝟏 − 𝚫𝚫𝒕𝒕𝒓𝒓 /𝑻𝑻𝑽𝑽
0 1 1
𝑻𝑻𝑽𝑽 ∆tr : REF and DCO time difference
TV : DCO Period
 TDC quantizes ΦE using inverter delay, Tdelay, as LSB(Least Significant Bit)

 ΦE is calculated from DCO Rise/Fall transition data sampled by delayed REF

SS/FF corner
T delay SS/FF corner 𝝓𝝓𝑬𝑬
REF
0 Time
OUT Full-Scale Error
REF Larger fractional spur & jitter
OUT
𝝓𝝓𝑬𝑬
𝝓𝝓𝑬𝑬 = 𝟏𝟏 − 𝚫𝚫𝒕𝒕𝒓𝒓 /𝑻𝑻𝑽𝑽(𝑭𝑭𝑭𝑭𝑭𝑭)
0 1 1
𝑻𝑻𝑽𝑽 ∆tr : REF and DCO time difference
TV(Fix): Estimated DCO Period
 PVT variation of inverter delay causes significant Full-Scale(FS) Error

T delay SS/FF corner 𝝓𝝓𝑬𝑬
REF
0 Time
OUT
REF
OUT
𝝓𝝓𝑬𝑬
𝝓𝝓𝑬𝑬 = 𝟏𝟏 − 𝚫𝚫𝒕𝒕𝒓𝒓 /𝑻𝑻𝑽𝑽(𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨)
1 0 0 1 1
𝑻𝑻𝑽𝑽 𝑻𝑻𝑽𝑽(𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨) = 𝟐𝟐 𝚫𝚫𝒕𝒕𝒇𝒇 − 𝚫𝚫𝒕𝒕𝒓𝒓
 PVT variation of inverter delay causes significant Full-Scale(FS) Error

 TDC Error normalization using DCO period average circuit fixes the problem

All-Digital PLL: Type-II Digital Filter
φE
IIR NTW φE Vctl
Filter + Charge
From ρ To From Pump
TDC DCO To
PFD
α VCO
1/(Z-1) Zero for
Loop stability
Z-domain → S-domain Model S-domain Model
𝝆𝝆𝒇𝒇𝑹𝑹 + 𝒔𝒔𝜶𝜶𝑰𝑰𝑰𝑰𝑰𝑰 𝒔𝒔 𝑰𝑰𝑪𝑪𝑪𝑪 𝟏𝟏 + 𝒔𝒔𝒔𝒔𝒔𝒔

𝑫𝑫𝑫𝑫𝑫𝑫 𝒔𝒔 = 𝑲𝑲𝑪𝑪𝑪𝑪 𝑳𝑳𝑳𝑳 𝒔𝒔 =
𝒔𝒔 𝟐𝟐𝝅𝝅 𝒔𝒔𝑪𝑪
 Small Area, Process scalability

 Software programmed PLL loop: Gentle transition from type-I to type-II

All-Digital PLL: Z to S-domain Model
 All-digital PLL can realize the same STF/NTF as Type-II analog PLL
Phase-to-Digital Digital-to-Phase
+ KTDC DLF(s) KDCO/s

Input - Output
Phase
Gain
Phase
-40dB/dec 𝑯𝑯𝑶𝑶𝑳𝑳 𝒔𝒔
𝒔𝒔 𝜔𝜔
𝟐𝟐 𝟏𝟏 +
𝝆𝝆𝒇𝒇𝑹𝑹 𝝆𝝆𝒇𝒇𝑹𝑹 /𝜶𝜶
𝑯𝑯𝑶𝑶𝑳𝑳 𝒔𝒔 = 𝑰𝑰𝑰𝑰𝑰𝑰(𝒔𝒔) STF NTF
𝒔𝒔 𝒔𝒔
Area-efficient
Digital Filter
can be used!!

All-Digital PLL: Poor TDC Noise
FCW Digital OUT

Fractional-locked case
+ Loop Filter Phase
Ideal locked phase
2π
Counter
1-Z-1 +TDC
REF
φQN,NL 0
Time
Quantization Noise Non-Linearity
TDC noise performance critically limits All-Digital PLL
 TDC Quantization Noise(QN) and Non-Linearity(NL) are converted to
spurs or noise concentrated at fractional frequency away from PLL carrier

Challenge: High-Resolution TDC
Td1 DCO
DCO
REF
REF
TA TA TA
T d2
Vernier Delay Line(VDL) [Dudek,JSSC’00] MUX
Fine Stage
Time Amp(TA) [Lee,JSSC’09]
 VDL time resolution can be enhanced from Td to |Td1-Td2|

 TA can amplify time difference using meta-stability of latch

Challenge: High-Resolution TDC
Td1 DCO
DCO
REF
REF
TA TA TA
T d2
Vernier Delay Line(VDL) [Dudek,JSSC’00] MUX
Fine Stage
Pros: Low QN Time Amp(TA) [Lee,JSSC’09]
Cons: Power hungry
 However, multiple circuits operated at DCO output speed are needed

Ring-VCO
Analog
LC-VCO
Analog
LC-DCO
All-
Jitter FoM Digital
[dB]
Chip Area
[mm2]

Outline

Advanced Digital PLL(Divider-based)
REF Digital OUT

TDC
Loop Filter
Divider
FCW
∆Σ [Zanuso,JSSC’11]
 Down-speeded DCO output make large benefit for TDC

 Great benefit from CMOS scalability is still maintained
 Chip-area and Power shrinking, Low development cost
 Robustness for PVT variation

Outline

Time Stored TDC
 Time-Stored type TDC can improve QN and NL by using voltage resolution

 Once ΦE is stored as charge/voltage, high digital affinity ADC can be used
Phase Detector ADC

REF
φE QF or VF Single-slope Dout
DCO
PD
SAR
Pipeline
Cyclic…
φE Charge
Fractional Voltage -to-Digital
Phase Error QF or VF
0111
…
・・・
DCO Dout
0001
REF 0000

Time Stored TDC: Single-slope
DCO
[Sai,ISSCC’16]
REF
PD ΦF CP
VF Major performance(CMOS 65nm)
DCO Σ Dout  Resolution :6.0ps
VRAMP
ΦF
Fractional
SS-ADC  INL :1.6ps
VF VRAMP  Power :0.36mW
Phase
(0~2π)  Sample-rate :40MS/s
 Calibration :No
DCO … …
REF
2π Dout = N
 Charge-pump NL and full-scale error cancellation by sharing current source
 Counter is shared with that of AD-PLL integer-phase for power reduction

Time Stored TDC: Gated Ring Oscillator(GRO)
[Hetal,VLSI’08]
 Maintain ring oscillator phase

in the interval between measurements
 TDC QN becomes first order noise shaped
 e[k] = Phase Error[k] + q[k] – q[k-1]
 Leverages PLL STF filtering to achieve improvement in resolution

Time Stored TDC: Gated Ring Oscillator(GRO)
[Hsu,ISSCC’08]
 Major performance(CMOS 130nm)

 Resolution :6.0ps
 Power :3.45mW
 Sample-rate :50MS/s
 Calibration :No
 TDC Resolution is proportional to an effective stage-delay

 Effective stage delay per stage is reduced from 35ps to 6ps
by leveraging edges from several previous delay stages

Delta-Sigma Modulator(∆ΣM) Q-Noise
Narrow Loop BW
REF Digital OUT DCO Dominant
TDC
Loop Filter
Divider
FCW
φQN ∆Σ
Signal Transfer Function(STF)

Wide Loop BW
φOUT 𝟏𝟏 ∆ΣM Q-noise Dominant
=
φ𝑸𝑸𝑸𝑸 𝟏𝟏 + 𝑯𝑯𝑶𝑶𝑶𝑶 (𝒔𝒔)
DCO phase noise

∆ΣM Quantization noise
Total noise

ΔΣM Q-Noise Cancellation(QNC) (1/2)
QNC
REF OUT
TDC + DLF
-
LMS
Divider
FCW
∆Σ [Hsu,ISSCC’08]
 ΔΣ Q-noise is greatly suppressed without analog mismatch

 Benefit from Down-speeded DCO output is still maintained
 Easy to use Time-Stored type and improve QN and NL of TDC

ΔΣM Q-Noise Cancellation(QNC) (2/2)
 Phase error due to ΔΣ is predictable by accumulating ΔΣ quantization error

 Correlator out is accumulated and filtered to achieve scale factor

Divider-based Digital PLL: QNC & GRO
[Hsu,JSSC’08]
Major performance(CMOS 130nm)

 Jitter :0.2ps
 Effect of QNC/GRO on divider/TDC
 FoM :-237.9dB
quantization noise realizes outstanding
 Power :46.7mW
jitter performance
 Area :0.96mm2
 Relatively large power and area
 Frequency :3.67GHz
due to less process scaling merit

Divider-based Digital PLL: Single-Slope TDC
Phase T-to-V Digital Convertion

Detection Convertion (Single-Slope ADC) TDC  Down-speeded TDC input and counter
sharing technique realize much power
Share!
reduction
REF ΦF CP VF SS-ADC  Divider ratio limits TDC resolution
PD DF
DCO
Σ Fractional [Sai, Kondo JSSC’16]
Phase
DI
(0~1) Major performance(CMOS 65nm)
Σ Integer  Jitter :0.8ps
Phase
(1,2,3...)  FoM :-237dB
 Power :3.0mW
OUT DLF 1-Z-1
 Area :0.23mm2
FCW  Frequency :2.2-2.4GHz

Ring-VCO
Analog
LC-VCO
Analog
LC-DCO
All-
Jitter FoM Digital
[dB]
Divider-
based
Chip Area
[mm2]

Outline
 Divider-less All-Digital PLL
 Noise analysis & Performance enhancement techniques
 Divider-based Digital PLL
 High performance TDCs and ΔΣM Q-Noise Cancellation
 Performance Trends analysis thorough DTC introduction

Innovation: Digital-to-Time Converter
REF Fine
DLF OUT
TDC
DTC Divider
LMS
FCW
∆Σ QNC [Tasca,Zanuso, JSSC’11]
 DTC can make TDC dynamic range very narrow

 ΔΣ Q-noise suppression and down-speeded DCO are maintained
 ΔΣ Quantization error is canceled by simple LMS without analog mismatch

DTC: High Resolution Divider Function
Divided
DCO Phase
DTC Time-domain Model
φDIV_int
φDIV_int φDTC_frac
2π ∫
2π
DTC
φDTC_frac
Ideal locked
phase
(FCW ∫)
 ΔΣ Q-noise and required TDC input range are reduced by DTC time resolution
 However, DTC gain “g” must be adjusted so that the full scale becomes 2π

DTC: Gain Calibration
REF Fine Integer From

DTC DCO
TDC Divider
 DTC delay gain “g” is estimated from TDC error information in background

Outline

DTC based-Digital PLL: Recent Papers(1/2)
 DTC enables to use high-resolution

and narrow-range time-amplifier (TA)
based TDC with low power
[Elkholy,JSSC’15]
 Jitter :0.49ps
 FoM :-240.5dB
 Power :3.7mW
 Area :0.22mm2
 Frequency :4.4-5.2GHz

DTC based-Digital PLL: Recent Papers(2/2)
[Liu,ISSCC’18]

 DTC enables to use high-resolution  Jitter :0.53ps
and narrow-range time-amplifier  FoM :-246dB
(TA) based TDC with low power
 Power :0.98mW
 Single-slope based DTC realizes
 Area :0.23mm2
much lower power consumption

Ring-VCO
Analog
LC-VCO
Analog
LC-DCO
All-
Jitter FoM Digital
[dB]
DTC- Divider-
based based
Chip Area
[mm2]

Outline

Recent Trend: Bang-bang Digital PLL
REF Bang- OUT

bang PD DLF
DTC Divider
Thermal Jitter
LMS [Tasca, ISSCC’11]
FCW
[Santiccioli, ISSCC’20]
∆Σ QNC
[Mercandelli, ISSCC’21]
[Santiccioli, ISSCC’22]
 DTC enables to use ultimate form of 1-bit TDC, bang-bang PD

Bang-bang Digital PLL: Recent Papers(1/2)
Bang-bang
Phase Detector
[Santiccioli,ISSCC’20]
 Jitter :66.2fs
 High-resolution DTC and  FoM :-250.6dB
1-bit bang-bang PD realizes  Power :19.8mW
much lower jitter performance  Area :0.17mm2

Bang-bang Digital PLL: Recent Papers(2/2)
Noise-shaping
 High-resolution DTC and
BB-PD
1-bit bang-bang PD realizes
much lower jitter performance
[Mercandelli,ISSCC’21]
 Jitter :79.5fs
 FoM :-251.7dB
 Power :10.8mW
 Area :0.21mm2

Ring-VCO
Analog
LC-VCO
Analog
LC-DCO
All-
Jitter FoM Digital
[dB]
DTC- Divider-
based based
Bang-
bang
Digital
Chip Area
[mm2]

Digital PLL Evolution Summary
All-Digital Divider Less Divider-based Digital PLL
 Free from complex analog design  High performance time-stored TDC
Digital PLL with QNC DTC-based bang-bang Digital PLL
 Quantization noise suppression  Ultimate 1-bit TDC implementation

Digital MDLL using DTC/Bang-bang PD
[Marucci,ISSCC’14]
 Jitter :1.4ps
 FoM :-232dB
 Frac. Spur :-47dBc
 All standard-cell implementation allows  Power :3mW
low-cost and high-flexibility design  Area :0.4mm2
 Poor phase noise and mismatch of delay  Frequency :1.6-1.9GHz
line dominate jitter and fractional spur

-200.0
Ring-VCO
-210.0 Analog
LC-VCO
-220.0
Analog
LC-DCO
-230.0 All-
Jitter FoM Digital
[dB]
DTC- Divider-
-240.0
based based
Bang-
Digital MDLL
-260.0
0.01 0.1 1 10
Chip Area
[mm2]

PLL Performance Trend(2023~)
-200.0
Ring-VCO
-210.0 Analog
LC-VCO
-220.0
Analog
LC-DCO
-230.0 All-
Jitter FoM Digital
[dB]
DTC- Divider-
-240.0
based based
Bang-
???
Digital MDLL
-260.0
0.01 0.1 1 10
Chip Area
[mm2]

Outline

Summary
 Frequency synthesis and PLL has become more and more indispensable
for recent growing demand of IoT systems.
 PLL is phase-domain feedback system to generate accurate frequency/phase output
; major applicative constraints and design challenges are fractional-N operation
with low jitter, low phase noise, and low fractional spur.
 All digital PLL is major breakthrough in frequency synthesis;
greatly mitigates tradeoff between loop bandwidth and area penalty of loop filter
 Advanced digital PLL with divider and DTC continue to improve jitter FoM by
cancelling ΔΣM Q-Noise and by making required TDC dynamic range very narrow;
ultimate TDC implementation is 1-bit bang-bang phase detector.
 While bang-bang digital PLL with divider and DTC continues being mainstream, it
must be taken into consideration that bang-bang digital MDLL benefit much from
CMOS process scaling.

Papers to See This Year
Session 4 Relevant Papers:
 4.2: good example of ring-VCO based analog PLL
 4.3 and 4.5: good example of DTC-based bang-bang digital PLL
Session 14 Relevant Papers:

 14.1: Fractional-N MDLL with excellent DTC NL cancellation
 14.2: Innovative DTC INL Calibration technique using auxiliary PLL

Right PLL in the Right place !!!
 Key factors are TDC, DTC, Divider, DCO selection, Digital/Analog.
Bang-bang
Phase Noise Digital Freq. Step
& Jitter
LC-DCO
Digital PLL All-Digital
MDLL
Area/Power Lock up time
Ring-VCO
Type-I
Analog

T5 Baiscs of ADPLL

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ISSCC 2023 Tutorials

Live Q&A Session: Feb. 19, 2023,

© 2023 IEEE International Solid-State Circuits Conference

 M.D. in EE from Waseda Univ., Tokyo, 2004

 R&D Fellow with Toshiba Corp.

 Interests in high-performance mixed-signal circuit

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 2 of 77

© 2023 IEEE International Solid-State Circuits Conference

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 3 of 77

© 2023 IEEE International Solid-State Circuits Conference

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 4 of 77

© 2023 IEEE International Solid-State Circuits Conference

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 5 of 77

© 2023 IEEE International Solid-State Circuits Conference

Low noise in frequency domain Low noise in time domain

fBB fLO fRF Freq.

© 2023 IEEE International Solid-State Circuits Conference

Period jitter [sec rms] Frequency Noise [dBc/Hz]

Time fOUT Freq.

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 7 of 77

© 2023 IEEE International Solid-State Circuits Conference

Phase jitter [sec rms] Phase Noise [dBc/Hz]

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 8 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Open-loop free-running oscillator is most simple clock generation

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 9 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Two major VCO types, LC/Ring,

Vctl OUT Vctl Vctl

© 2023 IEEE International Solid-State Circuits Conference

 Poor phase noise and jitter performance of VCO

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 11 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Poor frequency accuarcy

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 12 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Negative feedback can generate accurate output in voltage domain

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 13 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Phase-domain negative feedback can generate accurate output ?

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 14 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Feedback is constrained to clock division ratio

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 15 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Type-I PLL has one integrator of VCO frequency-to-phase conversion

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 16 of 77

© 2023 IEEE International Solid-State Circuits Conference

 PLL loop bandwidth(BW) is determined by unity gain frequency of HOL(s)

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 17 of 77

© 2023 IEEE International Solid-State Circuits Conference

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 18 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Type-II PLL suppresses VCO phase noise by 2nd-order HPF

A. Sai T5: All-digital PLLs : From fundamental concepts to future trends 19 of 77

© 2023 IEEE International Solid-State Circuits Conference

 Wide loop BW is effective for poor phase-noise VCO Ring

© 2023 IEEE International Solid-State Circuits Conference

Phase Noise [dBc/Hz]

Phase jitter [sec]

© 2023 IEEE International Solid-State Circuits Conference

© 2023 IEEE International Solid-State Circuits Conference

© 2023 IEEE International Solid-State Circuits Conference

 Key factors are feedforward gain, gain BW, feedback factor.