LTC3305

Lead-Acid Battery Balancer

FEATURES DESCRIPTION
n Single IC Balances Up to Four 12V Lead-Acid The LTC®3305 balances up to 4 lead-acid batteries
Batteries in Series connected in series. It is intended to be used in conjunction
n All NFET Design with a separate pre-existing battery charger as part of a
n Stackable to Balance Larger Series Battery Packs high performance battery system. All voltage monitoring,
n Standalone Balancing Operation: Requires No gate drive, and fault detection circuitry is integrated.
External μP or Additional Control Circuitry
The LTC3305 employs an auxiliary battery or an alternative
n Balancing Current Limited by External PTC Thermistor
storage cell to transfer charge to or from each individual
n Continuous Mode and Timer Mode
battery in the stack. A mode pin provides two operating
n Programmable UV and OV Fault Thresholds
modes, timer mode and continuous mode. In timer mode,
n Programmable Termination Time and Termination
once the balancing operation is completed, the LTC3305
Voltage
goes into a low power state for a programmed time and then
n Thermally Enhanced 38-Lead TSSOP Package
periodically rebalances the batteries. In continuous mode,
APPLICATIONS the balancing operation continues even after the batteries
are balanced to their programmed termination voltage.
n Telecom Backup Systems
The LTC3305 is available in a thermally enhanced 38-lead
n Home Battery Powered Backup Systems
TSSOP package.
n Industrial Electric Vehicles
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n Energy Storage Systems (ESS) Technology Corporation. All other trademarks are the property of their respective owners.
n Medical Equipment

TYPICAL APPLICATION
4-Battery Balancer with Programmed High and Low Battery Voltage Faults
10µF
25V

CHARGER
VREG CM CP 1.33k SUPPLY
EN1 249Ω NGATE5

1µF
EN2
MODE
BOOST
10µF
6.04k ICHARGE
BATTERY
STACK
Battery Voltages Converge
6V TERM1
V4
25V CHARGER Over Time
TERM2 NGATE4
+
10µF 6.04k BAT4 16
UVFLT 25V
OVFLT
DONE V3
14
100k EACH BAL NGATE3 +
PTCFLT 10µF 3.01k BAT3 12
BATTERY VOLTAGE (V)

BATX 25V
BATY 10
V2
CTON LTC3305 NGATE2
10nF 10µF + 8
6.04k BAT2
25V
CTOFF 6
100nF V1
10µF NGATE6 NGATE1 4 BATTERY 1
+
CTBAT 25V 6.04k 6.04k BAT1 BATTERY 2
10nF 2 BATTERY 3
9 BATTERY 4
NGATE1-9 NGATE7
VL 0
27.4k 6.04k TIME
PTC
3305 TA01a
AUXP +
VH 10µF AUX
42.2k 25V
AUXN 6.04k
ISET NGATE8
GND
12.1k
3305 TA01 6.04k
NGATE9

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LTC3305
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
TOP VIEW
Stack Voltage, V4 to GND..........................................68V
Battery Voltages, V4 to V3, V3 to V2, V2 to V1, BOOST 1 38 CM

V1 to GND................................................... –0.3V to 20V V4 2 37 CP

V3 3 36 NC
Auxiliary Cell Voltage, AUXP to AUXN......... –0.3V to 20V
AUXP 4 35 MODE
VREG Voltage................................................. –0.3V to 6V
AUXN 5 34 EN1
VH, VL Voltage...... –0.3V to Lesser of 6V or (VREG+0.3V) V2 6 33 EN2
UVFLT, OVFLT, PTCFLT, BAL, DONE, BATX, V1 7 32 TERM1
BATY Voltage................................................ –0.3V to 6V NGATE1 8 31 TERM2
EN1, EN2, MODE, TERM1, TERM2 NGATE2 9 30 VREG
Voltage................. –0.3V to Lesser of 6V or (VREG+0.3V) NGATE3 10 39 29 ISET
NGATE1, NGATE2, NGATE3, NGATE4, NGATE8, NGATE9 NGATE4 11
GND
28 VH
Voltage............... –0.3V to Lesser of 68V or (V4+0.3V) NGATE5 12 27 VL

NGATE5, NGATE6, NGATE7 NGATE6 13 26 CTBAT

Voltage............... (Greater of –0.3V or BOOST–68V) to NGATE7 14 25 CTON

(BOOST+0.3V)* NGATE8 15 24 CTOFF

UVFLT, OVFLT, PTCFLT, BAL, DONE, BATX, NGATE9 16 23 PTCFLT

BATX 17 22 DONE
BATY Current..........................................................10mA
BATY 18 21 BAL
ISET Current...............................................................1mA
OVFLT 19 20 UVFLT
CP, CM Current.......................................................50mA
Operating Junction Temperature Range FE PACKAGE
38-LEAD PLASTIC TSSOP
(Notes 2, 3)............................................. –40°C to 125°C θJA = 28°C/W
Storage Temperature Range................... –65°C to 150°C EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
NC = No Connect
Lead Temperature (Soldering, 10 sec).................... 300°C
*The BOOST voltage is generated by the LTC3305 and is typically 8.45V higher than V4.

ORDER INFORMATION
(http://www.linear.com/product/LTC3305#orderinfo)

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3305EFE#PBF LTC3305EFE#TRPBF LTC3305 FE 38-Lead Plastic TSSOP –40ºC to 125°C
LTC3305IFE#PBF LTC3305IFE#TRPBF LTC3305 FE 38-Lead Plastic TSSOP –40ºC to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

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 LTC3305
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) V1 = 13.2V, V2 = 26.4V, V3 = 39.6V, V4 = 52.8V,
AUXP - AUXN = 13.2V, RISET = 12.1kΩ
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VBAT Individual Battery Voltage l 4 16 V
V4 Voltage at the Top of the Battery Stack l 12 64 V
VREG Regulator Output Voltage IVREG = 200µA l 2.4 2.5 2.6 V
VREG,UV Regulator Undervoltage Threshold Regulator Voltage Falling l 1.7 2.1 V
Hysteresis 125 mV
Maximum Guaranteed Load Current VREG > VREG,UV l 3 mA
Regulator Short Circuit Current Limit VREG = 0V 8 15 22 mA
Shutdown Current Measured at V4, BOOST-V4 = 0V 16 33 50 µA
Measured at V3, V2, V1, AUXP, BOOST l 0 1 µA
Supply Current While Balancing Battery 1 Measured at V4 900 1350 µA
(Notes 4, 5) Measured at V3 0 1 µA
Measured at V2 0 1 µA
Measured at V1 150 225 µA
Supply Current While Balancing Battery 2 Measured at V4 900 1350 µA
(Notes 4, 5) Measured at V3 0 1 µA
Measured at V2 150 225 µA
Measured at V1 –70 –45 µA
Supply Current While Balancing Battery 3 Measured at V4 900 1350 µA
(Notes 4, 5) Measured at V3 150 225 µA
Measured at V2 –70 –45 µA
Measured at V1 0 1 µA
Supply Current While Balancing Battery 4 Measured at V4 1050 1575 µA
(Notes 4, 5) Measured at V3 –70 –45 µA
Measured at V2 0 1 µA
Measured at V1 0 1 µA
Supply Current While Balancing any Battery Measured at AUXP 165 245 µA
Measured at AUXN –195 –130 µA
Supply Current in OFF State (MODE = 0) Measured at V4, BOOST-V4 = 0V 100 150 µA
Measured at V3, V2, V1, AUXP, BOOST 0 1 µA
Boost Pin Current While Balancing any Battery 220 330 µA
(Notes 4, 5)
VISET ISET Servo Voltage 50µA< IISET< 150µA l 1.18 1.2 1.22 V
IVH, IVL Current Out of VH and VL Pins IISET = 100µA l 31.3 33.3 35.3 µA
INGATE Current For External NMOS Turn On (Note 5) NGATE3 Current, IISET = 100µA l 2.0 2.2 2.4 mA
All Other NGATE Currents, IISET = 100µA l 1.0 1.1 1.2 mA
Leakage Current in Shutdown EN1 = EN2 = 0 l –2 2 µA
Current Programmable Range NGATE3 Current l 1 3 mA
All Other NGATE Currents l 0.5 1.5 mA
VBAT,UV Undervoltage Falling Battery Threshold (Note 6) VL = 0.4V l 3.9 4 4.1 V
VL = 1.6V l 15.6 16 16.4 V
Undervoltage Hysteresis 120 mV
Undervoltage Falling Programmable Range l 4 16 V
VBAT,OV Overvoltage Rising Battery Threshold (Note 6) VH = 0.4V l 3.9 4 4.1 V
VH = 1.6V l 15.6 16 16.4 V
Overvoltage Hysteresis 150 mV
Overvoltage Rising Programmable Range l 4 16 V

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LTC3305
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) V1 = 13.2V, V2 = 26.4V, V3 = 39.6V, V4 = 52.8V,
AUXP - AUXN = 13.2V, RISET = 12.1kΩ
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PTC Fault Threshold |BAT-AUXP| Falling 0.8 1 1.2 V
Hysteresis 100 mV
VTERMINATE |BAT-AUXP| for Which Balancing Is Terminated TERM2 = 0, TERM1 = 0 l 5.0 12.5 20.0 mV
TERM2 = 0, TERM1 = 1 l 17.5 25 32.5 mV
TERM2 = 1, TERM1 = 0 l 40 50 60 mV
TERM2 = 1, TERM1 = 1 l 85 100 115 mV
Minimum (BOOST-V4) Voltage for Operation l 6.7 6.95 7.2 V
Hysteresis 180 mV
Maximum (BOOST-V4) Voltage Regulated l 8.45 8.75 V
Hysteresis 200 mV
RNMOS Charge Pump NMOS Switch ON Resistance Measured at 10mA 20 Ω
RPMOS Charge Pump PMOS Switch ON Resistance Measured at 10mA 55 Ω
tBAT Maximum Time a Single Battery Stays CTBAT = 10nF 4.5 5 5.5 sec
Connected to the Auxiliary Battery
tON Maximum Stack Balancing Termination Time MODE = 0, CTON = 10nF 0.43 0.48 0.53 hrs
tOFF Off Time After Stack Balance Termination MODE = 0, DONE = 0, CTOFF = 10nF 0.43 0.48 0.53 hrs
VIH Digital Input High Voltage EN1, EN2, MODE, TERM1, TERM2 Pins l 1.2 V
VIL Digital Input Low Voltage EN1, EN2, MODE, TERM1, TERM2 Pins l 0.4 V
IIH, IIL Leakage Current EN1, EN2, MODE, TERM1, TERM2 Pins; l –1 1 µA
2.5V at Pin
VOL Output Low Voltage BATX, BATY, BAL, DONE, l 27.5 150 mV
UVFLT, OVFLT, PTCFLT Pins; 3mA Into Pin
IOH Output High Leakage Current BATX, BATY, BAL, DONE, 1 µA
UVFLT, OVFLT, PTCFLT Pins; 6V at Pin
Thermal Shutdown Threshold (Note 7) Rising Temperature 155 °C
Thermal Shutdown Hysteresis 10 °C
Note 1. Stresses beyond those listed under Absolute Maximum Ratings Note 3. Continuous operation above the specified maximum operating
may cause permanent damage to the device. Exposure to any Absolute junction temperature may result in device degradation or failure.
Maximum Rating condition for extended periods may affect device Note 4. The NGATE pin currents are not included in this number.
reliability and lifetime. Note 5. The NGATE5, NGATE6, NGATE7 pin currents are drawn from the
Note 2. The LTC3305 is tested under pulsed load conditions such that TJ BOOST pin. All other NGATE pin currents are drawn from the V4 pin. The
≈ TA. The LTC3305E is guaranteed to meet specifications from 0ºC to 85ºC NGATE pin currents add to the currents drawn by V4 and BOOST.
junction temperature. Specifications over the –40ºC to 125ºC operating Note 6. The voltage programmed at the VH and VL pins are gained up to
junction temperature range are assured by design, characterization and set the undervoltage and overvoltage thresholds of each battery.
correlation with statistical process controls. The LTC3305I is guaranteed
Note 7: This IC includes overtemperature protection intended to protect
over the –40°C to 125°C operating junction temperature range. Note that
the device during momentary overload conditions. The maximum junction
the maximum ambient temperature consistent with these specifications
temperature may be exceeded when overtemperature protection is active.
is determined by specific operating conditions in conjunction with board
Continuous operation above the specified maximum operating junction
layout, the rated package thermal impedance, and other environmental
temperature may result in device degradation or failure.
factors. The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according
to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package
thermal impedance.

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 LTC3305
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

VREG Line and Load Regulation VREG vs Temperature VREG,UV vs Temperature

3.0 2.55 2.5
2.8 2.50 2.4
2.6
2.45 RISING
2.4 2.3
2.2 2.40
2.2
2.0 2.35
1.8 2.1

VREG,UV (V)
FALLING

VREG (V)
2.30
VREG (V)

1.6
2.0
1.4 2.25
1.2 V4 = 12V 2.20 1.9
1.0
2.15 1.8
0.8
0.6 2.10 IVREG = 0.2mA, V4 = 52.8V 1.7
0.4 V4 = 52.8V IVREG = 1mA, V4 = 52.8V
2.05 1.6
0.2 IVREG = 3mA, V4 = 12V
0.0 2.00 1.5
0 3 6 9 12 15 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G01 3305 G02 3305 G03

Shutdown Current vs Temperature OFF State Current vs Temperature VISET vs Temperature

55 125 1.220
120 1.215
50
115
45 1.210
V4 = 64V 110 V4 = 64V
40 105 VISET (V) 1.205
IV4 (µA)
IV4 (µA)

100 V4 = 52.8V 1.200

35
V4 = 52.8V
95 1.195
30 V4 = 12V
V4 = 12V 90
25 1.190
85
20 80 1.185

15 75 1.180
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G04 3305 G05 3305 G06

INGATE vs IISET INGATE vs Temperature UV Threshold vs Temperature

1.8 1.20 5.25
RISET = 12.1k
1.7 ALL NGATE PIN CURRENTS ALL NGATE PIN CURRENTS
5.20 RVL = 15k
1.18 AND NGATE3 CURRENT
1.6 AND NGATE3 CURRENT
2 2 5.15
1.5 1.16
V4 = 52.8V, VNGATE = 0V, RISET = 12kΩ
1.4 V4 = 52.8V, VNGATE = 0V
BATTERY VOLTAGE (V)

1.14 5.10 RISING

1.3
5.05
INGATE (mA)

1.12
INGATE (mA)

1.2
1.1 1.10 5.00
1.0 4.95
1.08 FALLING
0.9
0.8 1.06 4.90
0.7 1.04 4.85
0.6
1.02 4.80
0.5
0.4 1.00 4.75
50 60 70 80 90 100 110 120 130 140 150 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
IISET (µA) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G07 3305 G08 3305 G09

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 LTC3305
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

UV Threshold vs Temperature OV Threshold vs Temperature OV Threshold vs Temperature

10.5 7.70 15.4
RISET = 12.1k RISET = 12.1k RISET = 12.1k
10.4 RVL = 30.1k 7.65 RVH = 22.6k 15.3 RVH = 45.3k
10.3 7.60 15.2

BATTERY VOLTAGE (V)

BATTERY VOLTAGE (V)

10.2 15.1

BATTERY VOLTAGE (V)

7.55 RISING RISING
10.1 RISING 7.50 15.0
10.0 7.45 14.9
9.9 FALLING 7.40 14.8 FALLING
FALLING
9.8 7.35 14.7
9.7 7.30 14.6
9.6 7.25 14.5
9.5 7.20 14.4
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G10 3305 G11 3305 G12

PTC Fault Threshold Maximum Battery Current During

UV and OV Programming Gain vs Temperature PTC Fault Condition
10.5 1200 525
V1 = 13.2V, AUXN = GND V1 = 13.2V, AUXN = AUXP = GND
10.4 1175 515
1150
10.3 505
VBAT,UV/VL or VBAT,OV/VH (V/V)

1125
10.2 RISING 495
1100
|V1-AUXP| (mV)

10.1 UV GAIN 1075 485

IV1 (µA)

10.0 1050 475

9.9 1025 465
OV GAIN FALLING
1000
9.8 455
975
9.7 445
950
9.6 925 435
9.5 900 425
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
VL OR VH (V) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G13 3305 G14 3305 G15

12.5mV Termination Threshold 25mV Termination Threshold 50mV Termination Threshold

vs Temperature vs Temperature vs Temperature
22.5 35 60
20.5 33 58
18.5 31 56
16.5 29 54
VTERMINATE (mV)

VTERMINATE (mV)

VTERMINATE (mV)

14.5 27 52
12.5 25 50
10.5 23 48
8.5 21 46
6.5 19 44
4.5 17 42
2.5 15 40
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G16 3305 G17 3305 G18

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 LTC3305
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

100mV Termination Threshold Minimum Boost Voltage

vs Temperature vs Temperature tON, tOFF vs Temperature
110 7.2 0.510
V4 = 52.8V
108 0.505 CTON = CTOFF = 10nF (COG)
7.1 0.500
106
0.495
104 7.0 RISING 0.490
VTERMINATE (mV)

TIME (HOURS)
VBOOST-V4 (V)
102 0.485
6.9
100 0.480
98 6.8 0.475
FALLING 0.470
96 6.7
0.465
94
0.460
6.6
92 0.455
90 6.5 0.450
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3305 G19 3305 G20 3305 G21

tBAT vs Temperature VOL vs Temperature

5.5 45.0
CTBAT = 10nF (COG) I = 3mA
5.4 42.5
40.0
5.3
37.5
5.2
35.0
TIME (SECONDS)

5.1 32.5
VOL (mV)

5.0 30.0
4.9 27.5
25.0
4.8
22.5
4.7
20.0
4.6 17.5
4.5 15.0
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C)
3305 G22 3305 G23

VREG Start-Up Boost Charge Pump Start-Up

CVREG = 2.2µF
VOLTAGE ACROSS CBOOST
CH2, 0V
5V/DIV

500mV/
DIV
VOLTAGE ACROSS CFLY

0V
CH1, 0V
3305 G24 2V/DIV 3305 G25
100µs/DIV 5ms/DIV

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LTC3305
PIN FUNCTIONS
BOOST (Pin 1): Charge Pump Output. Decouple with a
10µF capacitor to V4.
V4 (Pin 2): Positive terminal of Battery 4 connects to this
pin. Battery 4 is connected between V4 and V3. Decouple
with at least a 10µF capacitor to V3.
V3 (Pin 3): Positive terminal of Battery 3 connects to this
pin. Battery 3 is connected between V3 and V2. Decouple
with at least a 10µF capacitor to V2.
AUXP (Pin 4): Positive terminal of the auxiliary cell con-
nects to this pin. Decouple with at least a 10µF capacitor
to AUXN.
AUXN (Pin 5): Negative Terminal of the auxiliary cell con-
nects to this pin.
V2 (Pin 6): Positive terminal of Battery 2 connects to this
pin. Battery 2 is connected between V2 and V1. Decouple
with at least a 10µF capacitor to V1.
V1 (Pin 7): Positive terminal of Battery 1 connects to this
pin. Battery 1 is connected between V1 and GND. Decouple
with at least a 10µF capacitor to GND.
NGATE1 (Pin 8): NMOS1 Gate. Connect to the gate terminal
of external NMOS switch.
NGATE2 (Pin 9): NMOS2 Gate. Connect to the gate terminal
of external NMOS switch.
NGATE3 (Pin 10): NMOS3 Gate. Connect to the gate ter-
minal of external NMOS switch.
NGATE4 (Pin 11): NMOS4 Gate. Connect to the gate ter-
minal of external NMOS switch.
NGATE5 (Pin 12): NMOS5 Gate. Connect to the gate ter-
minal of external NMOS switch.
NGATE6 (Pin 13): NMOS6 Gate. Connect to the gate ter-
minal of external NMOS switch.
NGATE7 (Pin 14): NMOS7 Gate. Connect to the gate ter-
minal of external NMOS switch.
NGATE8 (Pin 15): NMOS8 Gate. Connect to the gate ter-
minal of external NMOS switch.
NGATE9 (Pin 16): NMOS9 Gate. Connect to the gate ter-
minal of external NMOS switch.
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BATX (Pin 17): This pin along with BATY indicates which
battery in the stack is currently being balanced and to
which the fault outputs apply. Open Drain Output.
BATY (Pin 18): This pin along with BATX indicates which
battery in the stack is currently being balanced and to
which the fault outputs apply. Open Drain Output.
OVFLT (Pin 19): Overvoltage Fault. This pin is pulled low
when an overvoltage fault condition is detected on a bat-
tery. Open Drain Output.
UVFLT (Pin 20): Undervoltage Fault. This pin is pulled
low when an undervoltage fault condition is detected on
a battery. Open Drain Output.
BAL (Pin 21): Balancing Indicator. This pin is pulled low
while the balancing operation is being performed and is
in its high impedance state when the part is disabled or
the part is in the sleep state. Open Drain Output.
DONE (Pin 22): Done Indicator. This pin is pulled low when
all the batteries in the stack are balanced. This pin is in its
high impedance state in shutdown. Open Drain Output.
PTCFLT (Pin 23): PTC Fault. This pin is pulled low when the
voltage across the PTC thermistor exceeds 1V. It is in its
high impedance state at all other times. Open Drain Output.
CTOFF (Pin 24): A capacitor from this pin to GND programs
the retry time in timer mode. Connect to GND if MODE = 1.
CTON (Pin 25): A capacitor from this pin to GND programs
the maximum time for the balancing operation in timer
mode. Connect to GND if MODE = 1.
CTBAT (Pin 26): A capacitor from this pin to GND programs
the maximum time an individual battery in the stack is con-
nected to the auxiliary cell during the balancing operation.
VL (Pin 27): Low Voltage Fault Threshold. A resistor from
this pin to GND programs the low voltage fault threshold
for each battery in the series stack. Works in conjunction
with the ISET pin.
VH (Pin 28): High Voltage Fault Threshold. A resistor from
this pin to GND programs the high voltage fault threshold
for each battery in the series stack. Works in conjunction
with the ISET pin.
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PIN FUNCTIONS
ISET (Pin 29): Reference Current Pin that Servos to 1.2V.
A resistor from this pin to GND programs the gate charge
current for the external NMOS switches. The reference
current is also used to program the undervoltage and
overvoltage thresholds.
VREG (Pin 30): Low Voltage Regulated Output. An inter-
nally generated voltage of 2.5V is always present at this
pin. The voltage at this pin may be overdriven by a higher
external voltage up to 5.5V. This pin has limited current
sink capability and will not pull down a higher externally
applied voltage. All logic input pins must be referenced to
this pin. Decouple with a 1µF capacitor to GND.
TERM2 (Pin 31): Termination Threshold Select. This pin
along with TERM1 is used to set the voltage difference
between the battery and auxiliary cell at which a battery is
deemed balanced. High input impedance pin, do not float.
TERM1 (Pin 32): Termination Threshold Select. This pin
along with TERM2 is used to set the voltage difference
between the battery and auxiliary cell at which a battery is
deemed balanced. High input impedance pin, do not float.
EN2 (Pin 33): Enable Input. The state of the EN1 and EN2
pins is used to indicate the number of batteries in the stack.
With both pins at GND, the part is in shutdown. High input
impedance pin, do not float.
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LTC3305
EN1 (Pin 34): Enable Input. The state of the EN1 and EN2
pins is used to indicate the number of batteries in the stack.
With both pins at GND, the part is in shutdown. High input
impedance pin, do not float.
MODE (Pin 35): Mode Select. When held high, continuous
mode is selected. When held low, timer mode is selected.
High input impedance pin, do not float.
No Connect (Pin 36): This pin is not connected internally.
Solder this pin to a pad electrically isolated from all other
circuit nodes.
CP (Pin 37): Positive Terminal of Charge Pump Flying
Capacitor. Connect a 10µF capacitor from this pin to CM
for charge pump operation.
CM (Pin 38): Negative Terminal of Charge Pump Flying
Capacitor. Connect a 10µF capacitor from this pin to CP
for charge pump operation.
GND (Pin 39): The exposed pad is ground and must be
soldered to PCB ground for electrical connectivity and
rated thermal performance.
3305fb
9
LTC3305
BLOCK DIAGRAM
BOOST
1

GATE DRIVE NO CONNECT 36

CP
CHARGE 37
PUMP CM
38

NGATE1
8
NGATE2
9
MUX NGATE3
10
V4
2 NGATE4
11
V3 NGATE5
3 12
NGATE6
V2 13
6
NGATE7
14
V1
7 NGATE8
15
NGATE9
16

MIRROR V4

LOW VREG
VOLTAGE 30
BANDGAP REGULATOR
1.2V +
REFERENCE
–
ISET
29

EN2
33
EN1
34
VH
28 MODE
UV/OV 35
VL
27 BATX
17

TERM2 BATY
31 18
TERMINATION CONTROL
TERM1 SENSE LOGIC
32 OVFLT
COMPARATOR 19
AUXP
4
UVFLT
AUXN 20
5

CTOFF BAL
24 21

CTON DONE
25 TIMERS 22
CTBAT
26 PTCFLT
23
THERMAL
SHUTDOWN OT

39
3305 BD
GND

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 LTC3305
OPERATION
The LTC3305 balancer is intended to be used in conjunc- NGATE5
tion with a separate pre-existing battery stack charger as 9
part of a high performance battery system. The balancing NGATE1-9

operation itself is stand-alone and can operate independent N5

NGATE4 +
of whether the battery stack is being charged, discharged, NGATE6 BAT4
or both. That being said, because the LTC3305 balances
voltages, it works best if the voltage readings are stable, LTC3305
N4
NGATE3
N6 +
which is more true when the battery stack is not being NGATE7 BAT3

charged or discharged. Nevertheless, it will properly bal-

N3A N3B
ance the battery voltages when the stack is being concur- PTC NGATE2
N7 +
rently charged and/or discharged, since the voltage across AUXP +
BAT2

the batteries will average out over time as the LTC3305 AUX N8
AUXN N2
repeatedly cycles through them. Like all balancers, the
LTC3305 will slightly net-discharge the stack in the absence NGATE8 NGATE1 +
of a separate charger. N9 BAT1

The LTC3305 balances batteries using an auxiliary cell or an N1

NGATE9
alternate storage cell as a charge reservoir. External NMOS
switches are controlled in a preprogrammed sequence
3305 F01

to connect each battery in the stack to an auxiliary cell. Figure 1. External Switch Arrangement
Charge is transferred to or from the auxiliary cell when it for a 4- Battery Balancing Application
is connected to a battery.
The LTC3305 can operate in one of two modes program- The balancing operation begins with the negative terminal
mable via the MODE pin. of the auxiliary cell connected to the negative terminal of
BAT1, the lowest battery in the stack. Referring to Figure 1,
Timer Mode (MODE = 0) the bottom switches N1 and N9 that connect the negative
The balancing operation begins once the CBOOST capacitor terminal of BAT1 to the auxiliary cell’s negative terminal are
is charged to at least 6.95V. The BAL pin is pulled low, first turned on. To turn on an external NMOS switch, the
indicating that the part is enabled and balancing the bat- current source at the NGATE pin connected to the gate of
tery stack. the external NMOS is turned on and a gate source voltage
is developed across an external resistor.
The termination voltage, VTERMINATE, is the difference in
voltage between the auxiliary cell and the battery connected After an internally set delay of 35ms, the voltages across
to the auxiliary cell for which a battery is considered to the auxiliary cell and BAT1 are compared by the termina-
be balanced. VTERMINATE is programmed via the TERM1 tion sense comparator.
and TERM2 pins to one of four preset voltages as shown If the voltage difference between the auxiliary cell and BAT1
in Table 1. is less than the selected termination voltage, the battery
Table 1. Termination Voltages is deemed to be balanced with respect to the auxiliary cell
TERM1 TERM2 VTERMINATE and the bottom switches are turned off by turning off the
0 0 ±12.5mV corresponding NGATE pin currents. The next battery in
1 0 ±25mV the stack is then connected to the auxiliary cell.
0 1 ±50mV
1 1 ±100mV

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LTC3305
OPERATION
If the voltage difference between the auxiliary cell and In this fashion each battery in the stack is connected to the
BAT1 is greater than the selected termination voltage, the auxiliary cell and the batteries in the stack will be balanced.
top NMOS switches N2 and N7 that connect the positive
An internal clamp circuit protects the LTC3305 when the
terminal of BAT1 to the auxiliary cell’s positive terminal
voltage difference between the battery being balanced
through the PTC thermistor are turned on. After a second
and the auxiliary cell is greater than 1V. With a 13.2V
internally set delay of 35ms, the termination sense com- difference, the clamp draws 475µA of current. In the worst
parator starts monitoring the voltages across the auxiliary case scenario, a 16V difference may appear between the
cell and the battery. The battery stays connected to the auxiliary cell and a battery. The internal clamp draws 600µA
auxiliary cell until the voltage difference decreases to of current in this scenario.
VTERMINATE or a tBAT timeout occurs (tBAT is the maximum
time that a battery remains connected to the auxiliary cell In the state when both the top and bottom side switches
and is programmed by a capacitor on the CTBAT pin). This are turned on, the PTCFLT pin will be pulled low if the
timer is reset each time the auxiliary cell is connected to voltage difference between the battery being balanced and
a different battery. the auxiliary cell is greater than 1V. If during the balancing
operation the voltage difference becomes less than 1V, the
At this point, all switches are turned off and the next bat-
PTCFLT pin returns to its high impedance state.
tery in the stack is connected to the auxiliary cell. After
the switches have been turned off, an internal 40ms delay The BATX and BATY pins indicate which battery in the
provides a break-before-make time after which the nega- stack is currently connected to the auxiliary cell as shown
tive terminal of the next battery in the stack is connected in Table 3. In shutdown, the BATX and BATY pins are in
to the negative terminal of the auxiliary cell via its bottom a High Z state and the BAL pin is also in a High Z state.
switches. Table 2 shows the top and bottom switches Table 3. State of BATX and BATY Pins
used to connect each battery for different battery stack STATE OF OPERATION BATX BATY
configurations. When only the bottom switches are on, Battery 1 Connected High Z High Z
there is a conduction path between the auxiliary cell and Battery 2 Connected High Z 0
the battery through the body diodes of the top switches. Battery 3 Connected 0 0
Current will flow through this conduction path if the aux- Battery 4 Connected 0 High Z
iliary cell and the battery are more than two diode drops
apart. The current is limited by the PTC resistor.
Once all batteries in the stack are balanced the DONE pin
Table 2. Top and Bottom Switch Arrangement is pulled low, the BAL pin is in its high impedance state
BATTERY BEING TOP BOTTOM and the part is put in a low power OFF state.
EN1, EN2 BALANCED SWITCHES SWITCHES
1,1 Battery 1 N2, N7 N1, N9 A four-battery stack is deemed balanced when the ter-
(4 Bat App) Battery 2 N3, N6 N2, N8 mination sense comparator detects VTERMINATE on five
Battery 3 N4, N7 N3, N9 consecutive cycles that connect each of the batteries to
Battery 4 N5, N6 N4, N8 the auxiliary cell using the bottom switches only.
1,0 Battery 1 N2, N7 N1, N8
(3 Bat App) Battery 2 N4, N6 N2, N9
Battery 3 N5, N7 N4, N8
0,1 Battery 1 N7 N9
(2 Bat App) Battery 2 N5 N8

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OPERATION
In timer mode, a capacitor at the CTON pin programs the
maximum time, tON, that the balancing operation can run
for. The balancing operation is terminated either when the
batteries in the stack are deemed to be balanced or a tON
time out occurs. After the balancing operation has been
terminated, the LTC3305 is put in a low power OFF state
for a fixed time, tOFF. The tOFF time is programmed by a
capacitor at the CTOFF pin. In the OFF state, the BAL pin
is put in its high impedance state. Once tOFF times out,
the LTC3305 is put back in its ON state and the balancing
operation begins again. The tON timer may be defeated by
tying the CTON pin to GND. In this scenario, the LTC3305
will enter the OFF state only when all the batteries in the
stack are deemed to be balanced.
Continuous Mode (MODE = 1)
In the continuous mode of operation the part functions in
much the same way as in timer mode with the following
differences.
1. There is no ON or OFF state. The CTON and CTOFF pins
must be tied to GND in continuous mode. The balanc-
ing operation continues even if the stack is in balance.
The balancing operation is terminated only if the part
is put in shutdown. The BAL pin is always pulled low
in continuous mode.
LTC3305
voltages could differ by up to twice the programmed
VTERMINATE when balanced.
Charge Pump Operation
The LTC3305 uses external NMOS devices as switches to
connect a battery to the auxiliary cell. The LTC3305 has a
charge pump that generates the higher voltage required
to turn on some of the external NMOS switches.
Two external capacitors CFLY and CBOOST, two diodes D1
and D2, and resistors R1 and R2 are required for charge
pump operation as shown in Figure 2. When the LTC3305
is enabled, the charge pump is turned on. CFLY initially
charges with a current ICHG through external diode D1,
resistor R1, and the internal NMOS switch N1 to GND. When
CFLY is charged to 10.5V, an internal comparator switches
the internal NMOS switch off and turns on switch P1. CFLY
connects to CBOOST through diode D2, resistor R2 and the
internal PMOS switch P1. Charge is transferred from CFLY
to CBOOST with a current IDISCHG. When CFLY is discharged
to 9.5V, it is disconnected from CBOOST, recharged back up
to 10.5V, and then reconnected to CBOOST. In this fashion
the voltage across CBOOST is built up.
ICHG
D1

2. In timer mode, if the termination comparator senses R1 IDISCHG

that a battery is balanced to the auxiliary cell with only

the bottom plates connected, the balancing operation CFLY

on that battery is terminated. This is not the case in CM CP D2

continuous mode. In continuous mode the top switches P1 R2

BOOST
are turned on and the balancing operation on a battery N1
is terminated only by a tBAT time out. Since the auxiliary CBOOST

cell remains connected to the battery until a tBAT time V4

out occurs, its voltage can change before it connects

to the next battery in the stack. As a result, when the LTC3305

stack is balanced and the DONE pin is pulled low, the

voltages across the individual batteries in the stack
may differ by more than the programmed VTERMINATE.
In the worst case when the capacity of the auxiliary cell 3305 F02

is much smaller than the battery, the individual battery Figure 2. Charge Pump Operation

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LTC3305
OPERATION
Once the CBOOST capacitor has 6.95V across it, balancing
begins. When CBOOST is charged to 8.45V, the charge
pump operation is disabled and CFLY remains connected
to CBOOST. Charge pump operation resumes when CBOOST
discharges to 8.25V.
Undervoltage and Overvoltage Fault Detection
The undervoltage and overvoltage thresholds can be
programmed using the resistor at the ISET pin in con-
junction with resistors at the VL and VH pins. The voltage
present at the VL or VH pin programs the corresponding
fault threshold to 10× that voltage for each battery in the
stack. An internal amplifier accurately gains up the voltage
at the VL and VH pins and shifts the threshold voltage to
the appropriate battery common mode level. The VL and
VH pins have a programming range from 0.4V to 1.6V.
The internal undervoltage and overvoltage comparators
may not trip correctly for a program voltage outside this
range. An internal clamp prevents the thresholds from
being programmed to greater than 20V.
When an undervoltage or overvoltage fault condition is
detected, the corresponding UVFLT or OVFLT pin is pulled
to GND. The balancing operation is not interrupted during
this time. If an undervoltage or overvoltage fault condition
goes away during the balancing operation, the correspond-
ing fault pin returns to its high impedance state.
If the undervoltage and overvoltage fault detection is not
needed, the VL and VH pins must be tied to GND. The UVFLT
and OVFLT pins may either be tied to GND or left floating.
Low Voltage Regulator
The LTC3305 has an always on regulator that provides
2.5V at the VREG pin. The VREG pin may be driven externally
up to 5.5V. The VREG pin cannot sink current and will not
pull down an externally applied voltage. The regulator can
source up to 3mA of current. If more than 3mA of current
14 For more information www.linear.com/LTC3305
is drawn from the regulator, the VREG voltage will drop
below its undervoltage threshold, disabling the LTC3305
and terminating the balancing operation. The balancing
operation restarts when the regulator recovers from its
undervoltage state. In short circuit, the VREG current is
limited to 15mA. The VREG pin should be decoupled with
at least a 1µF capacitor to GND.
Thermal Shutdown
The LTC3305 has an overtemperature detect circuit that
shuts down the balancing operation when the internal
silicon junction temperature exceeds 155°C. The LTC3305
resumes balancing when the temperature drops to 145°C.
In thermal shutdown, the low voltage regulator remains
powered.
Balancing Battery Stacks with Two or Three Batteries
The LTC3305 can also be configured to balance battery
stacks of two or three batteries. The state of the enable pins
tells the LTC3305 to select the correct switch sequencing.
For a two battery stack, the LTC3305 must be enabled
with EN1 = 0 and EN2 = 1. For a three battery stack, the
LTC3305 must be enabled with EN1 = 1 and EN2 = 0. The
external NMOS switch arrangements for a two-battery
and three-battery application are shown in Figures 3 and
4 respectively. If pin NGATE6 is unused, it must be con-
nected to the BOOST pin. All other unused NGATE pins
must be connected to V4 as shown in Figures 3 and 4.
A two battery stack is deemed balanced if the termination
sense comparator senses the voltage difference between
the auxiliary cell and the battery is less than VTERMINATE
on three successive cycles when the auxiliary cell and a
battery are connected using only the bottom switches.
In the case of a three battery stack, four successive cycles
are required to deem the stack balanced.
3305fb
 LTC3305
OPERATION
10µF
25V

ALL NMOS DEVICES = SiR882DP

D2 D1, D2 = CMMSH1-100

249Ω 1.33k
CM CP
VREG BOOST
1µF D1
EN1
6V NGATE6
EN2
MODE
22µF
25V
TERM1
TERM2
UVFLT V4
4
OVFLT NGATE1-4 NGATE5
DONE 6.04k
V3
100k EACH BAL
PTCFLT LTC3305
BATX V2
10µF +
BATY BAT2
CTON 25V
10nF V1
10µF
+
25V BAT1
CTOFF
100nF
4 NGATE7
CTBAT NGATE5, 7, 8, 9 6.04k
22nF

VL PTC
27.4k AUXP
+
10µF
AUX
25V
VH
42.2k AUXN 6.04k
NGATE8
ISET GND
12.1k 3305 F03
6.04k
NGATE9

Figure 3. Two-Battery Application Showing External Switch Arrangement

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LTC3305
OPERATION
10µF
25V

ALL NMOS SWITCHES = SiR882DP

D2 D1, D2 = CMMSH1-100

249Ω 1.33k
CM CP
VREG BOOST
1µF D1
EN1
6V EN2 10µF
25V
MODE V4
NGATE5
6.04k
TERM1
TERM2 NGATE3
UVFLT V3
OVFLT
NGATE4 +
DONE 10µF 6.04k BAT3
100k EACH BAL 25V
PTCFLT LTC3305
BATX V2
BATY NGATE2
10µF +
CTON 6.04k BAT2
10nF 25V

V1
CTOFF
10µF NGATE6
100nF NGATE1
25V +
6.04k 6.04k BAT1
CTBAT
22nF
8 NGATE7
VL NGATE1, 2, 4-9
27.4k 6.04k
PTC
VH AUXP +
42.2k 10µF AUX
25V
ISET AUXN
GND 6.04k
12.1k 3305 F04
NGATE8

6.04k

NGATE9

Figure 4. Three-Battery Application Showing External Switch Arrangement

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16 For more information www.linear.com/LTC3305

 LTC3305
APPLICATIONS INFORMATION
Selecting the PTC Thermistor PTC Current Voltage Characteristics

A PTC thermistor is a type of resistor with a Positive Tem-

perature Coefficient that serves as a protection device by CURIE POINT

limiting its current above a certain threshold. The PTC device

limits the peak current that transfers charge between the

CURRENT →
auxiliary cell and the battery. When the voltage across the
PTC is small, the power dissipated in the PTC is small and
the PTC resistance remains constant. As the voltage across
the PTC increases, power dissipation in the PTC increases
which causes the PTC temperature to rise. When the tem-
perature reaches the Curie Temperature, further increases
VOLTAGE →
in voltage will cause the PTC resistance to increase rapidly, 3305 F05a

which limits the current through the device and thus limits (a)
the power dissipation in the PTC. This behavior is shown
in the PTC Current Voltage Characteristics in Figure 5a. In
Increasing Current at Large Voltage
this fashion the PTC serves to protect the external NMOS
switches from operating outside of their SOA region.
As seen in the PTC Current Voltage Characteristics in Figure PTC RESISTOR IN PARALLEL
5a, when the PTC has a small voltage or a high voltage WITH A RESISTOR

across it, the current flowing through it is small. For small

CURRENT →

SINGLE PTC RESISTOR

voltages, this is OK since the battery and the auxiliary cell RESISTOR ONLY

are close to balance. For high voltages, this slows down

balancing. To increase balance currents at high voltages
a power resistor can be placed in parallel with the PTC
device, as shown in Figure 5b. Additionally, multiple PTC
resistors may be connected in parallel to increase current VOLTAGE →
3305 F05b

flow at all voltages.

(b)
PTC devices are manufactured in two styles: ceramic and
poly fuse. Only a ceramic style PTC device should be used Figure 5. PTC Behavior
in this application. Poly fuse devices have a very limited
number of lifetime trip cycles and are not suitable in a Table 4. Recommended Ceramic PTC Thermistors
balancing application. RESISTANCE
PART NUMBER MANUFACTURER VOLTAGE (Ω)
The PTC must be selected such that power dissipation PTGL7SARR47M1B51B0 Murata 16V 0.47
through the external NMOS switches never exceeds their
PTGLASARR27M1B51B0 Murata 16V 0.27
rated SOA power dissipation value. Refer to Table 4 for a
PTGLESARR15M1B51B0 Murata 16V 0.15
list of recommended PTC thermistors.
PTGL12AR1R2H2B51B0 Murata 30V 1.2
2381 663 51121 Vishay 30V 0.7
2381 663 51321 Vishay 30V 0.5
2381 664 52021 Vishay 30V 0.3

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LTC3305
APPLICATIONS INFORMATION
Selecting the Auxiliary Cell
The auxiliary cell must be capable of sourcing and sink-
ing current and withstand the maximum voltage of any
individual battery in the stack. The ESR of the auxiliary
cell must be small compared to the PTC thermistor. Any
voltage dropped across the auxiliary cell ESR appears as
an offset voltage at the input of the termination comparator.
The auxiliary cell used may be a lead-acid battery, a stacked
supercapacitor, or a low leakage, high voltage capacitor.
When using a supercapacitor stack, the voltage across
each individual supercapacitor must not exceed its rated
operating voltage.
Figure 6a shows a battery stack made of 4 batteries,
each with a nominal capacity of 50Ah, but with a 10%
capacity mismatch. With no balancing, the stack capacity
is determined by the weakest battery in the stack and is
limited to 45Ah.
In Figure 6b, a small capacity auxiliary cell, such as a
supercapacitor stack, is used to balance the battery stack.
When balanced the stack capacity can be made to approach
the nominal capacity of 50Ah despite the 10% mismatch.
In Figure 6c, the auxiliary cell has the same capacity as
the batteries in the stack. Each of the batteries in Figure 6c
has a nominal capacity of only 40Ah but the stack capac-
ity approaches 50Ah since the auxiliary cell supplements
the capacity of the battery stack. Using a large capacity
auxiliary cell supplements stack capacity. Smaller capac-
ity batteries may be used in the stack which helps reduce
system costs.
Precharging the Auxiliary Cell
When using stacked supercapacitors or a single high volt-
age capacitor as the auxiliary cell, the auxiliary cell may
be initially discharged with a voltage of 0V. At startup, a
large voltage exists across the PTC resistor, which will
cause the PTC resistance to increase. This limits the cur-
rent and hence the charge transfer between the auxiliary
cell and the battery it is connected to. The auxiliary cell
will be charged very slowly with an indeterminate time,
as it sequentially connects to each battery in the stack.
Once the auxiliary cell has been charged to a point where
the PTC device operates as a low resistance device, the
balancing process is sped up.
A more time efficient solution is to precharge the auxiliary
cell to the average voltage of the batteries in the stack. Figure
7a shows a circuit using a high voltage buck regulator to
precharge the auxiliary cell to V4/4 volts. NMOS devices
N2A and N2B eliminate a parasitic charging path from
BATTERY1 to the auxiliary cell when AUXN is connected
to GND through N10. Figures 7b and 7c are scope photos
showing a complete precharging and balancing operation.

55Ah 55Ah 44Ah

(+10%) (+10%) (+10%)

50Ah 50Ah 40Ah

PTC PTC
50Ah 50Ah 40Ah
4Ah 40Ah
45Ah 45Ah (AUX) 36Ah (AUX)
(–10%) (–10%) (–10%)

STACK CAPACITY STACK CAPACITY STACK CAPACITY

=45Ah ≈50Ah ≈50Ah
(a) (b) (c)

Figure 6. Increasing Stack Capacity with an Auxiliary Cell

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 LTC3305
APPLICATIONS INFORMATION
D1, D2 = CMMSH1-100 N1A, N1B, N2, N3A, N3B, N4, N5, N6, N7, N8, N9, N10 - SiR882DP
D3 = CMMSH2-80

10µF D2
1.33k
25V
249Ω
CM CP NGATE5
VREG BOOST
1µF 10µF D1 6.04k
TERM1
6V 25V
TERM2
N5
MODE V4
NGATE4
+
10µF 6.04k BAT4
EN1
25V
EN2 N4
UVFLT V3
3.01k 2.2µF
OVFLT NGATE3
DONE + 100V
10µF BAT3
BAL 25V
PTCFLT N3A N3B VIN
SS RUN
BATX V2
6.04k FBO ISET
BATY LTC3305 NGATE2 SW
CTON 10µF + 174k
BAT2 LTC3630A
10nF 25V
VPROG1
N2A N2B
V1 FB VPROG2
GND
CTOFF 10µF 6.04k
100nF NGATE6 NGATE1
25V +
6.04k BAT1
CTBAT
10nF 9 N6 N1
NGATE1-9 6.04k
NGATE7
VL
27.4k N7
PTC D3 100µH
VH AUXP
42.2k N8
10µF + 5.11M
25V AUX 6.04k D4, D5, D6 = 1N914 V+
ISET IN– OUT
AUXN NGATE8 D4 REF
12.1k GND N9 365k
2.21M LTC1440 40.2k
D5
6.04k IN+ HYST
D6
NGATE9
2.21M 365k 2.43M
N12 V– GND
N10
S N11
D Q 681k
CLK
START
Q N11, N12 = FDV301N
R
3305 F07

(a)

BAT1, BAT2, BAT3, BAT4, AUXP-AUXN = 2V/DIV AUXP-AUXN = 2V/DIV

AUXN = 10V/DIV; START, EN_3305 = 5V/DIV AUXN = 10V/DIV; START, EN_3305 = 5V/DIV
TIME = 20s/DIV TIME = 5s/DIV
(b) (c)
Figure 7. Precharging the Auxiliary Cell Using the LTC3630A and LTC1440
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LTC3305
APPLICATIONS INFORMATION
Selection of External NMOS Switches the NMOS device. Programming a higher current reduces
the NMOS device turn on time. Programming a large gate
The external NMOS switches must be capable of with-
source voltage reduces the on resistance of the NMOS
standing a reverse voltage equal to the battery stack volt-
device. During turn off, the gate capacitor discharges
age. They should also be capable of carrying DC current
through the gate source resistor.
up to the PTC thermistor trip point. The maximum power
dissipated in the NMOS should not cause it to operate Programming Undervoltage and Overvoltage
outside of its Safe Operating Area. Refer to Table 5 for a Thresholds
list of recommended NMOS switches.
Referring to the Block Diagram, the voltage at the ISET pin
Table 5. Recommended NMOS Switches is servoed to 1.2V. An external resistor, RISET, from this
PART NUMBER MANUFACTURER IDS(MAX) VDC(MAX) pin to GND programs a current which is divided down and
SiR882DP Vishay 60A 100V mirrored to the VL and VH pins. The ISET pin current has
SiS892DN Vishay 25A 100V a programmed range from 50µA to 150µA.
IPD70N10S3-12 Infineon 70A 100V
The ISET pin current is given by:
IPB35N10S3L-26 Infineon 35A 100V
RJK1051DPB Renesas 60A 100V 1.2V
I ISET =
RJK1054DPB Renesas 92A 100V RISET
The current out of the VL and VH pins is given by:
Programming NMOS Turn On I ISET
IVL = IVH =
The NMOS switches are turned on by developing a voltage 3
across an external resistor from the gate to the source. External resistors RVL from the VL pin to GND and RVH
The current through the resistor is delivered from the from the VH pin to GND program the undervoltage and
NGATE pins and is programmed by the current at the overvoltage thresholds for each battery. The undervolt-
ISET pin. The internal current sources that provide the age threshold for a battery is given by:
NGATE pin currents operate from the V4 and BOOST R
supplies as shown in the Block Diagram. The BOOST VBAT,UV = 4V • VL
RISET
pin voltage is regulated at 8.45V greater than V4. It is
recommended that the gate turn on voltage be set to no The overvoltage threshold for a battery is given by:
more than 7.5V. The current flowing through the gate R
VBAT,OV = 4V • VH
turn on resistor connected to the NGATE3 pin is given by: RISET
26.4V Programming the tBAT Parameter
I NGATE3 =
RISET The tBAT parameter is programmed using a capacitor
The current flowing through the other NGATE pins is from the CTBAT pin to GND. tBAT is given by:
given by: C
13.2V tBAT = 5sec• TBAT
I NGATE = 10nF
RISET A C0G type capacitor is recommended due to its superior
The NGATE3 current has a programmed range from 1mA temperature characteristics.
to 3mA. All other NGATE currents have a programmed Programming the tON and tOFF Parameters
range from 500µA to 1.5mA.
The tON parameter is programmed by a capacitor from
The NGATE current initially charges the gate capacitor of the CTON pin to GND. tON is given by:
the NMOS device to turn it on. The external gate source CTON
resistor maintains a constant gate to source voltage on tON = 0.48hrs•
10nF
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20 For more information www.linear.com/LTC3305


APPLICATIONS INFORMATION
The tOFF parameter is programmed by a capacitor from
the CTOFF pin to GND. tOFF is given by:
C an external switching regulator generates a 3.3V rail that
tOFF = 0.48hrs• TOFF
10nF
C0G type capacitors are recommended due to their superior
temperature characteristics.
In the continuous operation mode (MODE = 1), the CTON
and CTOFF pins are unused and should be connected to
GND.
Selecting Charge Pump Components
Referring to Figure 2, recommended values for R1, R2
and CFLY are 249Ω, 1.33k & 10µF respectively for all ap-
plications. For applications in which V4 is no lower than
32V a 10µF capacitor is recommended for CBOOST. For
applications which may have lower voltages at V4, the
recommended value for CBOOST is 22µF. Schottky diodes
with a breakdown voltage larger than the maximum V4
voltage are recommended for diodes D1 and D2.
Selecting Decoupling Capacitors
Decoupling capacitors of at least 10µF must be placed
across each battery, from the BOOST pin to V4 and from
the AUXP pin to the AUXN pin. These capacitors must be
placed as close as possible to the LTC3305. The capacitors
must be capable of withstanding the maximum voltage
across each battery. Capacitors with an X5R or X7R type
dielectric should be used.
Thermal Considerations and Limiting On-Chip Power
Dissipation
Excessive on-chip power dissipation will cause the
LTC3305 to enter thermal shutdown. It is important to
understand the source of the power dissipation and how
power dissipation can be reduced. The two contributions
of on-chip power dissipation on the LTC3305 that may be
controlled by the user are the loading on the low voltage
regulator and the power dissipated through the current
sources that provide the NGATE pin currents.
The low voltage linear regulator provides a 2.5V output.
Any current provided by the regulator will cause power
For more information www.linear.com/LTC3305
LTC3305
dissipation in the internal switch connected from V4 to
VREG, which causes die temperature to increase. In Figure 8,
back drives the VREG pin and provides power to the external
microprocessor and other low voltage circuits. There is
no on-chip loading on the VREG pin and thus no on chip
power dissipation in the low voltage regulator.
In Figure 8, external resistors R1, R2, R3, R4, and R5 are in
series with the on-chip current sources that provide NGATE
pin current. These resistors reduce the voltage across the
on-chip current sources and thus reduce on-chip power
dissipation. As an example, the current source at NGATE1
delivers current from the V4 pin. When this current source
is turned on, the voltage across it is V4-VNGATE1. For a
typical application with V4 = 52.8V, programmed INGATE =
506µA and VNGATE1 = 6.12V, the on-chip power dissipated
in the current source is 23mW. In Figure 8, resistor R1
operates with approximately 30.5V across it. The on-chip
power dissipated in the current source is reduced to ap-
proximately 8mW. In similar fashion resistors R2, R3,
R4, and R5 reduce the on-chip power dissipation on the
respective current sources. When choosing these resistors
it is recommended to have the internal current sources
biased with at least 6V across them under all operating
conditions. Power dissipation through the on-chip current
sources may be further reduced by programming a lower
gate current through the NGATE pins.
Balancing Battery Stacks with more than Four Batteries
To balance battery stacks that have more than four batter-
ies, multiple LTC3305 devices may be stacked together. In
this scenario, it is recommended that each LTC3305 be
run in continuous mode and at least one battery in each
sub-stack of four is common to two LTC3305s. Each
LTC3305 needs an auxiliary cell for the balancing opera-
tion. Figure 9 shows an eight battery stack being balanced
using three LTC3305 devices connected together. Figure
10 shows a stack of six batteries being balanced using
two LTC3305 devices. To balance a battery stack with
n batteries, the minimum number of LTC3305 devices
required is [(n-1)/3] rounded up to the nearest integer.
In this calculation, each LTC3305 is assumed to be used
in a four-battery configuration and at least one battery
interleaves two LTC3305 devices.
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21
LTC3305
APPLICATIONS INFORMATION
When multiple LTC3305 devices are stacked, the logic out-
put pins may need to be level shifted and ground referred.
In Figure 9, optical isolators are used for level shifting.
Figure 11 shows an application in which an eight battery
stack is balanced using two LTC3305 devices and two
auxiliary cells. BAT1, BAT2, BAT3, and BAT4 are balanced
to each other using the lower LTC3305 whereas BAT5,
BAT6, BAT7, and BAT8 are balanced to each other by the
upper LTC3305.
The no-connect pin on the LTC3305 must be soldered to
a pad on the PCB and must be electrically isolated from
any other circuit node.
The trace that connects the AUXP pin to the positive
terminal of the auxiliary source must be as close to the
auxiliary source positive terminal as possible. Otherwise
the trace impedance adds to the ESR of the auxiliary cell
which manifests itself as an offset at the internal termina-
tion comparator.

PCB Considerations
In operation the LTC3305 can dissipate large amounts
of power which can increase die temperature and cause
the part to enter thermal shutdown. The exposed pad of
LTC3305 must be well soldered to the PCB to provide
adequate heat sinking. The exposed pad also provides an
electrical GND to the LTC3305.
10µF
25V
The V1, V2, V3 and V4 traces must be Kelvin connected
directly to the battery terminal and must not share a com-
mon trace through which high balance current will flow.
Any voltage drop in these traces also manifests itself as
an offset voltage at the termination comparator input.
ALL NMOS SWITCHES = SiR882DP
D1, D2 = CMMSH1-100

D2

249Ω
LTC3630A 3.3V CM CP 1.33k NGATE5
VREG BOOST
BUCK REGULATOR 10µF 12.1k
EN1
EN2 25V
D1
MODE V4
100k EACH TERM1 NGATE4
+
TERM2 10µF 12.1k BAT4
25V
UVFLT V3
OVFLT 6.04k 10k
DONE NGATE3
R3 +
MICROPROCESSOR BAL 10µF BAT3
PTCFLT 25V
BATX
V2
BATY 12.1k 37.4k
LTC3305 NGATE2
10µF R2 +
CTON 25V BAT2
10nF
V1
CTOFF 10µF 12.1k 60.4k
12.1k
100nF 25V NGATE6 NGATE1
R1 +
9 BAT1
CTBAT NGATE1-9
10nF 12.1k 12.1k
NGATE7
VL R4
59k
PTC = PTGL13AROR8H2B71B0
VH AUXP +
93.1k 10µF AUX 12.1k
25V
AUXN NGATE8
ISET
GND
23.7k
12.1k 20k
NGATE9 3305 F08

R5

Figure 8. 4-Battery Application with External Resistors to Limit Power Dissipation

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22 For more information www.linear.com/LTC3305

 LTC3305
APPLICATIONS INFORMATION
100k 100k 100k 100k 100k 100k 100k

10µF ALL NMOS DEVICES = SiR882DP

TO 25V D1, D2, D3, D4, D5, D6 = CMMSH1-100
µP

D6
2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k CM CP
VREG 249Ω 1.33k
NGATE5C
EN1 BOOST
EN2 10µF D5 5.49k
1µF
MODE 25V
6V V4
TERM1 +
CPC1301G TERM2 10µF NGATE4C BAT8
25V 5.49k
UVFLT V3
OVFLT
DONE 2.74k +
10µF NGATE3C BAT7
BAL
25V
PTCFLT
BATX
BATY V2
+
LTC3305 NGATE2C BAT6
10µF
CTON 5.49k
25V
V1
CTOFF
10µF NGATE6C NGATE1C
10nF
25V 5.49k 5.49k
CTBAT 9 NGATE1C-9C
NGATE1-9
20k NGATE7C
VL 5.49k
PTC
32.4k AUXP
VH +
10µF AUX3
25V +
5.49k BAT5
8.06k AUXN NGATE8C
ISET

GND 5.49k
100k 100k 100k 100k 100k 100k 100k
NGATE9C

10µF
TO 25V
µP

D4
2.43k 2.43k 2.43k 2.43k 2.43k 2.43k 2.43k CM CP
VREG 249Ω 1.33k
NGATE5B
EN1 BOOST
1µF EN2 10µF 5.49k
D3
6V MODE 25V
TERM1 V4
CPC1301G TERM2 NGATE4B
10µF 5.49k
25V
UVFLT
OVFLT V3
DONE 2.74k
BAL 10µF NGATE3B
PTCFLT 25V
BATX
BATY V2
LTC3305 NGATE2B
10µF
CTON 25V 5.49k

V1
CTOFF
10µF NGATE6B NGATE1B
10nF 25V
5.49k 5.49k +
CTBAT 9 NGATE1B-9B BAT4
NGATE1-9
20k NGATE7B
VL 5.49k
PTC
32.4k AUXP
VH 10µF +
AUX2
25V 5.49k
8.06k AUXN NGATE8B
ISET

+
GND 5.49k BAT3
NGATE9B

10µF
25V

D2
CM CP
3.3V VREG 249Ω 1.33k
NGATE5A
100k 100k 100k 100k 100k 100k 100k EN1 BOOST
1µF EN2 10µF D1 5.49k
6V MODE 25V
V4
TERM1
TO TERM2 NGATE4A
µP 10µF 5.49k
UVFLT 25V
OVFLT V3
DONE 2.74k
BAL NGATE3A
PTCFLT 10µF
25V
BATX V2
BATY
+
CTON LTC3305 NGATE2A BAT2
10µF
5.49k
25V

CTOFF V1
10µF +
25V NGATE6A NGATE1A BAT1
CTBAT 5.49k 5.49k
10nF 9 NGATE1A-9A
NGATE1-9
NGATE7A
VL 5.49k
20k PTC
AUXP
VH
10µF +
32.4k 25V AUX1 5.49k
NGATE8A
AUXN
ISET
8.06k GND 5.49k
NGATE9A

3305 F07

Figure 9. Three LTC3305 Devices Connected to Balance Eight Lead-Acid Batteries

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For more information www.linear.com/LTC3305 23

LTC3305
APPLICATIONS INFORMATION
10µF
25V ALL NMOS DEVICES = SiR882DP
D1, D2, D3, D4 = CMMSH1-100

D4
CM CP 1.33k NGATE5B
VREG 249Ω
1µF EN1 BOOST 6.04k
6V 10µF D3
EN2
MODE 25V
V4
TERM1 NGATE4B +
475Ω 475k BAT6
TERM2 10µF 6.04k
25V
UVFLT
OVFLT V3
DONE 3.01k
BAL NGATE3B
PTCFLT 10µF
BATX 25V
BATY V2
LTC3305 +
CTON NGATE2B BAT5
10µF
25V 6.04k
CTOFF
V1
6.04k
10µF NGATE6B
CTBAT 25V
10nF 9
NGATE1-9
VL NGATE1B-9B 6.04k
NGATE7B
27.4k

VH PTC +
42.2k AUXP BAT4
10µF +
ISET 25V AUX2 6.04k NGATE1B
12.1k AUXN NGATE8B 6.04k
GND

6.04k
NGATE9B

10µF
25V

D2
CM CP 1.33k NGATE5A
VREG 249Ω +
1µF EN1 6.04k BAT3
BOOST
6V EN2 10µF
D1
MODE 25V
V4
TERM1 NGATE4A
475k
TERM2 10µF 6.04k
25V
UVFLT
OVFLT V3
DONE 3.01k
BAL NGATE3A
PTCFLT 10µF
BATX 25V
BATY V2
LTC3305 +
CTON NGATE2A BAT2
10µF
25V 6.04k
CTOFF
V1
6.04k
10µF NGATE6A
CTBAT 25V
10nF 9
NGATE1-9 +
VL NGATE1A-9A 6.04k BAT1
NGATE7A
27.4k

VH PTC
42.2k AUXP
10µF +
ISET 25V AUX1 6.04k NGATE1A
12.1k AUXN NGATE8A 6.04k
GND

6.04k
NGATE9A

3305 F08

Figure 10. Two LTC3305 Devices Connected to Balance Six Lead-Acid Batteries with AND’d DONE Indicator
3305fb

24 For more information www.linear.com/LTC3305

 LTC3305
APPLICATIONS INFORMATION
ALL NMOS
DEVICES = SiR892DP
10µF D4 D1, D2, D3, D4 = CMMSH1-100
25V
CM CP 249Ω
VREG 1.33k
BOOST NGATE5B
1µF EN1
6V 10µF 6.04k
EN2 D3
100k 25V
MODE
V4 +
TERM1 6.04k
NGATE4B BAT8
TERM2 10µF
UVFLT 25V
OVFLT
DONE V3 +
3.01k BAT7
BAL NGATE3B
PTCFLT 10µF
BATX 25V
BATY
V2 +
LTC3305 NGATE2B BAT6
10µF
CTON 25V 6.04k

V1 +
CTOFF 6.04k BAT5
NGATE6B NGATE1B
10µF 6.04k
10nF 9 25V
CTBAT NGATE1-9 6.04k
NGATE1B-9B NGATE7B

VL PTC
AUXP
10µF +
VH AUX2
25V 6.04k
AUXN NGATE8B
12.1k I
SET
GND 6.04k
NGATE9B

10µF D2
25V
CM CP 249Ω
VREG 1.33k
BOOST NGATE5A
1µF EN1
6V 10µF 6.04k
EN2 D1
100k 25V
MODE
V4
TERM1 6.04k
NGATE4A +
TERM2 10µF BAT4
UVFLT 25V
OVFLT
DONE V3
3.01k
BAL NGATE3A +
PTCFLT 10µF BAT3
BATX 25V
BATY
V2
LTC3305 10µF NGATE2A +
CTON 25V BAT2
6.04k

V1
CTOFF 6.04k
NGATE6A NGATE1A +
10µF BAT1
6.04k
10nF 9 25V
CTBAT NGATE1-9 6.04k
NGATE1A-9A NGATE7A

VL PTC
AUXP +
AUX1
VH 10µF
25V 6.04k
AUXN NGATE8A
12.1k I
SET
GND 6.04k
3305 F11 NGATE9A

Figure 11. Eight Battery Balancer Using Two LTC3305 Devices

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For more information www.linear.com/LTC3305 25

LTC3305
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3305#packaging for the most recent package drawings.

FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA

4.75 REF 9.60 – 9.80*

(.378 – .386)
4.75 REF
(.187)
38 20

6.60 ±0.10
2.74 REF
4.50 REF
SEE NOTE 4 6.40
2.74
0.315 ±0.05 REF (.252)
(.108)
BSC
1.05 ±0.10

0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 19
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.50
0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.17 – 0.27
FE38 (AA) TSSOP REV C 0910
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN MILLIMETERS FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3305fb

26 For more information www.linear.com/LTC3305

 LTC3305
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/15 Added timer mode section. 13
Modified Figure 6 schematic. 16
Modified Figure 8 schematic. 22
Modified Figure 9 schematic. 23
B 03/16 Updated Feature bulleted items and description 1
Updated Application schematic 1
Enhanced Operation section 11

3305fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC3305
as described herein will not infringe on existing patent rights. 27
LTC3305
TYPICAL APPLICATION
A Minimum Component Application in Which an LED is Used to Display Status

10µF
25V
D1, D2 = CMMSH1-100

D1
CM CP 1.33k NGATE5
VREG 249Ω
1µF EN1 BOOST 6.04k
10µF
6V EN2 D2
25V
MODE V4
TERM1 NGATE4 +
100Ω BAT4
TERM2 10µF 6.04k
25V
UVFLT
OVFLT V3
DONE 3.01k
BAL NGATE3
+
PTCFLT 10µF BAT3
BATX 25V
BATY V2
LTC3305 NGATE2
10µF +
CTON 6.04k BAT2
25V

V1
CTOFF 10µF
6.04k
25V NGATE6 NGATE1 +
6.04k BAT1
9
CTBAT NGATE1-9
10nF
6.04k ALL NMOS
NGATE7
DEVICES = SiR882DP
VL

PTC
AUXP
VH 10µF +
25V AUX 6.04k
ISET AUXN NGATE8
12.1k GND

6.04k
NGATE9 3305 TA02

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3305fb

28 Linear Technology Corporation

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