8086 operating Modes:

There are two available modes of operation for the 8086 microprocessor:

 Minimum mode
 Maximum mode

Minimum mode operation is obtained by connecting the mode selection pin to +5.0 V, and
maximum mode is selected by grounding this pin.

Both modes enable different control structures for the 8086 microprocessor.

When the Minimum mode operation is selected, the 8086 provides all control signals needed to
implement the memory and I/O interface.

The maximum mode is unique and designed to be used whenever a coprocessor exists in a system.

Note that the maximum mode was dropped from the Intel family beginning with the 80286
microprocessor
Signals common to both the operating modes:

Minimum mode:

The minimum mode is selected by applying logic 1 to the MN / MX’ input pin.

This is a single microprocessor configuration.

When the Minimum mode operation is selected, the 8086 provides all control signals needed to
implement the memory and I/O interface.

Minimum mode operation is the least expensive way to operate the 8086 microprocessor. It costs
less because all the control signals for the memory and I/O are generated by the microprocessor.

• The minimum mode signal can be divided into the following basic groups: address/data bus, status,
control, interrupt and DMA.
The hold input requests a direct memory access (DMA). If the HOLD
signal is at logic 1, the microprocessor stops executing instruction and
places its address, data, and control bus at the high-impedance state.
Hold acknowledge indicates that the 8086 has entered the hold state
This pin selects memory or I/O. This pin indicates that the
microprocessor address bus contains either a memory address or an I/O
port address.

The write line is a strobe that indicates that the 8086 is outputting data to
a memory or I/O device. During the time that there is logic 0, the data
bus contains valid data for memory or I/O. This pin floats to a high
impedance during a hold acknowledge.
The interrupt acknowledge signal is a response to the INTR input pin.
The pin is normally used to gate the interrupt vector number onto the
data bus in response to an interrupt request.
Address latch enable shows that the 8086 address/data bus contains
address information. This address can be a memory address or an I/O
port number.
The data transmit/receive signal shows that the microprocessor data bus
is transmitting or receiving data. This signal is used to enable external
data bus buffers.
Data bus enable activates external data bus buffers.
Maximum mode:

Maximum mode operation differs from minimum mode in that some of the control signals must be
externally generated. This requires the addition of an external bus controller—the 8288 bus
controller. There are not enough pins on the 8086/8088 for bus control during maximum mode
because new pins and new features have replaced some of them. Maximum mode is used only when
the system contains external coprocessors such as the 8087 arithmetic coprocessor.

The maximum mode is selected by applying logic 0 to the MN / MX’ input pin.

This is a multi microprocessors configuration.

 The status bits indicate the function of the current bus cycle. These
signals are normally decoded by the 8288 bus controller.

The request/grant pins request direct memory accesses (DMA) during

Maximum mode operation. These lines are bidirectional and are used to
both request and grant a DMA operation.

The lock output is used to lock peripherals off the system. This pin is
activated by using the LOCK: prefix on any instruction.

The queue status bits show the status of the internal instruction queue.
These pins are provided for access by the numeric coprocessor (8087).

References:

https://userpages.umbc.edu/~squire/intel_book.pdf

https://nptel.ac.in/content/storage2/courses/106108100/pdf/Teacher_Slides/mod1/M1L3.pdf
Memory Segmentation

A segment is a logical unit of memory that may be up to 64K bytes long. Each segment is made up of
contiguous memory locations and is independent, separately addressable unit. Every segment is
assigned (by software) a base address, which is its starting location in the memory space. A segment
address (or logical address) has two components:

 Segment base address

 Offset

A logical address contains a segment base value (starting address) and offset defined as base value:
offset.

For any given memory location, the segment base value locates the first byte of the containing
segment and the offset value is the distance, in bytes, of the target location from the beginning of
the segment.

Segment base and offset values are unsigned 16-bit quantities; the lowest addressed byte in a
segment has an offset 0.

The size of offset limits the maximum size of a segment. In 8086 with 16-bit offset, a segment may
be no longer than 64KB.

1 MB memory of 8086 is partitioned into 16 segments-outs of these segments only 4 segments can
be active at a time (Code, data, stack and extra segments). The currently addressable segments
provide a generous work space: 64K bytes for code, a 64K byte stack and 128 K bytes of data
storage.

The 16-bit content of segment register actually points to the starting location of a particular
segment. The address may be assigned as 0000H (min) to F000H (max) respectively. The offset
address values are from 0000H to FFFFH.

All segments begin on the 16-byte memory boundaries. There are no other restrictions on the
segment locations; segments may be: adjacent, disjoint, partially overlapped, or fully overlapped.
Overlapping Segment: A segment starts a particular address and its maximum size can go upto 64
KB. But if another segment starts along with any of 64KB locations of this segment, then two
segments are said to be overlapping segments.

Non-overlapping segments: A segments starts after 64KB of a segment is called non-overlapping

segments.

Continuous segment: A segment starts just after the location where the previous segments ends.

Disjoint segment: A segment neither overlapping nor continuous will be a disjoint segment.

A physical memory location may be mapped into (contained in) one or more logical segments.

Why segmentation:

 The segmented structure of 8086 memory space supports modular software design.
 Segmentation provides a way to implement object oriented programs
 Segments allow two processes to share data easily

Physical Address generation:

Physical address is 20-bit value that uniquely identifies each byte location in the megabyte memory
space. Physical addresses range from 00000H (or 0H) through FFFFFH. The programs deal with
logical addresses and allow code to be developed without prior knowledge of where the code is to
be located in memory and facilitate dynamic management of memory resources.

Whenever the BIU accesses the memory, it generates a physical address from a logical address; this
is done by the shifting left the segment base value four bit positions and adding the offset

The BIU obtains the logical address of a memory location from the different sources depending on
the type of reference that is being made as shown in the following table:
Logical Address Sources:

Many different logical addresses can map to the same physical location (overlapping segments).
8086 memory interface
From the point of view, the 8086 memory spaces are organized as identical arrays of 8-bit
bytes. Instruction, byte data and word data may be freely stored at any byte address without
regard for alignment.

The 8086 can access any two consecutive bytes as a word of data. The lower-addressed byte
is the least significant byte of the word, and the higher- addressed byte is its most significant
byte.
The 8086 has 16-bit data bus. It must be able to write data to any 16-bit location or any 8-bit
location. The 16-bit data bus must be divided into two separate sections (or banks) that are 8
bits wide so that microprocessor can write to either half (8 bit) or both halves (16-bit).
Memory is arranged in two 8-bit banks.
Low bank: contains all even addresses
High bank: contains all odd addresses
The 8086 microprocessor uses the signal BHE’ (high bank) and the A0 address bit (low bank)
to select one or both banks of memory used for the data transfer

Function

0 0 Both banks enabled for a 16-bit transfer

0 1 High bank enabled for an 8-bit transfer
1 0 Low bank enabled for an 8-bit transfer
1 1 No bank enabled

Bank selection is accomplished in two ways:

(1) A separate write signal is developed to select a write to each bank of the memory, or
(2) Separate decoders are used for each bank.

Separate Bank Write Strobes: The most effective way to handle bank selection is to
develop a separate write strobe for each memory bank. This technique requires only one
decoder to select a 16-bit-wide memory, which often saves money and reduces the number of
components in a system.
The word of data is at an even-address boundary (i.e. address of least significant byte is even)
is called aligned word. It can be accessed in a single read cycle.
The word of data is at an odd-address boundary is called misaligned word. The word is stored
at an odd (unaligned) address, as shown in Figure below. It will require two read cycles.
(a) During first read, W2L (odd address) will appear on the high byte of the data bus.
(b) During the second read, W2H (even address) will appear on the low byte of data
bus.

[A1] Aligned and unaligned words

To store double word four locations are needed. The double word that it’s least significant
byte address is a multiple of 4 (e.g. 0 16, 416, 816 ...) is called aligned double word. The
double word at address of non-multiples of 4 is called misaligned double word.

References
[A1] https://www.sakshieducation.com/Story.aspx?nid=89886