Bidirectional Three-Level DC-DC Converters:

Sum-Difference Modeling and Control

Michael Eull and Matthias Preindl
Department of Electrical Engineering, Columbia University in the City of New York
matthias.preindl@columbia.edu

Abstract—This paper proposes a modeling and control ap- ic1

proach for the three-level DC-DC converter. The converter is iL L S1 +
described in a sum and difference (Σ∆) framework. It is shown C1 v1
that the formulation is useful to model the inverter and derive + S2 +
design-specific equations. The Σ component is responsible for the +
inductor current, i.e. the power flow, and the ∆ component is Ib Cb vb vs vd Id
used to balance (or unbalance) the DC-link capacitor voltages. S3
It is shown that there are cross-coupling terms between the Σ
+
C2 v2
and ∆ axes that can be compensated. The proposed model is
validated using high fidelity simulations with a proportional- S4 i
c2
integral controller. Two- and three-level converter operation is
shown and it is proven that the passive components can be
reduced by 50% to 75% using three-level operation without
Fig. 1: Three-level DC-DC converter.
affecting the control performance. The control is verified by
introducing load current and DC voltage steps.
anced operation. The results are confirmed by simulation. The
I. I NTRODUCTION converter is operated in both two- and three-level operation.
Bidirectional non-isolating DC-DC converters are a key The latter introduces vertical interleaving to reduce passive
technology for electrified transportation systems. They are components. It is proven that the passive components can be
particularly relevant for vehicles with more-electric drivetrains reduced by 50% to 75% using three-level operation. The same
[1]–[3]. DC-DC converters are used to interface energy storage ratio holds when comparing the 2L DC-DC (conventional
systems in electric vehicles (EV) and plug-in hybrid electric buck-boost converter) to the 3L DC-DC converter.
vehicles (HEV) and energy transformation units in fuel-cell The Σ∆ framework is further used for control. It can
vehicles [4]–[6]. The energy necessary for xEV traction can be be used in a fashion similar to the dq framework that is
provided by one or more electrical energy sources or storage widely employed in motor drives [17]. The Σ component is
mediums. Non-isolating DC-DC converters are necessary to responsible for current control, i.e. the power flow, whereas the
interface different voltage levels and to control the power ∆ system is used to control the voltage sharing of the DC-
flow [7], [8]. An example are EVs with hybrid energy storage link capacitors. It is shown that there are cross-coupling terms
systems [9], [10], where a battery pack stores the energy for between the Σ and ∆ axes and that they can be compensated.
a suitable driving range and an ultracapacitor pack provides Compensation is optional and can be taken care of by a
peak power and handles micro-cycling [8]. sufficiently fast feedback controller. The control is verified by
Numerous converters have been proposed and compared introducing load current and DC voltage steps in high fidelity
in literature [7], [11]–[13]. DC-DC converters for xEV are simulations.
typically benchmarked with respect to efficiency. xEVs require
II. A NALYSIS
a high efficiency over a wide range of operating points that
are defined by city and highway driving cycles. A promising The bidirectional three-level boost converter has four useful
solution is the three-level DC-DC converter [14], [15] that is switching states. One of the upper two switches (S1 and S2 )
capable of operating at high efficiency over wide load and high needs to be off to avoid short-circuiting the voltage v1 (t).
voltage transformation ranges. In particular, this converter has
been shown to be highly competitive when compared to the
TABLE I: Switching states, capacitor currents and output
two-level and two-level inverterleaved converters [16].
voltages for the three-level converter.
This paper proposes a novel modeling and control ap-
proach for the three-level DC-DC converter. The converter S1 S2 S3 S4 s(t) [ic1 ,ic2 ]0 vs (t)
is described in a sum and difference (Σ∆) framework. It is off on on off [0,0]0 [0,0]0 0
shown that the formulation is useful to model the inverter and on off on off [1,0]0 [−iL ,0]0 v1
derive design specific equations. Design equations are given off on off on [0,1]0 [0, − iL ]0 v2
on off off on [1,1]0 [−iL , − iL ]0 v1 + v2
for balanced operation and can be easily extended to unbal-

978-1-5090-3953-1/$31.00 ©2017 IEEE 573

Likewise, one of the lower two switches (S3 and S4 ) needs
to be off to avoid short-circuiting the voltage v2 (t). Turning
both S1 and S2 (or S3 and S4 ) off yields a voltage, vs (t), that
depends on the sign of the current and is ignored in this text.
The resulting useful switching states are shown in Table I and
Fig. 2.
To simplify the modeling, we introduce the binary switching
state s(t) = [s1 (t),s2 (t)] ∈ {0,1}2 and capacitor voltage
v12 (t) = [v1 (t),v2 (t)]0 ∈ R2+ , where vd (t) = 10 v12 (t) = (a) s = [0,0]0 (b) s = [1,0]0 (c) s = [0,1]0 (d) s = [1,1]0
v1 (t) + v2 (t) ∈ R+ . Hence, the voltage that is applied to
the inductor is vs (t) = v12 (t)0 s(t) ∈ R+ . In practice, DC-DC Fig. 2: Conduction paths as a function of the switching state
converters are typically designed for Pulse Width Modulation s(t).
(PWM). PWM translates a duty cycle d = [d1 ,d2 ]0 ∈ [0,1]2
into a switching sequence with time average
Adding the dynamic equation of the capacitor Cb , we obtain
Z kTsw +Tsw
1 the full dynamics of the system in scalar notation:
d= s(t) dt, (1)
Tsw kTsw
Ts Ts
i+
L = iL + (vd dΣ + v∆ d∆ ) − vb , (8a)
where Tsw is the switching period. Similarly, the model can 2L L
be rewritten using average modeling (neglecting second order + Ts
v∆ = v∆ − iL d∆ , (8b)
components) C
+ Ts 2Ts
0
vs = v12 d = v1 d1 + v2 d2 . (2) vd = vd − iL dΣ + Id , (8c)
C C
Ts Ts
Furthermore, we introduce the sum and difference notation vb+ = vb + iL − Ib ; (8d)
Cb Cb
dΣ∆ = [dΣ ,d∆ ]0 = Td and vΣ∆ = [vΣ ,v∆ ]0 = Tv12 , where
  or, in matrix form,
1 1
T= (3)
1 −1 x+ = Ax + B(x)u + e, (9)
and vΣ = vd . The updated notation yields
where x = [iL ,v∆ ,vd ,vb ]0 is the state vector, u = dΣ∆ is the

0
vs = T−1 vΣ∆ T−1 dΣ∆ input and e is the exogenous input. Their parameters are


(4a)
1 0 1  −T
  Ts Ts
  
0
= vΣ∆ dΣ∆ = (vd dΣ + v∆ d∆ ) , (4b) 2L vd 2L v∆
1 00 s
L 0
2 2 A= 0 10 0  , B(x) =  0 −Ts
C iL ,e =  2Ts .
0 01 0 −Ts C Id
C iL 0
Ts −Ts
and the (discrete-time) dynamic equation of the inductor C b
00 1 C b Ib
0 0
current
The system (9) has a constant state parameter matrix and is
Ts Ts
i+
L = iL + vs − vb (5a) affine in the input with a state-dependent parameter matrix.
L L
Ts Ts The state-space system (8) defines the following control
= iL + (vd dΣ + v∆ d∆ ) − vb , (5b) problems that need to be addressed to operate the three-level
2L L
DC-DC converter
where the sampling period Ts = Tsw for simplicity and .+
• Power flow: the converter transfers the power p = vb iL .
denotes entities of the (discrete) sampling time instant t + Ts .
Controlling the power translates into controlling iL since
The voltages on capacitors C1 and C2 vary as a function of
vb is approximately constant (by design or control).
the inductor current and duty cycle, per
• Symmetric operation: Converters are typically imple-
+ Ts Ts mented with one type of semiconductor and capacitor.
v12 = v12 − iL d + Id , (6)
C C To minimize component stresses, the capacitor voltages
where we assume C1 = C2 = C for simplicity and Id is the should be symmetrical, which can be achieved by con-
constant DC current. This equation states that d1 > 0 and trolling v∆ to zero.
d2 > 0 discharges the capacitors C1 and C2 with current iL , • Voltage stabilization: Either vb or v12 can be controlled
respectively. The duty cycles d1 = 0 and d2 = 0 bypass iL and via the power flow through the converter. The other
do not affect the capacitor voltage. The equation is rewritten voltage needs to be stabilized via the exogenous input
using the sum and difference notation as (Ib or Ic ) since the converter cannot store significant
amounts of energy. Stabilization can be achieved through
 0
+ Ts 2Ts connection to a DC bus or energy storage system (battery
vΣ∆ = vΣ∆ − iL dΣ∆ + Id ,0 . (7) or ultracapacitor).
C C

574
 1 1 1 1
pwm

pwm

pwm

pwm
0.5 0.5 0.5 0.5
0 0 0 0
0 10 20 0 10 20 0 10 20 0 10 20
400 400 400 400
vs [V]

v [V]

vs [V]

vs [V]
200 200 200 200

s
0 0 0 0
0 10 20 0 10 20 0 10 20 0 10 20
60 60 60 60
iL [A]

iL [A]

iL [A]

iL [A]
50 50 50 50
40 40 40 40
0 10 20 0 10 20 0 10 20 0 10 20
50 50 50 50
ic [A]

ic [A]

ic [A]

ic [A]
0 0 0 0
0 10 20 0 10 20 0 10 20 0 10 20
202 202 202 202
vc [V]

v [V]

vc [V]

vc [V]
200 200 200 200
198 198 198 198
c

0 10 20 0 10 20 0 10 20 0 10 20
405 405 405 405
vd [V]

v [V]

vd [V]

vd [V]
400 400 400 400
d

395 395 395 395

0 10 20 0 10 20 0 10 20 0 10 20
120.5 120.5 280.5 280.5
vb [V]

vb [V]

vb [V]

vb [V]
120 120 280 280
119.5 119.5 279.5 279.5
0 10 20 0 10 20 0 10 20 0 10 20
t [us ] t [us ] t [us ] t [us ]
(a) No interleaving, d1 = 0.3. (b) Interleaving, d1 = 0.3. (c) No interleaving, d1 = 0.7. (d) Interleaving, d1 = 0.7.

Fig. 3: High fidelity simulations, with and without interleaving, for C1 = C2 = Cb = 30µF, L = 47µH and fsw = 100kHz.

0.3
compared to 2L switching. An example is shown in Fig.3.
iL, vd [pu]

0.2
The switching ripples are analyzed in steady state condi-
tions. Substituting i+ +
L = iL and v∆ = v∆ in (28) yields vs =
_^ _^

0.1 vb and i∆ = 0, i.e. d∆ = 0, and d1 = d2 = dΣ /2 = vb /vd .

We also assume symmetric operation, where v∆ = 0 and
0
0 0.2 0.4 0.6 0.8 1 v1 = v2 = vd /2. This operation yields symmetric voltage
0.04
and current stresses on the upper and lower bridge and it can
be shown that it yields minimum ripples. In these conditions,
0.03
it can be shown that the (constant) input/output currents are
vb [pu]

0.02 Ic = d1 iL and Ib = iL .
_^

0.01 Both 2L and 3L switching yield a characteristic switching

0 pattern in the steady state that can be observed in Fig. 3. Two-
0 0.2 0.4 0.6
d =d [pu]
0.8 1
level switching only applies the switching states s(t) = [0,0]0
1 2
and s(t) = [1,1]0 such that vs (t) switches between two voltage
Fig. 4: Normalized current and voltage ripples. Continuous levels: 0V and vd . In contrast, 3L switching applies all four
line: analytic functions (12), (13), (15), (16), (18) and (19); switching states and vs (t) ∈ {0V ,vd /2,vd }. Dependent on the
markers: current (◦) and voltage (×) ripples obtained from duty cycle, vs switches between 0V and vd /2 or vd /2 and vd .
high fidelity simulation with C1 = C2 = Cb = 30µF, L = In addition, 3L switching effectively doubles the switching
47µH and fsw = 100kHz. frequency for the passive components.
To quantify the effects of switching, we formally define
the switching ripple as the peak-to-peak amplitude over Tsw
III. M ODULATION in steady state conditions. The switching ripple of inductor
The upper bridge (switches S1 and S2 ) is actuated by current is defined as
the duty cycle d1 and the lower bridge (S3 and S4 ) by d2
îL = max iL (t) − min iL (t) ∀t ∈ [kTsw ,(k + 1)Tsw ], (10)
using dedicated PWM modules. Both bridges can be operated
independently from one another and two modulation strategies and the switching ripple of vs and vb are defined analogously.
are analyzed: two-level (2L) and three-level (3L) switching. Switching ripples are calculated using the discrete version
The PWM carrier signals of the upper and lower bridge are in of the characteristic inductor and capacitor equations. The
phase for 2L switching and phase shifted by 180◦ (Tsw /2) inductor current ripple results from
in 3L switching. Three-level switching can be interpreted
as a vertical interleaving of the two bridges. Interleaving îL
L = |v̂L |, (11)
is generally considered to reduce current (voltage) ripples T̂

575
where the voltage v̂L is assumed to be approximately constant The normalized switching ripple is provided by (12), (13),
and applied for the period T̂ . For 2L switching, the normalized (15), (16), (18) and (19) and shown in Fig. 4 as con-
current ripple is tinuous lines. The analytic equations are validated using a
L high fidelity MATLAB/Simulink model with Simscape/SPICE
îL,2L (d1 ) = îL = d1 (1 − d1 ) (12) components applying (10) to the steady state waveforms for
Tsw vd
d = 0.1,0.2, . . . ,0.9. The results are shown in Fig. 4 as markers
when considering the off period where |v̂L | = vb = d1 vd is with current being circles (◦) and voltages crosses (×).
applied for T̂ = (1 − d1 )Tsw . With interleaving, the current
ripple depends on the value of d1 as follows: IV. D ESIGN
(
|0.5 − d1 |d1 , if 0 ≤ d1 ≤ 0.5; The switching ripples of the presented boost converter
îL,3L (d1 ) = (13)
|0.5 − d1 |(1 − d1 ), if 0.5 < d1 ≤ 1. depend on the modulation technique. Three-level switching
For d1 ≤ 0.5 the voltage |v̂L | = d1 vd is applied during the off significantly reduces the current and voltage switching ripples
interval |0.5 − d1 |Tsw ; for d1 ≥ 0.5, the voltage |v̂L | = vd − compared to 2L switching. Hence, 3L switching can be used
vb = (1−d1 )vd is applied during the on interval |0.5−d1 |Tsw . to reduce the passive components. This section presents design
The vd voltage ripple is computed similar to îL . The equations for 2L and 3L switching.
treatment is based on the equation The maximum normalized ripple is obtained by deriving
the analytic expression and setting it to zero. Using the 2L
C v̂d
= |îd |, (14) inductor current ripple as an example, we have
2 T̂
d ˆ 
where v̂d is the voltage ripple, îd is the capacitor current that is īL,2L (d1 ) = 1 − 2d1 = 0 ⇔ d1,2Lmax = 0.5. (20)
assumed to be approximately constant over the period T̂ that d d1
it is applied, and C/2 is the resulting capacitance of the series In the same fashion, d1,3Lmax = 0.25 for 3L switching. The
connected C1 and C2 . Without interleaving, the normalized same duty cycles are obtained for the maximum voltage
voltage ripple is ripples. The maximum 2L normalized ripples are obtained by
C substituting the duty cycles in (12), (15) and (18):
v̄ˆd,2L (d1 ) = v̂d = d1 (1 − d1 ) (15)
2Tsw ILR ˆī ˆd,2Lmax = 250 · 10−3 ,
L,2Lmax = v̄ (21a)
when considering the off period where |îd | = |Ib | = d1 ILR is
v̄ˆb,2Lmax = 31.2 · 10−3 . (21b)
applied for T̂ = (1−d1 )Tsw . The ripple is computed using the
rated (average) inductor current ILR , which yields the worst- The maximum 3L normalized ripples are obtained by sub-
case ripple. With interleaving, the voltage ripple is stituting the duty cycles in (13), (16) and (19):
(
|0.5 − d1 |d1 , if 0 ≤ d1 ≤ 0.5; ˆī
v̄ˆd,3L (d1 ) = (16) ˆd,3Lmax = 62.5 × 10−3 ,
L,3Lmax = v̄ (22a)
|0.5 − d1 |(1 − d1 ), if 0.5 < d1 ≤ 1.
v̄ˆb,3Lmax = 3.9 × 10−3 . (22b)
For d1 ≤ 0.5 the current |îc | = |Ib | = d1 ILR is applied during
the off interval |0.5 − d1 |Tsw ; for d1 ≤ 0.5, the current |îc | = Once the maximum normalized ripples are known, the design
ILR − |Ib | = (1 − d1 )ILR is applied during the on interval equations result directly from (12), (15) and (18). Transform-
|0.5 − d1 |Ts . ing these equations, we obtain
The computation of thevoltage ripple of vb is based on the vd
assumption that the inductor current ripple circulates in the L = ˆīL,max (23a)
fsw îLmax
capacitor. The charge, which varies with vd , is obtained by 2ILR
integrating the triangular inductor current ripple in the positive C1 = C2 = C = v̄ˆd,max (23b)
fsw v̂dmax
half-period and is calculated as vd
Cb = v̄ˆb,max 2 (23c)
1 îL fsw Lv̂bmax
Q̂b = Cb v̂b = T̂ , (17)
2 2 where fsw = 1/Tsw is the switching frequency. The normal-
where T̂ is the duration of the half-period. Without interleav- ized ripples ˆīL,max , v̄ˆd,max and v̄ˆb,max are either the normalized
ing, we obtain the normalized voltage ripple 2L switching ripples specified in (21) or the normalized 3L
LCb 1 1 switching ripples specified in (22). The maximum peak-to-
v̄ˆb,2L (d1 ) = 2 v̂b = îL,2L (d1 ) = d1 (1 − d1 ), (18)
Tsw vd 8 8 peak current ripple, îL,max is often chosen as 40% of ILR . The
maximum peak-to-peak voltage ripples v̂d,max and v̂b,max are
where T̂ = Tsw /2. With interleaving, T̂ = Tsw /4 and we typically specified design requirements.
obtain The required inductance and capacitance values can be put
îL,3L (d1 ) into relation for a 2L and 3L design that use the same voltages
v̄ˆb,3L (d1 ) = . (19)
16 (vd and vb ), current (ILR ), inductor current ripple (îL,max )

576
and switching frequency (fsw ). The inductance L ratio and
1 1
capacitance C ratio is

pwm

pwm
0.5 0.5
0 0
L3L ˆī C3L v̄ˆd,3Lmax 1 0 10 20 0 10 20
L,3Lmax 800 800
= = = = (24)

vs [V]

vs [V]
L2L ˆīL,2Lmax C2L ˆ
v̄d2L,max 4 400 400
0 0
0 10 20 0 10 20
and the capacitance Cb ratio is 70 70

iL [A]

iL [A]
60 60
50 50
Cb,3L v̄ˆb,3Lmax ˆīL,2Lmax 1 0 10 20 0 10 20
= = . (25)
Cb,2L v̄ˆb2L,max ˆīL3L,max 2

ic [A]

ic [A]
50 50
0 0
Hence, 2L switching requires 4 times the inductance L and 0 10 20 0 10 20
404 404

vc [V]

vc [V]
capacitance C compared to 3L switching. Although the in- 400 400
ductance current ripple is the same, 3L switching requires half 396 396
0 10 20 0 10 20
the capacitance Cb since the frequency of the current ripple is 802 802

vd [V]

vd [V]
2fsw compared to just fsw for 2L switching. 800 800
798 798
The impact of the filter parameter on volume can be 0 10 20 0 10 20
401 201

vb [V]

vb [V]
estimated using scaling laws [18]. The inductor volume scales 400 200
approximately according to 399 199
0 10 20 0 10 20
 34  34  34 t [us ] t [us ]
0.5LI 2
  
YL EL L (a) 2L. (b) 3L.
= = = , (26)
YL∗ EL∗ 0.5L∗ I 2 L∗
Fig. 5: Reference design (Table II) validation for worst-case
where YL and EL are the inductor volume and energy, duty cycles: d = 0.5 for 2L and d = 0.25 for 3L.
respectively. The variables with superscript .∗ belong to a
reference device using the same technology. The capacitor FB and FF Control Duty Cycle Calculation
+ vs + + dΣ d1
volume scales approximately according to rL
- PI - * ΣΔ
iL vb + vd/2 ÷

YC EC 0.5CV 2 C vΔ/2 .5

*
*
rΔ +
∗ = ∗ = = ∗ (27) - PI -1 *
YC EC 0.5C ∗ V 2 C vΔ iΔ iL ÷
dΔ 12 d2

where YC and EC are the capacitor volume and energy, Fig. 6: Control block diagram with feedback (FB) and feed-
respectively. Since the inductor (capacitor) works with the forward (FF) control and duty cycle calculation. The compen-
same current (voltage), the volume ratio can be computed sation of v∆ d∆ /2 (grey blocks) can be typically omitted.
based on the parameter values. Therefore, the inductor L
volume can be reduced by a factor of about 2.8 using 3L
switching compared to 2L switching. Similarly, the volume of be analyzed using common SISO tools, such as Bode plots.
C and Cb can be reduced by a factor of 4 and 2, respectively.
A 2L switching-based converter is compared to a (vertically
interleaved) 3L switching-based converter with a reference TABLE II: Two- and three-level converter design.
design for each case. The design specifications and results Design Specification
are shown in Table II.
Voltage range vd 400V . . . 800V
Voltage range vb 200V . . . 400V
V. C ONTROL Rated current ILR 60A
Ripple amplitude v̂dmax 1%vdmin = 4V
A simple control approach is obtained by assuming that the Ripple amplitude v̂bmax 1%vbmin = 2V
DC voltages, vd and vb , are effectively constant with respect to Ripple amplitude îLmax 40%ILR = 24A
Switching frequency fsw 100kHz
sampling instants (controlled externally or due to a connected
energy storage system). This assumption can be relaxed such Passive Design 2L 3L
that only one voltage is constant using a(n) (outer) voltage Inductance L 83.3µH 20.8µH
Capacitance C 75.0µF 18.8µF
control loop. Ignoring (8c) and (8d), the state-space model is Capacitance Cb 15.0µF 7.5µF
Inductance ratio L3L /L2L 25.0%
Ts Ts
i+
L = iL + vs − vb , (28a) Capacitor ratio C3L /C2L 25.0%
L L Capacitor ratio Cb3L /Cb2L 50.0%
+ Ts Estimated Volume Reduction
v∆ = v ∆ + i ∆ , (28b)
C Inductor volume ratio YL3L /YL2L 35.4%
where vs is used to steer iL and i∆ = −iL d∆ steers v∆ . The Capacitor volume ratio YC3L /YC2L 25.0%
Capacitor volume ratio YCb3L /YCb2L 50.0%
dynamic equations are independent from one another and can

577
 It is noted that the term iL can be positive, negative or
50 rL 50 rL
zero. If iL = 0, v∆ is constant and not controllable. Hence,
r [.]

r [.]
0 0
rΔ rΔ
-50 -50 the computation of d∆ in (30)–or, (31)–has to be protected
0 5 10 0 5 10
50 50 against division by zero. The control is shown in Fig. 7 using
vS , iΔ

vS , iΔ
0 0 synchronous sampling.
-50 -50
0 5 10 0 5 10 VI. C ONCLUSIONS
1 1
This paper presented a Σ∆ formulation of the three-level
d [-]

d [-]
0 0
_

_
0 5 10 0 5 10
DC-DC converter. Three-level operation is shown to reduce
1 d [-] 1 switching ripples by 50% to 75%. Alternatively, the passive
d [-]

0.5 0.5 components can be reduced by the same amount to achieve a

0 0
0 5 10 0 5 10 required switching ripple under the same operating conditions.
50 50 The control can also be implemented in this framework and
iL [A]

iL [A]

0 0
-50 -50 has been demonstrated with a proportional-integral controller.
0 5 10 0 5 10
220 220 R EFERENCES
vc [V]

vc [V]

200 200
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