A Novel High Gain DC-DC Multilevel Boost

Converter Using Voltage-Lift Switched-Inductor Cell

Mahajan Sagar Bhaskar, Nandyala SreeramulaReddy, Repalle Kusala Pavan Kumar, Inukonda Rajesh
Power Electronics and Drives Department
School of Electrical Engineering
VIT University, Tamil Nadu
sagar25.mahajan@gmail.com, ammasreeram@gmail.com, repallekusalapavan@gmail.com, mail2rajesh245@gmail.com

Abstract— This paper presents a novel high gain DC-DC devices. DC-DC multilevel converter combines the function of
multilevel boost converter using voltage-lift switched-inductor conventional boost converter and voltage multiplier cell.
(VLSI) cell. Cascading of conventional boost converters is not a Three-level voltage multiplier cell is shown in Fig1. In [12]-
viable solution to achieve high voltage gain. Thus, DC-DC [13], Switched inductor (SI) cell is used with voltage multiplier
multilevel converters are employed to achieve high conversion
cell to achieve high voltage gain. Switched inductor (SI)
ratio. The proposed high gain DC-DC multilevel boost converter
topology is non-isolated which combines the function of voltage- multilevel boost converter gives higher voltage gain than DC-
lift switched-inductors (VLSI) cell and voltage multiplier cell. In DC multilevel boost converter. In switched inductor cell, both
this paper voltage-lift switched-inductor (VLSI) cell is used to inductors are charges in parallel when switch is ON and
improve the boost capability of multilevel DC-DC converter. 2N discharges in series when switch is OFF. Fig2 shows switched
capacitors, 2N+3 diodes, two inductors and single switch are inductor cell switching states.
needed to design proposed N-level DC-DC topology. Proposed
DC-DC multilevel converter topology can be synthesized by using
low voltage rating devices because blocking voltage across each
power devices is less. The main advantage of this multilevel
topology is high conversion ratio is achieved without using
coupled inductor, transformer and extreme duty cycle. The
conversion ratio of this multilevel DC-DC converter is depends
upon the duty cycle and number of levels present in the voltage
multiplier cell. The proposed DC-DC multilevel converter has Fig1. Three-level voltage multiplier cell
been designed for three levels with rated power 200W, input
supply voltage is 12V, output voltage is 288V and switching
In this paper a novel high gain DC-DC multilevel boost
frequency is 50kHz. The proposed DC-DC multilevel converter
topology is simulated in MATLAB/SIMULINK. The simulation converter using voltage-lift switched-inductor (VLSI) cell is
results will verify the validity of the analytical design. proposed. In multilevel DC-DC boost converter voltage-lift
switched-inductor cell is employed to improve the boost
Keywords— Boost; High gain; Multilevel; Voltage multiplier; capability. Voltage-lift switched-inductor cell states are shown
Voltage-lift switched inductor cell (VLSI cell). in Fig3. In voltage-lift switched-inductor (VLSI) cell, both
inductors along with capacitor are charges in parallel when
I. INTRODUCTION switch is ON and discharges in series when switch is OFF.
Now day’s transformer-less DC-DC converters have drawn
tremendous interest in the renewable energy systems and
battery backup systems for power supplies [1]-[2]. However,
their voltage boost capability is limited due to the number of
power switches. Series connection of the conventional boost
converters is not a viable solution to achieve large conversion
ratio. In [3]-[4], cascaded DC-DC boost converter is used to
(a)Switched inductor cell
obtain high voltage gain. Higher switching losses in cascaded
converter prove to be an obstacle to achieve high voltage gain.
In [5]-[6], isolated converter topologies were used to achieve
high voltage gain. Isolated converter topology would only
increases the size, losses and cost of the converter because of
transformer and coupled inductors. Non-isolated topologies are
employed to overcome the drawbacks of isolated converters (b) When switch is ON (c) when switch is OFF
[7]-[8]. In [9]-[11], DC-DC multilevel boost converters were
used to achieve high voltage by using low voltage power Fig2. (a)-(c) Switched Inductor (SI) cell switching states
 switch S is turned ON and another when switch S is turned
OFF.

When Switch S is ON, inductors L1 and L2 are charged in

(a)Voltage-lift Switched Inductor (VLSI) Cell
parallel by supply voltage Vdc through diodes D8 and D6
respectively. At the same time capacitor C is also charged by
supply voltage Vdc through diode D7 and D8. When diode D2 is
forward biased, capacitor C2 is charged by voltage across
capacitor C1. Finally when diode D4 is forward biased,
capacitors C2 and C4 are charged by voltage across capacitors
C1 and C3. The mode-1 operation when switch S is ON is
shown in Fig5(a)-(c).

When Switch S is turned OFF, capacitor C, inductors L1

and L2 are discharges in series with supply voltage Vdc through
diode D9. Capacitor C1 is charged by the series combination of
inductors L1, L2 and capacitor C with supply voltage Vdc
(b) When switch is ON (c) When switch is OFF
through D9 and D1. When D3 is forward biased, capacitors C1
and C3 are charged by inductors L1, L2 and capacitors C, C2
Fig3. (a)-(c) Voltage-Lift Switched Inductor (VLSI) cell states with supply voltage Vdc through D9 and D3. Finally, capacitors
C1, C3 and C5 are charged by inductors L1, L2 and capacitors C,
II. CIRCUIT DESCRIPTION OF PROPOSED CONVERTER C2, C4 with supply voltage Vdc through D9 and D5. The mode-2
operation when switch S is OFF is shown in Fig6(a)-(c). Thus
A. Power Circuit diodes D1, D3, D5 and D9 are operated complementary with
The power circuit diagram of proposed N-level DC-DC diodes D2, D4, D6, D7 and D8.
Boost Converter which uses voltage-lift switched inductor III. ANALYSIS OF PROPOSED CONVERTER
(VLSI) Cell is depicted in Fig4. 2N capacitors, 2N+3 diodes,
two inductors and single switch are needed to design proposed Consider a 3-level proposed DC-DC converter in which
N-level DC-DC topology. The main advantage of this DC-DC both inductors L1 and L2 have same value. Assume D is duty
multilevel topology is high conversion ratio is achieved ratio of applied gate pulse and Vdc is supply voltage connected
without using coupled inductor, transformer and extreme duty at the input terminal of proposed converter.
cycle. The conversion ratio of this multilevel DC-DC boost
converter is depends upon the duty cycle and number of levels When switch S is turned ON, both inductors along with
present in the voltage multiplier cell. capacitor are charged in parallel, which is present in voltage-
lift switched-inductor (VLSI) cell.
VL1 = Vdc (1)
VL2 = Vdc (2)
VL1 = VL2 = VL (3)
VC = Vdc (4)
VC2 = VC1 (5)
VC2 + VC4 = VC1 + VC3 (6)
Vout = VC1 + VC3 + VC5 (7)
When switch S turned OFF, both inductors along with
capacitor are discharged in series.
Vdc − VL1 + VC − VL2 − VC1 = 0 (8)

Fig4. Proposed N-level DC-DC Multilevel Boost Converter VC3 = VC2 (9)
VC3 + VC5 = VC2 + VC4 (10)
B. Modes of operation
Put equation (3) in (8)
To explain the operation modes, 3-level proposed
converter circuit is considered. The operation modes of
VL =
( Vdc + VC − VC1 ) (11)
proposed converter are divided into two modes, one when 2
 (a) Charging of inductors (b) charging of C2 (c) Charging of C2 and C4

Fig5.(a)-(c) mode-1 operation when switch S is ON.

(a) Discharging of inductors (b) Charging of C1 and C3 (c) Charging of C1, C3 and C5

Fig6.(a)-(c) mode-2 operation when switch S is OFF.

By inductor volt second balance VC3 2

= (17)
⎛ ( V + VC − VC1 ) ⎞ Vdc (1 − D )
Vdc D + ⎜ dc ⎟ (1 − D ) = 0 (12)
⎝ 2 ⎠ Similarly from (6), (10), (15), (16) and (17)
V (1 + D ) VC4 VC5 2
VC1 = dc + VC = = (18)
(1 − D )
(13) Vdc Vdc (1 − D )
2Vdc
VC1 (1 + D ) VC VC1 = VC2 = VC3 = VC4 = VC5 = (19)
= +
Vdc (1 − D ) Vdc
(14) (1 − D )
Put equation (4) in (14)
Vout VC1 VC3 VC5 2 2 2
= + + = + + (20)
VC1 (1 + D ) 2 Vdc Vdc Vdc Vdc (1− D) (1− D) (1− D)
= +1 = (15) Thus, conversion ratio for proposed DC-DC 3-level
Vdc (1 − D ) (1 − D ) converter is
Put equation (5) in (15) 2×3
VC2 2 G3 = (21)
= (16) (1 − D )
Vdc (1 − D ) Thus, the gain of the proposed converter topology is twice
Put equation (9) in (16) than the gain of the conventional multilevel boost converter.
 Voltage gain of N-level proposed converter is
2N
GN = (22)
(1 − D )
IV. DESIGN DETAILS
The proposed multilevel DC-DC converter is based on the
voltage-lift switched inductor (VLSI) cell. The proposed
converter has been designed for 3-levels with rated power
200W, output voltage is 288V, supply voltage is 12V, and
switching frequency is 50kHz. To generate output voltage
288V from 12V input voltage, 75% duty ratio of gate pulse is
needed. The load is calculated from below expression Fig8. Gain comparison of proposed converter with existing multilevel
DC-DC converter
( Vout )
2
2882
R= = = 414.72Ω
P 200
Based on the required duty cycle, load resistance and
switching frequency, the critical value of the inductance LC is
calculated by using the expression,
D (1-D ) R
LC1 = LC2 = (23)
2f
Where, f is switching frequency
R is load.
0.75 (1-0.75 ) ×414.72
LC1 = LC2 = = 777.6 μH
2×50000
Fig9. Output Voltage and current waveform
V. SIMULATION RESULTS
The proposed multilevel DC-DC converter is simulated in
MATLAB/SIMULINK for 3-level with designed parameters.
The critical value of both inductors L1 and L2 is 777.6µH. For
convenience, inductors 1.0mH and 220μF capacitors are
selected. Fig7 shows the graph of gain versus duty ratio for
various output levels of proposed converter. In Fig8, the gain
of proposed converter is compared with existing multilevel
DC-DC converters. The output voltage and output current
waveform for a rated power 200W is shown in Fig9. Output
power waveform is shown in Fig10. Fig11 shows the inductors
L1 and L2 current waveforms with applied gate pulse. The
ripple in the inductor currents and output current is 0.2A and Fig10. Output power waveform
2mA respectively. Voltage stress waveform across switch S is
shown in Fig12. Fig13 shows the voltage at capacitors node
with respect to ground. The voltage stress across switch is 98V
which is acceptable for 12V input supply and 288V output.

Fig7. Voltage gain Vs duty cycle for various levels of proposed converter Fig11. Inductors L1 and L2 current waveforms with applied gate pulse

Fig12. Voltage stress waveform across switch S
Fig13. Voltage at capacitors with respect to ground
VI. CONCLUSION
The proposed high gain DC-DC multilevel boost converter
has been designed by using voltage-lift switched inductor
(VLSI) cell. The proposed converter topology is suitable for
unidirectional power transfer applications, where supply
voltage needs to be stepped up with high conversion ratio. This
converter provides a voltage gain higher than conventional
multilevel DC-DC converter. The proposed high gain DC-DC
multilevel boost converter topology combines the function of
voltage-lift switched-inductors (VLSI) cell and voltage
multiplier cell. This DC-DC multilevel converter topology can
be synthesized by using low voltage rating devices because
blocking voltage across each power devices is less. The main
advantage of this topology is the gain of converter can be
increases by adding capacitors and diodes at the output side
without disturbing the voltage-lift switched inductor (VLSI)
cell. The voltage gain of this converter is depends on the duty
cycle as well as number of levels. The MATLAB/SIMULINK
simulation results will verify the validity of the analytical
design of proposed converter.
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