1.
The n-MOS inverter is better than BJT in terms of
Answer: (d) All the mentioned
2. Silicon oxide is patterned on a substrate using
Answer: (b) Photolithography
3. CMOS inverter has ______ regions of operation.
Answer: (b) four
4. In CMOS fabrication, the photoresist layer is exposed to
Answer: (b) ultraviolet light
5. nMOS device, gate material could be
Answer: (b) polysilicon
6. P-well is created on
Answer: (b) n substrate
7. Latch-up can be induced by
Answer: (a) incident radiation
8. What can be introduced to reduce the latch-up effect
Answer: (b) guard rings
9. What are the features of BiCMOS?
Answer: (b) high packing density
10. Oxidation process is carried out using
Answer: (b) low purity oxygen
11. The ______ is used to reduce the resistivity of poly silicon.
Answer: Phosphorus doping
12. Transconductance can be increased by
Answer: Increasing gate width or decreasing channel length
13. MOSFET is used as
Answer: A switch or amplifier
14. In linear region ______ channel exists.
Answer: Conductive channel exists
15. The most popular types of ICs are
Answer: CMOS ICs
U-2
16. Stick diagrams are those which convey layer information through
Answer: (b) color
17. Which color is used for n-diffusion?
Answer: (a) red
18. The width of n-diffusion and p-diffusion layer should be
Answer: (b) 2λ
19. Which color is used for polysilicon
Answer: (a) brown
20. N-well is formed by
Answer: (b) diffusion
21. Circuit designers need _______ circuits.
Answer: (d) all of the mentioned
22. Process engineers want ______ process.
Answer: (c) reproducible
23. The oxide layer below the first metal layer is deposited using
Answer: (b) chemical vapour deposition
24. Minimum diffusion space is
Answer: (a) 2λ
25. Z can be given as the ratio of
Answer: (b) upper channel by lower channel
26. n and p transistors are separated by using
Answer: Diffusion regions and wells
27. Diffusion and polysilicon layers are connected together using
Answer: Contact cuts
28. _______ layer should be over ______ layer.
Answer: Metal should be over polysilicon
29. When two or more cuts of the same type cross or touch each other, that represents
Answer: A short circuit or incorrect layout
30. Implant is represented using
Answer: Dopant concentration
U-3
31. The subsystem of the circuits should have ______ interdependence
Answer: (a) minimum
32. Pass transistor can be driven through _____ pass transistors.
Answer: (c) more
33. Clocked sequential circuits are
Answer: (b) two-phase non-overlapping clock
34. Register cell consists of
Answer: (c) inverter & pass transistor
35. In Pseudo-nMOS logic, n transistor operates in
Answer: (c) resistive region
36. The power dissipation in Pseudo-nMOS is reduced to about ________ compared to
nMOS device.
Answer: (c) 60%
37. Area A of a slab can be given as
Answer: (c) L * W
38. What is the relationship between channel resistance and sheet resistance?
Answer: (b) R = Z * Rs
39. For signals which are updated frequently _____ is used.
Answer: (b) dynamic storage
40. BiCMOS is used for ____ fan-out.
Answer: (b) more
41. Gate logic is also called as
Answer: Static logic
42. Switch logic is based on
Answer: Transistor switching
43. For a pseudo nMOS design, the impedance of pull-up and pull-down ratio is
Answer: Typically high impedance pull-up with a fixed ratio
44. The switch logic approach takes _____ static current.
Answer: (a) very low static current
45. ___________ is used to drive high capacitance load.
Answer: Buffers or drivers
U-4
46. What is the full form of FPGA?
Answer: (c) Field Programmable Gate Array
47. Which of the following is used by the I/O blocks of an FPGA to drive the I/O pins?
Answer: (b) Tri-state buffers
48. Which of the following is related to a characteristic of FPGA?
Answer: (d) RAM
49. Multipliers are built using
Answer: (a) binary adders
50. Flash memory is a non-volatile storage device in which data
Answer: (c) can be erased electrically
51. Clock signal Φ2 is to
Answer: (c) refresh data
52. Which occupies lesser area?
Answer: (c) CMOS
53. Which is known as the stored test pattern method?
Answer: (a) deterministic test pattern
54. Pseudo static RAM cell is built using
Answer: (b) two inverters
55. Which implementation is slower?
Answer: (b) NOR gate
56. Data storage time is
Answer: Related to memory retention period
57. RAM is a _____ cell.
Answer: Volatile storage cell
58. In NOR type flash memory, data is erased
Answer: In blocks
59. Static RAM uses ____________ transistors.
Answer: Six transistors (6T SRAM)
60. PAL refers to
Answer: Programmable Array Logic
U-5
61. The circuit should be tested at
Answer: (b) chip level
62. Partitioning into subsystems is done at
Answer: (a) design stage
63. The functions performed during chip testing are
Answer: (d) All of the mentioned
64. Delay fault is considered as
Answer: (c) Physical defect
65. The fault simulation detects faults by
Answer: (d) All of the mentioned
66. The poor controllability circuits are
Answer: (d) All of the mentioned
67. The serial shift register is driven using
Answer: (d) two non-overlapping clock
68. The circuit operation is independent of
Answer: (c) propagation delays
69. The boundary scan path is provided with
Answer: (a) serial input pads
70. The circuits with poor observability are
Answer: (d) All of the mentioned
71. ______ of the area is dedicated for testability.
Answer: Approximately 30%
72. Test pattern generation is assisted using
Answer: ATPG tools
73. In scan/set method __________ is used to implement a scan path.
Answer: Multiplexers and flip-flops
74. ATPG stands for
Answer: Automatic Test Pattern Generation
75. Hot carrier injection causes
Answer: Device degradation
