Limits of Scaling MOSFETs

Grant McFarland and Michael Flynn

Technical Report CSL-TR-95-662 (Revised)

November 1995

This work was supported by the NSF under contract MIP93-13701 and by fellowship support from the IBM/CIS Fellow Mentor Advisor Program.

Technical Report CSL-TR-95-662 (Revised)

November 1995 Computer Systems Laboratory Stanford University Gates Building 3A, Room 332 Stanford, California 94305 Email: farland@umunhum.stanford.edu Web: http://umunhum.stanford.edu

by Grant McFarland and Michael Flynn

Limits of Scaling MOSFETs

Abstract
In this paper the fundamental electrical limits of MOSFETs are discussed and modeled to predict the scaling limits of digital bulk CMOS circuits. Limits discussed include subthreshold leakage, short channel e ects (SCE), gate induced drain leakage (GIDL), gate tunneling current, time dependent dielectric breakdown (TDDB), and hot carrier e ects (HCE). This paper predicts the scaling of bulk CMOS MOSFETs for high performance microprocessors to reach its limits at drawn lengths of approximately 0:08 m. Trends in scaling interconnects are also discussed. The device limits presented are used to project the characteristics of future processor technologies and to nd scaling factors for the SPICE level 3 model parameters. A SPICE device model which can be scaled to re ect a range of MOSFET technologies from drawn lengths of 0:5 m to 0:1 m is presented along with a scalable wire model.

Key Words and Phrases: MOSFET, device scaling, interconnect scaling, subthreshold leakage,
short channel e ects, gate induced drain leakage, gate tunneling current, time dependent dielectric breakdown, hot carrier e ects, spice models

Copyright c 1996 by Grant McFarland and Michael Flynn

1 Introduction 2 MOSFET Scaling 3 Limits of Scaling MOSFETs

3.1 3.2 3.3 3.4 3.5 3.6 3.7

Contents

Subthreshold Leakage Currents . . . . . . . . . . Short Channel E ects (SCE) . . . . . . . . . . . Gate Induced Drain Leakage (GIDL) . . . . . . . Gate Tunneling Current . . . . . . . . . . . . . . Time Dependent Dielectric Breakdown (TDDB) Hot Carrier E ects (HCE) . . . . . . . . . . . . . Summary of Scaling Limits . . . . . . . . . . . .

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1 1 4

4 Scaling of Interconnects 5 Scaling the SPICE Level 3 Model

5.1 Scaled SPICE Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Constant SPICE Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 Using the Scaled SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

19 24

6 Conclusion Appendix A { SIA Roadmap Appendix B { Scalable SPICE Device Models Appendix C { Scalable SPICE Wire Models

27 29 29 31

iii

List of Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Trends in Gate Oxide Thickness . . . Trends in Gate Oxide Fields . . . . . . NMOS Device . . . . . . . . . . . . . . Inverter Delay vs Supply . . . . . . . . SCE Maximum TOX ( VT = 0:25VT ) . GIDL Minimum TOX . . . . . . . . . Tunneling Minimum TOX . . . . . . . Gate Oxide Fields vs Year . . . . . . . TDDB Minimum TOX . . . . . . . . . HCE Minimum TOX (t10% = 10 years) Minimum TOX . . . . . . . . . . . . . Limits for VDD = 3.3V . . . . . . . . . Limits for VDD = 2.5V . . . . . . . . . Limits for VDD = 1.8V . . . . . . . . . Projected TOX Scaling . . . . . . . . . Projected LEFF Scaling . . . . . . . . Scaling of Wire Delay . . . . . . . . . Trends in M1 Pitch . . . . . . . . . . . Projections of M1 Thickness . . . . . . Fanout of 4 Inverter Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 6 8 9 11 12 12 14 16 16 17 17 18 18 22 22 23 28

iv

List of Tables
1 2 3 4 5 6 7 8 MOSFET Scaling . . . . . . . . . Device Scaling Laws . . . . . . . Technology Scaling Comparison . Process Variation . . . . . . . . . Scaling Limits Summary . . . . . MOSFET Technology Projection Scaling Local Interconnects . . . MOSFET Technology Projection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 5 15 19 21 24

1 Introduction
For digital circuit design, the ideal MOSFET would be a perfect switch. It would conduct in nite current in the on-state and zero current in the o -state. Scaling of the device dimensions has been e ective at increasing the on-current of the device, but at the same time it causes an increase in the o -current. For an NMOS device with the drain at the supply voltage and the source, gate, and bulk at ground, ideally there should be no current ow. However, for submicron devices, there may be signi cant drain current to the source as subthreshold leakage, to the gate as tunneling current, and to the bulk as gate-induced drain leakage. The need to minimize these leakage currents while at the same time increasing on-current limits the scaling of MOSFETs. Another characteristic of an ideal MOSFET would be an in nite lifetime. Unfortunately, real devices tend to degrade when exposed to high electric elds in either the gate oxide or the channel. High eld phenomenon, such as time dependent dielectric breakdown and hot carrier e ects, are especially worrisome since they can cause a chip to suddenly fail after operating correctly for months or even years. Therefore, reliability concerns further limit practical device designs. This paper examines how MOSFETs have been scaled in recent years and how leakage currents and reliability limit their future scaling. A brief discussion of the scaling of interconnects is also presented. Finally, scalable SPICE level 3 device models and a scalable wire model are derived to re ect the trends predicted.

2 MOSFET Scaling
Since MOSFET integrated circuits were rst invented, fabrication engineers have steadily scaled devices to improve performance. A generalized scaling scheme is shown in table 1. In this table the Table 1: MOSFET Scaling Description General Scaling Device Dimensions 1=SL Oxide Thickness 1=ST Power Supply 1=SV Gate Capacitance ST =SL2 Current ST =SV 2 { ST =(SV SL) Delay SV =SL2 { 1=SL ranges for current and delay are for devices that experience no carrier velocity saturation compared to devices that are completely velocity saturated. Table 1 shows that the most e ective way to reduce delay is to reduce the device dimensions. This has been the primary goal of industry research. 1

Scaling the gate oxide thickness improves current drive but increases the gate capacitance at the same time. Scaling the oxide improves performance because the wire capacitance is not similarly increased. However, the improvement is less than that gained by scaling the device length. The scaling of devices combined with the scaling of interconnects has allowed more devices, and therefore more functionality, to be placed on a single chip. This combination of reduced delay and increased integration has dramatically improved computer performance. The most famous systematic scheme for scaling MOSFET devices is called constant eld scaling and was proposed by Robert Dennard in 1974 10]. In constant eld (CE) scaling, all of the horizontal and vertical dimensions are scaled with the power supply to maintain constant electric elds throughout the device. Other proposed scaling schemes include quasi-constant voltage (QCV) scaling and constant voltage (CV) scaling 8]. Quasi-constant voltage scaling reduces the supply voltage more slowly than constant eld scaling. Constant voltage scaling maintains a constant power supply and scales the gate oxide thickness more gradually to slow the growth of elds in the oxide. These three scaling schemes are summarized in the table 2. Table 2: Device Scaling Laws Description Parameter Constant Quasi-Constant Constant Field (CE) Voltage (QCV) Voltage (CV) Device Dimensions L, W 1=S 1=S 1=S p Oxide Thickness TOX 1=S 1=S 1= S p Power Supply VDD 1=S 1= S 1 Channel Doping NSUB S S S To see which of these three schemes best re ects past trends in the industry, gate oxide thickness versus e ective channel length is plotted for various CMOS processes in gure 1. This gure shows that oxide thickness and channel length have scaled at roughly equal rates. This is consistent with either constant eld scaling or quasi-constant voltage scaling. These two scaling schemes are distinguished by observing how the gate oxide eld has scaled. This is shown in gure 2. Clearly the oxide elds are not unchanged as is predicted by constant eld scaling. Instead, the data shows p elds increasing at a rate which matches well with the S rate predicted by quasi-constant voltage scaling. An example of how closely industry has followed QCV is shown in table 3 by comparing CE and QCV scaling on the base technology provided in Dennard's paper to a modern fabrication process. Both scaling schemes predict values for TOX and NSUB which are very close to those of the modern process. However, CE scaling also predicts a power supply voltage more than a factor of 2 too low, while QCV scaling very accurately predicts the supply voltage. There are two principle reasons why the industry has been reluctant to scale voltages. The rst is the di culty in designing circuit boards for chips designed to operate at di erent voltages. Secondly, scaling the power supply tends to increase delay. This has caused chip foundries to avoid scaling power supplies as long as possible. While constant eld scaling has been a good predictor of oxide thicknesses and doping 2

Tox (nm)

30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0

2.5 | 0.1

| |
Tox=1/S

| | | | | | | | |

|
0.3

|
0.5

|
0.7

|
0.9

|
1.1

|
1.3

|
1.5

| | | | | | | | | |

Figure 1: Trends in Gate Oxide Thickness

Eox (MV/cm)
5.5

Leff (um)

5.0

4.5

4.0

Eox=sqrt(S)

3.5

3.0

2.5

2.0

1.5

1.0 | 2.5

|
7.5

|
12.5

|
17.5

|
22.5

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27.5

|
32.5

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37.5

|
42.5

|
47.5

Figure 2: Trends in Gate Oxide Fields 3

Tox (nm)

Table 3: Technology Scaling Comparison Parameter L=5 m 1974 10] L=0:8 m (CE) L=0:8 m (QCV) L=0:8 m11993 TOX 1000A 160A 160A 175 A NSUB 5 1015cm?3 3 1016cm?3 3 1016cm?3 4 1016cm?3 VDD 12V 2V 4:8V 5V levels, it has not been a good predictor of power supply voltages or device performance. QCV scaling is a much better indicator of past trends in device scaling. However, QCV allows elds in the channel and in the gate oxide to increase. This means that QCV scaling can not be continued inde nitely. In order to determine how device parameters will be scaled in the future, the speci c electrical limitations of MOSFETs must be examined.

3 Limits of Scaling MOSFETs

The following sections describe the leakage currents and reliability concerns that limit the scaling of MOSFETs. The basic MOSFET considered is a lightly doped drain (LDD) double implanted NMOS device shown in gure 3 1, 28, 41, 43]. The lightly doped drain reduces the maximum
Ldrawn Silicide N+ Poly HDIF HDIF LD NN+ Source Nsub Nbulk Leff Vt Implant Tox Silicide NXj N+ Drain S/D Depth

Figure 3: NMOS Device electric eld in the channel and therefore reduces hot carrier e ects. The lightly doped extensions on the source and drain are made shallower than the di usion under the contacts to reduce short channel e ects. A silicide layer is added to the heavily doped di usion regions and polysilicon gate to reduce resistance. The device is made on a lightly doped substrate to provide low junction capacitances with a deep implant into the channel region to prevent punchthrough and short channel e ects. A shallow implant at the Si-SiO 2 interface sets the desired threshold voltage. In general, all of the limitations considered in this paper could also be applied to a PMOS device. If the PMOS device uses a P+ poly gate then each of these limitations is the same as
1

MOSIS HP CMOS26B Process

for the NMOS device (except for hot carrier e ects). However, many current processes use N+ poly gates for both the NMOS and PMOS devices. This is because N+ poly has lower resistance and because the boron dopant within P+ poly tends to di use through gate oxides and cause threshold shifts. If an N+ poly gate is used for a PMOS device, the low atband voltage makes the threshold so negative that a P-type threshold implant is typically used. This forms a buried channel device in which the channel extends much deeper than in a typical surface channel device. Buried channel devices tend to be more sensitive to subthreshold leakage, short channel e ects, and hot carrier e ects 15, 19]. Therefore, it seems likely that as MOSFETs are scaled into the deep submicron regime, buried channel devices will be intentionally drawn with longer channels or abandoned entirely. Therefore, the limitations on buried channel devices are not considered in this paper. In any integrated circuit fabrication process there will be some variation in the device parameters. To produce chips with acceptable yields, the typical device parameters must be chosen so that the device requirements are met for reasonable range of process corners. This paper assumes the process corners shown in table 4. In the following sections typical parameter values are chosen so that the limits presented are met for the worst case variation in all of these parameters. Table 4: Process Variation Description Parameter Variation Power Supply VDD 10% Oxide Thickness TOX 25% Channel Length LEFF 20% Threshold Voltage VTVAR 80mV

Simple MOSFET models assume that the drain to source current is zero for VGS < VT . In reality the current decreases exponentially as the gate voltage drops below the threshold. Grotjohn 11] writes this current as:

3.1 Subthreshold Leakage Currents

IDS = ( ? 1) 2 exp VGS ? VT t

t

1 ? exp ?VDS
t

(1) (2) (3)

= COX W L = 1+

EFF CDEP COX

where t is the thermal voltage and CDEP is the capacitance of the channel depletion region. The slope of this subthreshold current is: d(VGS ) = ln 10 (4) d(log IDS ) t For a typical device at room temperature this slope is approximately 80 mV=decade, and the subthreshold slope is always greater than the best case where CDEP COX and the slope is 60 mV=decade. d(VGS ) (5) d(log IDS ) 80 mV=decade > 60 mV=decade The on/o current ratio of a device is de ned as the ratio of the current at VGS = 0 to the current at VGS = VT . The smaller this ratio the less signi cant subthreshold leakage is for a particular technology. For large chips with millions of devices, a current ratio of at least 104 is desirable 22]. IDS (VGS = VT ) > 104 (6) IDS (VGS = 0) Assuming a typical subthreshold slope and a worst case threshold variation of VTVAR gives the required minimum threshold. d(V (7) VT > 4 d(logGS ) ) + VTVAR = 0:4V IDS Because currents drop o exponentially in the subthreshold regime, circuits designed to switch using primarily subthreshold currents face severe performance penalties as shown in gure 4. For high performance operation the power supply voltage must be su ciently greater than VT so that the devices spend most of their switching time out of the subthreshold regime. Analyzing performance as a function of VDD =VT shows that a good requirement for high performance operation is 31]:

VDD > 3 VT > 1:2V

(8)

Therefore, subthreshold currents and the need for high performance limit the extent to which the supply and threshold voltages can be scaled.

3.2 Short Channel E ects (SCE)

As MOSFET channel length is reduced, the device threshold becomes dependent on the e ective channel length (LEFF ) and the drain to source voltage (VDS ). These deviations from the ideal threshold model are known as short channel e ects (SCE). The e ect of the drain voltage alone on the threshold is known as drain induced barrier lowering (DIBL) 40]. Short channel e ects limit the scaling of MOSFETs by reducing the threshold of the device and causing large increases in the subthreshold leakage currents. As the device dimensions are reduced, the source and drain regions begin to deplete signi cant portions of the channel. This reduces the charge in the channel which is matched by the gate and therefore reduces the threshold voltage. At very high VDS the depletion regions of the source and drain may touch causing large amounts of 6

| | | | | | | |

Relative Delay

0| 1.0

|
1.5

|
2.0

|
2.5

|
3.0

|
3.5

|
4.0

|
4.5

|
5.0

current to ow uncontrolled by the gate. This phenomenon is known as punchthrough. All these e ects are reduced by increasing the channel doping to reduce the size of the source and drain depletion regions and by decreasing the gate oxide thickness to give the gate more control over the channel region. A model presented in 1993 by Liu and intended for use with devices down to 0:1 m estimates the change in threshold due to SCE 21].
q VT = 3(Vbi ? s ) + VDS ] exp ?LlEFF + 2 (Vbi ? s)(Vbi ? s + VDS ) exp ?LEFF 2l

where Vbi is the built-in potential between the source/drain regions and the channel, s is the band bending in the channel at the onset of inversion, and XDEP is the channel depletion width. The ratio between the gate oxide thickness and the channel depletion width is determined by the long channel threshold VTO . p2q N Si SUB s + qDV T = V + + 2 Si s + qDV T V =V + + (11)
TO FB s

where VFB is the atband voltage, and DV T is the shallow implant dose. For the case of no shallow implant (DV T = 0), the threshold voltage must be set entirely by the deep implant which sets 7

Vdd/Vt

Figure 4: Inverter Delay vs Supply

(9) (10)

l = 0:1 m

"

XJ m

TOX A

# XDEP 2 1=3 m

COX

COX

FB

COX XDEP

COX

NSUB . In this case XDEP is as follows: XDEP = V 6TOX s? (12) TO ? VFB s The desired threshold is assumed to vary linearly from 0:8V at a supply of 5V down to 0:4V at a supply of 1:2V . VT = 0:275V + 0:105VDD (13)
A reasonable requirement is to limit the change in threshold due to SCE to one quarter of the desired threshold ( VT < 0:25VT ). For a given supply voltage and channel length, this restriction limits how thick a gate oxide may be used. Figure 5 shows these results for the worst case process variations. For oxides less than this maximum thickness, a lighter deep implant may be used and the desired threshold voltage set with a shallow implant.
Tox (nm)
22.5

|
Vdd=3.3V Vdd=2.5V Vdd=1.8V Vdd=1.2V

20.0

| | | | | | | |

17.5

15.0

12.5

10.0

7.5

5.0

2.5

0.0 | 0.05

|
0.10

|
0.15

|
0.20

|
0.25

|
0.30

|
0.35

|
0.40

|
0.45

|
0.50

Leff (um)

Figure 5: SCE Maximum TOX ( VT = 0:25VT )

In addition to subthreshold leakage from the drain to the source, MOSFETs with high oxide elds may also show signi cant leakage from the drain to the bulk. This phenomenon is known as subbreakdown drain leakage 9] or gate induced drain leakage 7]. High elds in the oxide produce high elds in the surface of the silicon. In the heavily doped gate-to-drain overlap region, this produces band bending greater than the silicon band gap over a very short vertical distance. Within this depleted region at the surface of the drain, electrons may tunnel from the valence band into the conduction band producing a drain to bulk current. This tunneling may be assisted by interface traps within the band gap 27, 44]. The vertical eld at the surface of the drain is written as: V OX ESI = ox EOX = 3VT = VDG ? T FB ? s (14) 3 where s is the band bending within the silicon, and VFB is the atband voltage between the gate and drain. The current density is the highest where the band bending is equal to the silicon band gap of approximately 1:2V . If the gate and drain are the same doping type, the atband voltage is zero which gives the following: ? ESI VDG T 1:2V (15) 3
OX Si OX OX

3.3 Gate Induced Drain Leakage (GIDL)

For a lightly doped drain device, the lateral electric eld is typically much smaller than the vertical eld and does not signi cantly increase the e ective eld 30]. GIDL is directly proportional to the device width but is not a function of the device length since it occurs only in the gate-to-drain overlap region. Parke 30] models the GIDL current per width as:
2 ? IGIDL =W = AESI exp E B B SI A 1 10?4 A=V B = 45 MV=cm

(16)

(17) This model allows a minimum oxide thickness to be calculated for a given power supply and maximum GIDL current desired. These results for the worst case process corner are shown in gure 6. The ultimate limit on the thickness of gate oxide layers may be tunneling currents. One of the basic principles of quantum mechanics is that particles do not have well de ned locations, but instead exist only with a certain probability within a given region. A consequence of this is that for particles with very little mass isolated by very thin energy barriers, there is a nite probability that the particle will appear on the far side of the barrier even though it does not have su cient energy to surmount the barrier. This phenomenon, which is observed to occur but is impossible by the classical laws of physics, is known as tunneling. As gate oxides are scaled down below 10 nm, signi cant tunneling current may ow from the drain to the gate in an o device or from the gate to the source in an on device. In the worst case the voltage across the gate oxide (VOX ) is approximately the power supply voltage. If the voltage across the oxide is greater than the oxide energy barrier ( B = 3:25V ), the electrons pass 9

3.4 Gate Tunneling Current

Tox (nm)

10

|
I=0.1(pA/um) I=10(pA/um) I=1(nA/um) I=100(nA/um)

| | | | | | | | |

0| 1.0

|
1.5

|
2.0

|
2.5

|
3.0

|
3.5

|
4.0

|
4.5

|
5.0

through a triangular energy barrier and undergo Fowler-Nordheim tunneling 37]. Yoshida models the tunneling current density as 46]:
2 AFN = 8 q = 474 nA=V 2 h B

where mFN is the electron e ective mass for Fowler-Nordheim tunneling and is equal to 0:34m0. If the voltage across the oxide is less than the oxide energy barrier, the electrons pass through a trapezoidal energy barrier and undergo direct tunneling. In this region tunneling current density is modeled as follows 46]: 2 (21) ADT = 2q h = 6:17 A=V

Vdd (V)

Figure 6: GIDL Minimum TOX

(18) (19) (20)

2qmFN 3=2 = 233 MV=cm B BFN 3h JFN = AFN EOX 2 exp ?BFN E =8
OX

BDT

=4

nm V DT = B ? VOX =2
10

2qmDT = 5:52 p h

(22) (23)

where mDT is the electron e ective mass for direct tunneling and is equal to 0:29m0. These two sets of equations allow a minimum oxide thickness to be calculated for a given power supply and the worst case tunneling current density desired. These results are shown in gure 7.
Tox (nm)
9

h JDT = ADT2 TOX

DT exp

?BDT TOX

DT

B exp

?BDT TOX

(24)

|
J=0.1(pA/um^2) J=10(pA/um^2) J=1(nA/um^2) J=100(nA/um^2)

| | | | | | | |

0| 1.0

|
1.5

|
2.0

|
2.5

|
3.0

|
3.5

|
4.0

|
4.5

|
5.0

3.5 Time Dependent Dielectric Breakdown (TDDB)

tBD = 0 exp EG OX

Fields within the gate oxide have been steadily increasing as power supplies are scaled more slowly than oxide thickness. Experiments have shown that over time very high elds damage the oxide layer and eventually cause breakdown 45]. The time to breakdown is commonly written as: (25)

where G is the breakdown acceleration factor, 0 is a time constant, and EOX is the eld in the oxide. At 25 C typical values for G and 0 are 350 MV=cm and 1 10?11 sec 26]. At 125 C , tBD is found to be reduced by a factor of 20 compared to lifetimes at 25 C 36]. For a 10 year lifetime at 125 C , equation 25 gives a gate oxide eld of approximately 7:3 MV=cm. The limit on the typical supply voltage and oxide thickness is set by making this value the maximum eld for the case of 11

Vdd (V)

Figure 7: Tunneling Minimum TOX

high supply voltage and thin oxide.

(27) Figure 8 shows that elds in the gate oxide have been steadily increasing until today it is common to nd parts with elds very close to the 10 year breakdown limit. The restriction TDDB places upon minimum oxide thickness is shown in gure 9 as a function of the power supply and desired minimum lifetime. This gure shows that because breakdown tends to accelerate very rapidly once it has begun, changing the required lifetime of the oxide has little e ect on the minimum thickness required. Lateral elds within the channel have been steadily increasing as power supplies are scaled more slowly than channel length. At su ciently high elds electrons may gain enough energy to cause impact ionization in the channel. The energetic carriers produced lead to gate and substrate current. Interface traps may also be formed and hot electrons may become trapped within the gate oxide. This build up of traps and negative charge in the oxide causes NMOS thresholds to increase and their transconductance to decrease. Eventually reduced current drive causes the circuit containing the degraded device to fail. NMOS and PMOS devices both experience hot carrier e ects, but the lower mobility of holes and their reduced ability to cause impact ionization makes hot carrier e ects much less signi cant in PMOS devices 15]. The lifetime of a device (de ned as the time until a 10% reduction in transconductance) is found to be related to the substrate current by the following relation 16, 17, 20, 39]: ?2:9 W / I ISUB (28) I The substrate current is modeled as follows:
D D

VDD (1 + VDD) < 7:3 MV=cm TOX (1 ? TOX ) EOX = VDD=TOX < 5:0 MV=cm

(26)

3.6 Hot Carrier E ects (HCE)

ISUB =ID = 2 exp

i EMAX

(29)

where i = 1:3V is the minimum energy for a hot-electron to cause impact ionization, is the hotelectron mean-free-path (78 A), and EMAX is the maximum lateral electric eld in the channel. The only unknown in this equation is the lateral electric eld. Kakumu 20] has empirically determined this to be: ? EMAX = VD+ lVDSAT (30) l where VDSAT doped portion of the drain. Thinning the gate oxide makes hot carrier e ects worse by moving the 12 (31) cm is the potential at the pinch-o point, and lLDD is the e ective length of the lightly

l = 0:02 cm cm

LDD TOX 1=3 XJ 1=3

Eox (MV/cm)

5.0

|
10 year TDDB Limit

4.5

| | | | | | |

4.0

3.5

3.0

2.5

2.0

1.5

1.0 | 80

|
82

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84

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86

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88

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90

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92

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94

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96

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98

| | | | | | | | | | | | |

Year

Figure 8: Gate Oxide Fields vs Year

Tox (nm)
11 10 9 8 7 6 5 4 3 2 1

Tbd=100 years Tbd=10 years Tbd=1 year

0| 1.0

|
1.5

|
2.0

|
2.5

|
3.0

|
3.5

|
4.0

|
4.5

|
5.0

Vdd (V)

Figure 9: TDDB Minimum TOX 13

pinch-o point closer to the drain, and therefore increasing the lateral electric eld. Hu 17] models the voltage at the pinch-o point as: ( ) VDSAT = VVG ? VT+LEFF ESAT (32) G ? VT LEFF ESAT where ESAT is the carrier velocity saturation eld of approximately 5 104 V=cm for electrons. The saturation current per unit width (ID =W ) is proportional to VDSAT as follows:
2 ID =W / LVDSAT T
EFF OX

(33)

In this equation K is a technology constant which may vary over a wide range depending upon the details of the fabrication process, such as what kind of gate oxide anneals are performed and the exact location of the maximum lateral eld with respect to the gate. A reasonable value chosen for this study is K = 0:8(V 2 year= m2 ). This value is chosen so that a typical device has a 10 year lifetime at a lateral eld of approximately 0:45 MV=cm. A common means for reducing hot carrier e ects is the use of a lightly doped drain (LDD). By rst performing a light implant and then using oxide spacers left on either side of the gate to mask a second heavy implant, the doping pro le of the source and drain is made much more gradual which reduces EMAX . How much EMAX is reduced depends on the length of the lightly doped portion of the drain (lLDD ), however because of its light doping this region has a high resistance and as its length is increased performance su ers. Typically EMAX is reduced to between 60% and 70% of its value in a comparable standard device without severe performance penalties 23]. This paper assumes the drain junction depth is one half the e ective channel length. The e ective length of the lightly doped drain has been found empirically to be approximately one third the junction depth 20]. XJ LEFF =2 lLDD XJ =3 (35) Using these equations, the minimum TOX of an LDD device for a 10 year lifetime at VG = VD = VDD is shown in gure 10 as a function of power supply and channel length for the worst case process corner. The limitations presented in this paper are summarized in table 5 as a list of speci c requirements for a reliable, high performance, low leakage MOSFET. Subthreshold leakage limits the supply and threshold voltages to above 1:2V and 0:4V respectively. The limitations of GIDL, tunneling current, and TDDB restrict the allowable elds in the oxide and are independent of the channel length. In gure 11 these three requirements are plotted as functions of the power supply. This gure shows that for supply voltages of 1:3V and above, TDDB limits the minimum oxide thickness. For supply 14

Combining equations 28 and 33 gives the following relation for the time to a 10% reduction in transconductance: ?2:9 t10% = K LEFF TOX ISUB (34) 2 I

VDSAT

3.7 Summary of Scaling Limits

Tox (nm)

25.0

|
Vdd=3.3V Vdd=2.5V Vdd=1.8V Vdd=1.2V

22.5

| | | | | | | | |

20.0

17.5

15.0

12.5

10.0

7.5

5.0

2.5

0.0 | 0.05

|
0.10

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0.15

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0.20

|
0.25

|
0.30

|
0.35

|
0.40

Table 5: Scaling Limits Summary Limit Criteria Subthreshold Leakage ID (VG = VT )=ID (VG = 0) > 104 Short Channel E ects VT < 0:25VT Gate Induced Drain Leakage IGIDL =W < 100nA= m Gate Tunneling Current JTUN < 100nA= m2 Time Dependent Dielectric Breakdown tBD > 10 years Hot Carrier E ects t10% > 10 years

Leff (um)

Figure 10: HCE Minimum TOX (t10% = 10 years)

15

Tox (nm)

10

|
Tbd=10 years Itun=100(nA/um^2) Igidl=100(nA/um)

| | | | | | | | |

0| 1.0

|
1.5

|
2.0

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2.5

|
3.0

|
3.5

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4.0

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4.5

|
5.0

voltages below 1:3V , gate tunneling current becomes the limiting factor. For these desired leakage currents, GIDL is never a limitation. Short channel e ects restrict the maximum oxide thickness, and hot carrier e ects restrict the minimum channel length. Combining these requirements with the restrictions on the oxide eld allows the minimum channel length at a given supply voltage to be predicted. Figures 12, 13, and 14 show these restrictions compared to actual microprocessor technologies for supplies of 3:3V , 2:5V , and 1:8V respectively. Projecting out to the predicted minimum VDD of 1:2V gives the expected characteristics of future bulk MOSFET generations shown in table 6. In gure 15 these projected oxide thicknesses are compared to the SIA roadmap 3] (see appendix A) and projections from a recent paper by Chemming Hu 18]. The SIA roadmap appears slightly conservative, as processors have been manufactured with thinner oxides than it predicts. All the processors have thicker oxides than the limits projected by this work and Hu. Figure 16 compares the minimum channel length from the same projections used in the previous gure and an empirical equation for minimum channel length presented by Brews 6]. This equation is as follows: LEFF > K (XJ TOX (WS + WD )2 )1=3 (36) where K = 0:41A?1=3, and WS and WD are the depletion widths at the source and drain.

WS = 2 Si Vbi qNSUB

Vdd (V)

Figure 11: Minimum TOX

Vbi WD = 2 Si (qN + VDD ) SUB

16

(37)

Tox (nm)

20.0

SCE HCE TDDB Processors

| | | | | |

17.5

15.0

12.5

10.0

7.5

5.0 | 0.15

|
0.20

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0.30

|
0.35

|
0.40

|
0.45

|
0.50

|
0.55

| | | | | | | |

Leff (um)

Figure 12: Limits for VDD = 3.3V

Tox (nm)
15.0
SCE HCE TDDB Processors

12.5

10.0

7.5

5.0

2.5

0.0 | 0.10

|
0.15

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0.20

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0.25

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0.30

|
0.35

Leff (um)

Figure 13: Limits for VDD = 2.5V 17

Tox (nm)

15.0

|
SCE HCE TDDB Processors

12.5

| | | | |

10.0

7.5

5.0

2.5

0.0 | 0.05

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0.10

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0.15

|
0.20

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0.25

|
0.30

Table 6: MOSFET Technology Projection VDD (V ) 5.0 3.3 2.5 1.8 1.5 1.2 LDRAWN ( m) 0.52 0.32 0.23 0.15 0.12 0.08 LEFF ( m) 0.39 0.24 0.17 0.11 0.09 0.06 XJ (nm) 195 120 85 55 45 30 TOX (nm) 10.0 6.6 5.0 3.6 3.0 2.6 VT (V ) 0.80 0.62 0.54 0.46 0.43 0.40 VTL(mV ) 35 30 30 30 30 30 VTDIBL(mV ) 165 125 105 85 80 70 NSUB (cm?3) 4:0 1016 7:2 1016 1:1 1017 1:7 1017 2:2 1017 3:5 1017 DV T Dose(cm?2) 2:3 1012 2:7 1012 3:1 1012 3:8 1012 4:2 1012 4:1 1012 18

Leff (um)

Figure 14: Limits for VDD = 1.8V

Tox (nm)

10

|
Processors SIA McFarland C.Hu

| | | | | | |

2| 1.0

|
1.5

|
2.0

|
2.5

|
3.0

|
3.5

| | | | | | | |

Figure 15: Projected TOX Scaling

Leff (um)
0.30
Processors SIA Brews McFarland C.Hu

Vdd (V)

0.25

0.20

0.15

0.10

0.05

0.00 | 1.0

|
1.5

|
2.0

|
2.5

|
3.0

|
3.5

Figure 16: Projected LEFF Scaling 19

Vdd (V)

It is assumed that XJ = 0:5LEFF . The oxide thicknesses from table 6 are used and the doping levels are set to give the long channel thresholds in table 6. These equations are then used to estimate the minimum acceptable channel length at a given supply voltage. All of these projections are in very close agreement except for those made by Hu. These points seem overly optimistic when compared to actual processor technologies. The projections made by Hu would indicate that 3:3V technologies could continue to e ective channel lengths of 0:15 m. However, current state of the art processes with channel lengths between 0:20 m and 0:25 m are already moving to 2:5V . Since the industry has historically been extremely reluctant to scale voltages, this suggests that these processes could not be used at 3:3V . The minimum channel lengths predicted by this work, the SIA roadmap, and Brews equation all correctly predict this move to a lower voltage at channel lengths below approximately 0:25 m. Scaling the horizontal and vertical dimensions of the device without scaling the supply voltage causes the electric elds in the device to increase to unacceptable levels. However, the supply voltage can not be scaled inde nitely without giving up either high performance operation or a high ratio of on-current to o -current. The projected parameters for the allowable range of supply voltages is summarized in table 6. These limitations prevent current bulk CMOS devices from begin scaled below drawn lengths of approximately 0:1 m.

4 Scaling of Interconnects
Much of the dramatic improvement in computer performance has been due to increasing levels of integration. The ability to pack more devices into a single die allows for higher performance implementations requiring more devices or for more functionality to be provided at lower cost. However, these bene ts could not be gained from scaling devices alone. The interconnects which provide for communication between the devices must be scaled as well. Many studies have predicted that the resistance and capacitance of these wires will have an increasingly large impact on the overall circuit delay 4, 32, 35]. When scaling a chip from one technology to the next, the basic functional units are reduced in size, reducing the needed length of the local interconnect wires. However, as more functionality is added to the chip, the overall die size increases requiring longer global interconnect wires 4]. The trend toward shorter local wires and longer global wires has forced the rst two levels of interconnect to be scaled di erently from the top levels used for global signals, the clock, power, and ground. The scaling of these global wires is highly dependent on the overall die size and the clock frequency desired. Therefore, only scaling of local interconnects is considered here. The resistance of a line of a single material per unit length is written as

is its thickness. Aluminum is the most commonly used interconnect material, but typically thin layers of refractory metals (Ti, TiW, TiN) are used on the top and bottom of the aluminum lines to provide better contacts, adhesion, or barriers to di usion. These layers reduce the aluminum thickness and increase the overall resistance of the wire. This e ect is modeled by calculating the 20

RL = W T (38) INT INT where is the resistivity of the interconnect material, WINT is the interconnect width, and TINT

total wire resistance as the parallel combination of the aluminum layer and constant thickness TiN layers on the top and bottom of the wire.

RAl = (T

INT ? 2TTiN )WINT TiN TiN WINT

Al

(39) (40) (41)

where TTiN is the constant thickness of the TiN layers which is assumed to be 50nm. To properly model the capacitance per unit length, the area and fringe capacitance to the substrate as well as coupling capacitance to adjacent wires must be taken into account. An empirical model of capacitance is as follows 34]:
0:222 T CSUB = ox = 1:15 WINT + 2:8 T INT (42) TFOX FOX # " WINT + 0:83 TINT ? 0:07 TINT 0:222 WSP ?1:34 (43) CCOUP = ox = 0:03 T TFOX TFOX TFOX FOX CTOTAL = CSUB + 2 CCOUP (44) where TFOX is the thickness of the eld oxide, and WSP is the width of the space between adjacent

RL = 1=R +11=R Al TiN

RTiN = 2T

lines. These models for resistance and capacitance are used to compare the three basic interconnect scaling schemes, ideal scaling, quasi-ideal scaling, and constant-R scaling shown in table 7 4]. Table 7: Scaling Local Interconnects Description Parameter Ideal Quasi-Ideal Scaling Scaling Width WINT 1=S 1=S Spacing WSP 1=S 1=S p Thickness TINT 1=S 1= S p Field Oxide TFOX 1=S 1= S p Aspect Ratio Ar 1 S Res per Length Cap per Length RC per Length2

Constant-R Scaling p 1= S p 1= S p 1= S p 1= S 1

RL CL RLCL

S2 S2
1

S 1:5 0:9 + 0:1S 0:9S 1:5 + 0:1S 2:5

S
1

21

Ideal scaling reduces the horizontal and vertical dimensions of the interconnect at the same rate as the devices are scaled. Constant-R scaling reduces all the wire dimensions more slowly than the device scaling. Quasi-ideal scaling performs ideal scaling of the horizontal dimensions but scales the vertical dimensions more slowly. For quasi-ideal scaling the equations for the scaling of capacitance and delay are approximations assuming that all the horizontal and vertical dimensions are equal in the base technology. The scaled wire delay per unit length is shown in gure 17. Constant-R scaling is clearly superior in minimizing delay, however this scheme leads to severely
Relative Delay per Length2
100

| |
Ideal Scaling Quasi-Ideal Scaling Constant-R Scaling

90

80

| | | | | | | |

70

60

50

40

30

20

10

0| 1

|
2

|
3

|
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|
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8

|
9

|
10

wire limited layout and may limit the achievable level of integration. Figure 18 shows the rst level metal wiring pitch of a wide range of fabrication processes compared to the drawn device size. This gure shows that wire pitches have scaled with the device size, and that constant-R scaling has not occurred. This gure is consistent with either ideal scaling or quasi-ideal scaling. Ideal scaling has the advantage of keeping a constant aspect ratio, but it has the worst delay of the three schemes. Therefore, in order to avoid becoming severely wire limited while keeping wire delay to a minimum, quasi-ideal scaling is a good middle ground. In modern processes, high aspect ratio wires and vias are implemented using chemical mechanical planarization (CMP) after each wiring level and chemical vapor deposition (CVD) of tungsten into via holes 33, 38]. Future projections of realizable interconnection thicknesses (shown in gure 19) predict that quasi-ideal scaling will continue into deep submicron technologies 5, 25, 29].

Scale

Figure 17: Scaling of Wire Delay

22

M1 Pitch (um)

5.0

|
Wint=1/S

4.5

| | | | | | | | |

4.0

3.5

3.0

2.5

2.0

1.5

1.0

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0.35

|
0.60

|
0.85

|
1.10

|
1.35

|
1.60

| | | | | | |

Ldrawn (um)

Figure 18: Trends in M1 Pitch

Tint (um)
0.8
Bothra93 Mii92 Oh92

0.7

0.6

0.5

Tint=1/sqrt(s)

0.4

0.3 | 0.0

|
0.2

|
0.4

|
0.6

|
0.8

|
1.0

|
1.2

Wint (um)

Figure 19: Projections of M1 Thickness 23

5 Scaling the SPICE Level 3 Model

The delay of circuits fabricated in future IC technologies is an important factor in what types of computer architectures and applications will be possible. This paper presents a scalable SPICE device model which allows the delay of any circuit to be simulated for a wide range of technologies. The level 3 model was chosen because it is a reasonable balance of accuracy and complexity. The projections for some of the basic device and model parameters as well as their scaling factors are shown in table 8. The basic model parameters TOX , NSUB , and VTO are set to their initial values for the 0:5 m base technology and then scaled according to the factors given in table 8. The remaining model parameters are either scaled the same way using scaling factors which are functions of the basic parameter scaling factors or assumed to be constant across technologies. Table 8: MOSFET Technology Projection LDRAWN ( m) 0.52 0.32 0.23 0.15 0.08 1=SL 1=S LEFF ( m) 0.39 0.24 0.17 0.11 0.06 1=SL 1=S XJ ( m) 195 120 85 55 30 1=SL 1=S VDD(V ) 5.0 3.3 2.5 1.8 1.2 1=SVDD 1=S 0:79 TOX(nm) 10.0 6.6 5.0 3.6 2.6 1=STOX 1=S 0:76 NSUB (cm?3) 4:0 1016 7:2 1016 1:1 1017 1:7 1017 3:5 1017 SSUB S 0:92 VTO(V ) 0.97 0.74 0.64 0.55 0.47 1=SVT 1=S 0:40 VTDIBL(V ) 0.17 0.12 0.10 0.086 0.071 1=SDIBL 1=S 0:47

5.1 Scaled SPICE Model Parameters

CJ { Bottom Junction Capacitance (F=m2 )

The zero bias capacitance per unit area of the bottom junction of the source and drain regions. CJ is a function of the built-in junction voltage PB and the bulk doping concentration which is assumed to be one tenth the doping in the channel to avoid bulk punchthrough 31].
s

CJ =

Si q (NSUB=10)

2PB

/ SSUB

(45)

CJGATE { Gate-Edge Sidewall Junction Capacitance (F=m)

24

The zero bias fringing capacitance of the gate-edge sidewalls of the source and drain regions. CJGATE is a function of the doping in the channel and the junction depth.

CJGATE = XJ

Si qNSUB

2PB

pS / SSUB L

(46)

CJSW { Sidewall Junction Capacitance (F=m)

s

The zero bias fringing capacitance of the sidewalls of the source and drain regions. CJSW is a function of the bulk doping concentration and the junction depth.

CJSW = XJ

Si q (NSUB=10)

ETA { Drain Induced Barrier Lowering Factor ETA controls the decrease in threshold due to DIBL. In this paper ETA is set to give the same VTDIBL as given in table 8. K is a constant used by SPICE with a value of 2:36 10?11 m2. 3 V ETA = KTDIBL LEFF / SVDD STOX (48) TOX VDD SDIBL SL3 HDIF { Heavy Di usion Length (m)
The length of the heavily doped di usion from the center of the contact to the lightly doped region. HDIF = 5=4LDRAWN / 1=SL (49)

2PB

pS / SSUB L

(47)

LD { Lateral Dopant Di usion (m)

The lateral di usion of the source and drain underneath the gate edge.

RS { Lightly Doped Di usion Sheet Resistance ( =2)

LD = LDRAWN2? LEFF / 1=SL

(50)

RSH { Heavily Doped Di usion Sheet Resistance ( =2)

The sheet resistance of the lightly doped portion of the source/drain regions. Assuming a doping concentration of 1018 cm?3 gives resistivities of 200 m for n-type and 400 m for p-type. (51) RS = XJ / SL The sheet resistance of the heavily doped portion of the source/drain regions. A doping concentration of 1020 cm?3 gives resitivities of 8 m for n-type and 10 m for p-type. This work assumes that the junction depth of the heavily doped source/drain regions is twice that of the lightly doped regions. Also a silicide layer of TiSi 2 is assumed with resistivity of 0:15 m and a thickness of one fth the heavily doped junction depth. (TiSi2 (52) RSH = 2(Si) jj 2=5XJ) / SL XJ 25

THETA { Surface Mobility Degradation Factor (1=V )

Controls surface mobility reduction due to the vertical electric eld in the channel. THETA is a function of the defect density at the Si-SiO 2 barrier (represented by the scattering constant ) and the oxide thickness 2].

COX / S THETA = 2 TOX

Si

(53)

DELTA { Narrow Width Factor

5.2 Constant SPICE Model Parameters

Controls the increase in threshold due to the narrow channel e ect. DELTA is a function of the slope between the gate oxide and the eld oxide on either side of the channel 24].

DELVTO { Threshold Voltage Shift (V )

The threshold voltage which best ts the drain current of the devices is the linear extrapolated threshold. This voltage is larger than the theoretically calculated threshold, because the band bending in the channel becomes pinned at a value several thermal voltages above the value of PHI typically assumed. At room temperature for a wide range of technologies this di erence is found to be approximately 0:2V 42].

KAPPA { Saturation Field Correlation Factor

Controls channel length modulation and is a measure of what fraction of the voltage di erence between the end of the inversion layer and the drain appears across the pinched-o region of the channel. UO { Low Field Carrier Mobility (cm2=(V s)) This parameter represents the ideal mobility of a carrier in the bulk in a low lateral eld and no vertical eld. Increased doping concentration will reduce the carrier mobility, but this e ect is ignored in this paper. The saturation velocities of electrons and holes should be una ected by device scaling, however when used for curve tting the parameter VMAX can be as much as 3{5 times the true saturation velocity 2]. The actual junction depths scale with technology as shown in table 8, but when LD is set SPICE only uses XJ to calculate the reduction in threshold due to short channel e ects. Since these e ects are already taken into account in the values of VTO given in table 8, XJ is set to zero to turn o the SPICE short channel threshold model.

VMAX { Maximum Carrier Drift Velocity (m=s)

XJ { Di usion Junction Depth (m)

26

The scalable level 3 models created by using these technology projections are given in appendix B. Models for NMOS and PMOS devices are given assuming that the only di erences are the sign of the threshold voltage, the di usion sheet resistance, and the carrier mobility. To use the models simply include them in a SPICE simulation and set the parameter Length to the desired drawn device length. This length should be between approximately 0:5 m and 0:1 m and causes the model parameters to be scaled accordingly. The user must scale the drawn device lengths and widths as needed and use a power supply voltage equal to the parameter Supply. The Supply parameter is scaled down for technologies whose maximum allowable supply voltage is below 5V. Because scaling devices alone leads to unrealistic estimates of delay, a scalable wire model is provided in appendix C. This model assumes aluminum wires which for the 0:5 m technology are assumed to have dimensions of WINT = WSP =0:75 m and TINT = TFOX =0:6 m. These dimensions and the wire resistance and capacitance are scaled by quasi-ideal scaling according to the value of the same Length parameter which sets the scaling of the device models. The user may set the length of the wire in microns through the subcircuit parameter Lwire. The width and spacing of the wire may also be set by the user through the parameters Wint and Wsp. The subcircuit wireC models the wire capacitance but assumes no resistance. The subcircuit wireRC models the wire resistance and capacitance. The default values are the scaled minimum width and spacing for the technology. The results obtained by simulating circuits using these models are not intended to be de nitive for any of these technologies. At any drawn device length there may be considerable variation in the technology parameters. However, this paper has shown that their are limits to the variation of all these parameters and that the values chosen by these models are reasonable for drawn lengths down to 0:1 m. An example of using these models is shown in gure 20 where fanout of 4 inverter delay is plotted as a function of the e ective device length. Above an e ective length of approximately 0:38 m the supply is xed at 5V. Below this length the supply voltage must be scaled down with the length. In both of these ranges the improvement in performance is basically linear as is expected for heavily velocity saturated devices.

5.3 Using the Scaled SPICE Model

6 Conclusion
This paper has used data on previous processor fabrication technologies to show that quasi-constant voltage scaling is the best match for recent MOSFET scaling. However, because this type of device scaling allows elds in the oxide and channel to increase, it can not be continued inde nitely. By examining the speci c electrical limitations of MOSFETs in the form of various leakage currents and reliability concerns, the characteristics of future MOSFET technologies have been projected. Time dependent dielectric breakdown (TDDB), hot carrier e ects (HCE), and the inability to scale the subthreshold slope are shown to be the primary limitations on submicron MOSFETs. TDDB and HCE limit the maximum elds in the oxide and in the channel. These limits force the supply voltage to be scaled down as the device dimensions are reduced. However, because the subthreshold slope can not be scaled, reducing the supply voltage can not be continued inde nitely without severe leakage currents or performance penalties. These factors produce a limit to the scaling of bulk 27

Delay (ps)

175

| | | | | | |

150

125

100

75

50

25

0| 0.05

|
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|
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|
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|
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|
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|
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MOSFETs at drawn lengths of approximately 0:1 m. Interconnect scaling is shown to be following quasi-ideal scaling, in which wire and eld oxide thickness are scaled more slowly than the wire pitch. This produces wires with increasing aspect ratios which are more di cult to fabricate, but reduces the wire resistance causing wire delay per unit length to grow more slowly than ideal scaling. The projections for future MOSFET technologies are used to produce a scalable SPICE level 3 device model. This model allows for circuits to be simulated using reasonable device parameters for technologies with drawn lengths from 0:5 m down to 0:1 m. A scalable wire model is also provided using quasi-ideal scaling to model the resistance and capacitance per unit length of future interconnect technologies.

Leff (um)

Figure 20: Fanout of 4 Inverter Delay

28

Appendix A { SIA Roadmap

1st DRAM Year Feature Size ( m) LEFF ( m) TOX(nm) VDD(V ) VT (V ) XJ (nm) S/D depth (nm) WINT ( m) WSP ( m) TINT ( m) TFOX ( m) Wire Aspect Ratio Wire Res ( = m) Wire Cap (fF= m) 1994 SIA Roadmap Summary 1995 1998 2001 2004 2007 0.35 0.25 0.18 0.13 0.10 0.28 0.18-0.20 0.10-0.14 0.08-0.10 < 0:10 8.0-8.3 6.0-7.3 4.5-5.0 4.0-4.5 3.4 3.3 2.5 1.8 1.5 1.2 0.65 0.60 0.50 0.45 0.40 70-150 50-120 30-80 20-60 15-45 100-200 100-150 70-130 50-100 < 70 0.40 0.30 0.22 0.15 0.11 0.60 0.45 0.33 0.25 0.16 0.60 0.60 0.55 0.45 0.39 1.00 0.84 0.70 0.59 0.57 1.5 2 2.5 3 3.5 0.15 0.19 0.29 0.82 1.34 0.17 0.19 0.21 0.24 0.27

Appendix B { Scalable SPICE Device Models

* To use model simply set Length parameter to desired drawn device length .param BaseLength = 0.52u .param s = 'BaseLength/Length' .param .param .param .param .param .param Slen Stox Svdd Ssub Svto Svtdibl = = = = = = s 'pwr(s, 'pwr(s, 'pwr(s, 'pwr(s, 'pwr(s,

0.76)' 0.79)' 1.16)' 0.40)' 0.47)'

29

.param Seta = 'Svdd*Stox/(Svtdibl*pwr(Slen,3))' .param Supply = 'min(5, 5/Svdd)' .MODEL TN NMOS LEVEL=3 * * Parameters which can be scaled directly + TOX = '10n/Stox' * Gate oxide thickness + NSUB = '4.04e16*Ssub' * Channel doping + VTO = '0.966/Svto' * Threshold voltage at Vds=0 * * Parameters which are functions of scaled parameters + CJ = '1.88e-4*sqrt(Ssub)' * Bottom Junction Capacitance + CJGATE = '1.15e-10*sqrt(Ssub)/Slen' * Gate-edge Sidewall Capacitance + CJSW = '3.65e-11*sqrt(Ssub)/Slen' * Sidewall Junction Capacitance + ETA = '8.23e-3*Seta' * DIBL Factor + HDIF = '0.65u/Slen' * Heavy Diffusion Length + LD = '0.065u/Slen' * Lateral Dopant Diffusion + RS = '1.03k*Slen' * Lightly Doped Sheet Resistance + RSH = '1.77*Slen' * Heavily Doped Sheet Resistance + THETA = '0.12*Stox' * Surface Mobility Degradation * * Parameters which are independent of scaling + ACM = 3 * Source/drain Diffusion area model + DELTA = 0.1 * Narrow Width Factor + DELVTO = 0.2 * Threshold Voltage Shift + KAPPA = 0.2 * Saturation Field Correlation Factor + U0 = 260 * Low Field Carrier mobility + VMAX = 2e5 * Maximum Carrier Drift Velocity + XJ = 0 * Junction Depth (zero turns off SPICE SCE)

.MODEL TP PMOS LEVEL=3 * * Parameters which can be scaled directly + TOX = '10n/Stox' * Gate oxide thickness + NSUB = '4.04e16*Ssub' * Channel doping + VTO = '-0.966/Svto' * Threshold voltage at Vds=0 * * Parameters which are functions of scaled parameters + CJ = '1.88e-4*sqrt(Ssub)' * Bottom Junction Capacitance + CJGATE = '1.15e-10*sqrt(Ssub)/Slen' * Gate-edge Sidewall Capacitance + CJSW = '3.65e-11*sqrt(Ssub)/Slen' * Sidewall Junction Capacitance + ETA = '8.23e-3*Seta' * DIBL Factor

30

+ + + + + * * + + + + + + +

HDIF LD RS RSH THETA

= = = = =

'0.65u/Slen' '0.065u/Slen' '2.06k*Slen' '1.80*Slen' '0.12*Stox'

* * * * *

Heavy Diffusion Length Lateral Dopant Diffusion Lightly Doped Sheet Resistance Heavily Doped Sheet Resistance Surface Mobility Degradation

Parameters which are independent of scaling ACM = 3 * Source/drain Diffusion area model DELTA = 0.1 * Narrow Width Factor DELVTO = -0.2 * Threshold Voltage Shift KAPPA = 0.2 * Saturation Field Correlation Factor U0 = 80 * Low Field Carrier mobility VMAX = 2e5 * Maximum Carrier Drift Velocity XJ = 0 * Junction Depth (zero turns off SPICE SCE)

Appendix C { Scalable SPICE Wire Models

* To use model simply set Length parameter to desired drawn device length .param BaseDeviceLength = 0.51u .param swire = 'BaseDeviceLength/Length' * Quasi-Ideal scaling .param SWint = Swire .param SWsp = Swire .param STint = 'sqrt(Swire)' .param STfox = 'sqrt(Swire)' .param .param .param .param BaseWint BaseWsp BaseTint BaseTfox = = = = 0.75 0.75 0.60 0.60 * * * * Base Base Base Base tech tech tech tech minimum wire width (um) minimum wire space (um) wire thickness (um) field oxide thickness (um)

.param Tint = 'BaseTint/STint' .param Tfox = 'BaseTfox/STfox' .param Trefractory = 0.05 .param .param .param .param rhoAl = 0.03 rhoTiN = 0.40 EO = '8.854e-18' Eox = '3.9*EO'

* Scaled wire thickness (um) * Scaled field oxide thickness (um)

* Constant refractory metal thickness (um) * * * * Resistivity of Al wires (Ohm*um) Resistivity of TiN refractory metal (Ohm*um) Permittivity of free space (F/um) Permittivity of SiO2 (F/um)

31

.subckt + Lwire + Wint + Wsp

wireC in out = '1500/Swire' = 'BaseWint/SWint' = 'BaseWsp/SWsp'

* Default length 1500um for base tech * Default wire width is minimum * Default wire spacing is minimum

.param CapSub = 'Eox*(1.15*Wint/Tfox + 2.8)' .param CapFringe = 'Eox*(0.03*Wint/Tfox + 0.76)*pwr(Wsp/Tfox,-1.34)' .param Cap = 'Lwire*(CapSub + 2*CapFringe)' R1 in out 0.001 C1 out gnd 'Cap' .ends wireC .subckt + Lwire + Wint + Wsp wireRC in out = '1500/Swire' = 'BaseWint/SWint' = 'BaseWsp/SWsp'

* Default length 1500um for base tech * Default wire width is minimum * Default wire spacing is minimum

.param ResAl = 'rhoAl/((Tint-2*Trefractory)*Wint)' .param ResTiN = 'rhoTiN/(2*Trefractory*Wint)' .param Res = 'Lwire/(1/ResAl + 1/ResTiN)' .param CapSub = 'Eox*(1.15*Wint/Tfox + 2.8)' .param CapFringe = 'Eox*(0.03*Wint/Tfox + 0.76)*pwr(Wsp/Tfox,-1.34)' .param Cap = 'Lwire*(CapSub + 2*CapFringe)' R1 in A 'Res/3' R2 A B 'Res/3' R3 B out 'Res/3' C1 C2 C3 C4 in A B out gnd gnd gnd gnd 'Cap/6' 'Cap/3' 'Cap/3' 'Cap/6'

.ends wireRC

32

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