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Euler Path: Traverses Each Branch of The Graph Exactly Once!
Euler Path: Traverses Each Branch of The Graph Exactly Once!
R. W. Knepper
SC571, page 5-17
UNIT III
Carry_out = AB + AC + BC
R. W. Knepper
SC571, page 5-19c
CMOS - Full Adder Circuit
CMOS - Full Adder Circuit
This alternate representation of the sum function
allows the full adder to be implemented in complex
CMOS with 28 transistors, as shown below.
Carry_out internal node is used as an input to the
adder complex CMOS gate
CMOS Full Adder Layout (Complex Logic)
R. W. Knepper
SC571, page 5-19d
CMOS Full Adder Layout (Complex Logic)
R. W. Knepper
SC571, page 5-19d
Multiplexers
2:1 multiplexer chooses between two
inputs
S
S D1 D0 Y
0 X 0 D0 0
0 X 1 Y
D1 1
1 0 X
1 1 X
Multiplexers
2:1 multiplexer chooses between two
inputs
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
Gate-Level Mux Design
Y SD1 SD0 (too many transistors)
How many transistors are needed?
Gate-Level Mux Design
Y SD1 SD0 (too many transistors)
How many transistors are needed? 20
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate Mux
Nonrestoring mux uses two transmission
gates
Transmission Gate Mux
Nonrestoring mux uses two transmission
gates
Only 4 transistors
S
D0
S Y
D1
S
Inverting Mux
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two
selects
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two
selects
Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
Or four tristates
D0
S0 S1
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
D3
SR Latch Using NOR Gates
Characteristics Table of SR Latch
CMOS SR latch using NOR Gates
SR Latch Using NAND Gates
CMOS SR latch using NAND Gates
Clocked RS Flip-Flop
CMOS-Clocked RS Flip-Flop
JK Flip-flop
CMOS JK-Flip-Flop
D-Latch
CMOS implementation of the D-latch (version 1)
CMOS implementation of the D-latch (version 2)
ROM
Read only memories are used to store
constants, control information and program
instructions in digital systems. They may also
be thought of as components that provide a
fixed, specified binary output for every binary
input.
ROM
The read only memory can also be seen as a
simple combinational Boolean network, which
produces a specified output value for each input
combination, i.e. for each address. Thus storing
binary information at a particular address
location can be achieved by the presence or
absence of a data path from the selected row
(word line) to the selected column (bit line),
which is equivalent to the presence or absence of
a device at that particular location.
ROM
The two different types of implementations of
ROM array are:
NOR-based ROM array
NAND-based ROM array
NOR based ROM Array
There are two different ways to implement
MOS ROM arrays. Consider the first 4-bit X 4-
bit memory array as shown in Figure. Here,
each column consists of a pseudon MOS NOR
gate driven by some of the row signals, i.e.,
the word line.
NOR based ROM Array
NOR based ROM Array
Only one word line is activated at a time by raising voltage to
VDD, while all other rows are held at a low votlage level.