A Power-Constrained MPU Roadmap for

International Technology Roadmap for Semiconductors

Kwangok Jeong and Andrew B. Kahng

UCSD VLSI CAD Laboratory
abk@cs.ucsd.edu

CSE and ECE Department

University of California, San Diego
Needs for MPU Roadmap
• What is the limit of future SoC designs?
• MPU uses highest frequency / power / integration level of a technology
 MPU is a reference of leading edge SoC designs
• For a good MPU roadmap,
• How would you approach the task of roadmapping MPU?
• On what technology parameters should the MPU roadmap depend?
• What constraints cause fundamental shifts in the MPU roadmap?

• A consistent and holistic modeling approach for MPU roadmap

to reflect recent technology changes and to tradeoff MPU
design constraints
• Historical MPU design constraints
• Moore’s Law: #TrN = 2  (#TrN-1)
• Constant die area: 310mm2 ((2X #Tr)  (0.5X Tr area) = 1)
• Power: 130W ~ 150W
• Performance: improved with multicore architecture

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (2/11)

Technology Scaling Changes for ITRS 2009
• New scaling trends for M1 half pitch and gate length
• Cell area follows M1 half pitch
• Electrical parameter follows gate length
M1 ½ Pitch 2 year delayed, but scaling becomes more aggressive
60 0.7x / 3year  0.7x / 2year (~2013), 0.7x / 3year (2014~)
50
40
WAS Decreases dimension
Smaller area
(nm)

30 IS
20 Decreases Pdyn and Pleak
10
0
Increases density
2009 2012 2015 2018 2021 2024 Increases Pdyn and Pleak
Physical Lgate 1 year delayed
35
30 WAS
25
IS
Electrical Parameters (Ioff, Cunit, etc.)
(nm)

20
15 Increases gate capacitance
10
5
Decreases Ioff
0
2009 2012 2015 2018 2021 2024
Increases Pdyn but decreases Pleak

• Smaller area is expected, but what about power?

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (3/11)
Parameterized MPU Model
Metal1 (M1) Pitch
M1 Half-Pitch
(F)
Unit Cell Layout
Unit logic cell width (Wlogic ) M1 half-pitch (F)
Unit logic cell height (Hlogic) A-Factor = M1 pitch / 2
Unit SRAM bitcell width (WSRAM) (Alogic , ASRAM)
Unit SRAM bitcell height (HSRAM)
Unit-Cell Area Design Rules
#Components
(Ulogic , USRAM) Metal2 routing pitch (pM2)
#Tr. per logic cell (Ntr,nand2)
#Tr. per SRAM bitcell (Ntr,bitcell) Poly-to-poly pitch (ppoly)
#Logic gates per core (Ngates) Transistor Density
#Bitcells per core (Nbits) (Dlogic , DSRAM) Design Overhead
#Cores per die (Ncore) Logic layout overhead (Ologic)
SRAM layout overhead (OSRAM)
Technology (PIDS) Capacitance Density
Gate length (Lg) (Dcap,logic , Dcap,SRAM , Dcap,int)
Gate width (Wg) Technology (Interconnect)
Gate capacitance (Cg) Interconnect capacitance (Cint)
Power Density Interconnect density (Dl,max)
Unit-width leakage (Ioff)
(Ddynamic , Dstatic)
Low Power Tech. Operating Condition
Switching ratio () MPU Power Voltage (V)
Low-Vth cell ratio () (P) Frequency (f)

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (4/11)

Updated A-Factors: M1 HP (F) based Model
• Logic: • M1SRAM:
Half-Pitch
(F)
• A-factor = 175 • A-factor = 60
M2 pitch
A-Factor
(PM2  1.25PM1)
(Alogic , ASRAM)

NWell
Active
Unit-Cell Area
(Ulogic , USRAM)
Poly
Contact
M1 Transistor Density
M1 pitch (PM1 Contacted-poly pitch
(Dlogic , D) SRAM)
(PPoly  1.5PM1)
Contacted-poly pitch
(PPoly  1.5PM1) Capacitance Density
(Dcap,logic , Dcap,SRAM , Dcap,int)
NAND2 Area SRAM Bitcell Area
= 3 PPoly  8 PM2 PPoly  5 PM1
= 2 Density
Power
 (3 1.5 PM1)  (8  1.25 PM1) (D= 3 P, D
dynamic M1 ) 5 PM1= 15
static

= 45 (PM1)2 (PM1)2
= 180 F2  175 F2 MPU (2 F)2 = 60 F2
= 15Power
(P)

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (5/11)

Transistor Density Model
(U) Area of unit cells M1 Half-Pitch
(F)
• Logic: U logic  AlogicF 2
• SRAM: U SRAM  ASRAM F 2 A-Factor
(Alogic , ASRAM)
Unit area #gates per core
Overhead #cores Unit-Cell Area
(S) Area of MPU (Ulogic , USRAM)

• Logic: Slogic  OlogicU logicN core N gate

Transistor Density
• SRAM: S SRAM  OSRAMU SRAM N core Nbits (Dlogic , DSRAM)

#bits per core Capacitance Density

(D) Density of MPU (#Tr. / Area) (Dcap,logic , Dcap,SRAM , Dcap,int)

• Logic: D tr,logic  N tr,logic / Slogic Power Density

• SRAM: D tr,SRAM  N tr,bitcell / SSRAM (Ddynamic , Dstatic)

MPU Power
(P)

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (6/11)

Power Density Model
• Capacitance density M1 Half-Pitch

Dcap  Dcap,tr  Dcap,int  Dtr C gWg   1 / 3Dl ,maxCint

(F)

A-Factor
• Dynamic
Cg: gate cap.power
per unitdensity
width from PIDS* (Alogic , ASRAM)
Cint: unit length interconnect capacitance from INT**
• Active capacitance
W g: average
density Dcap,logic  Dcap
width of a transistor (=5F) Unit-Cell Area
Dl,max: maximum interconnect density (/cm2) from INT**, (Ulogic , USRAM)
• Dynamic power
assuming density
every third track is occupied
 
f    1   1   
1
Ddynamic  Dcap,logicVHP
2 Transistor Density
 3  (Dlogic , DSRAM)

• Static power density

: switching ratio, assumed as 15% in 2007 Capacitance Density

 
: ratio of high performance (HP) transistors,
 
(Dcap,logic , Dcap,SRAM , Dcap,int)

Dstatic,logic  part
of logic .5Duses
0assumed HP I off , HP  1   I off ,LSTP
transistors
VHP10%
tr ,logicas
: ratio of SRAM dynamic power to logic Power Density
Bitcell array (1/OSRAM) uses LSTP transistors
Dstatic,logic  0.dynamic
5Dtr ,logicVHPpower (Ddynamic , Dstatic)
 of peripheral part uses HP transistors
(1- ) of 1 
I  1   I off , LSTP  
peripheral
OSRAM part uses LSTP transistors 1
 off , HP I off , LSTP  MPU Power
 OSRAM OSRAM  (P)
*PIDS: Process Integration, Devices and Structure
** INT: Interconnect
UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (7/11)
New MPU Integration Scaling and Chip Size
• Fast M1 half-pitch • Reduced A-factors
 Increases density • Logic A-factor: ~320  175
• Number of cores: 2x / 2year • SRAM A-factor: ~100  60
(~2013), 2x / 3year (2014~)
• Number of transistors per core:
 Reduced chip size
2x / 2year (~2013), 2x / 3year • 310mm2  260mm2
(2014~) • Logic area
= #cores  #Logic Tr.  AF2
= ~100mm2
Billion Transistors

120
• SRAM area
100
Was Is = #SRAM bits  9  6  AF2
80
= ~83mm2
60

40
• Integration overhead
20
= 30% of total chip size
0 = ~77mm2
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024

* Intel Core-i7: 263mm2

* AMD Opteron (Shanghai): 258mm2

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (8/11)

Intrinsic Frequency Scaling
• MPU frequency scaling follows 700
Dynamic Power (W)
transistor intrinsic delay (CV/I) 600
Static Power (W)
500
scaling: 400
• 13% per year 300

• Dynamic power increases due to 200

100
large active capacitance increases
0

2013
2009
2010
2011
2012

2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
• Dynamic power reduction techniques must be developed
• Switching activity ratio scaling factor: N = k N-1
Dynamic Power (W)
700 1.2 700 Dynamic Power (W) 1.2
Active Capacitance Density (nF/mm^2)
600 600 Active Capacitance Density (nF/mm^2) 1
1
500 500
0.8 0.8
400 400
0.6 0.6
300 300
0.4 0.4
200 200

100 k=1 0.2 100 k = 0.95 0.2

0 0 0 0
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (9/11)

Power-Constrained Frequency Scaling
• Intrinsic frequency scaling + activity scaling
 Still exceed 150W in 2015
• To meet market needs (130~150W for a platform),
frequency improvement has to be limited:
• 13% per year  8% per year, total power < 150W
60 Frequency (GHz) with 13% per year increase 400
Frequency (GHz) with 8% per year increase
350
50 Total power (W) for 13% per year frequency scaling
Total power (W) for 8% per year frequency scaling 300
40
250

30 200
Power < 150W
150
20
100
10
8% frequency scaling 50

0 0

2023
2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

2021

2022

2024
UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (10/11)
Conclusion
• We have proposed a consistent, holistic modeling
approach for MPU area/power/frequency
roadmapping. From the model,
• For future high performance MPU, aggressive dynamic
power reduction techniques are strongly required
• Frequency improvements need to be restricted: 8% per year
• Ongoing work
• We track tradeoff every year and make sure we don’t miss
the frequency/#core/power curve tradeoff
• We are considering doing a 2009 blind survey on frequency
from key vendors

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (11/11)

BACKUP
 Outline
• International Technology Roadmap for Semiconductors
• Roadmap for Microprocessor
• Recent Technology Roadmap Changes
• Parameterized MPU Roadmap Models
• Transistor Density Model
• Capacitance Model
• Power Model
• Power-Constrained Frequency Model
• Conclusion

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (13/11)

History of ITRS
National Technology Roadmap for Semiconductor
1991 (NTRS) - Semiconductor Industry Association (SIA)
Micro Tech 2000
Workshop Report
1992 1994 1997

SIA

Europe Japan Korea Taiwan USA

International Technology Roadmap for Semiconductors

(First Version - 1998 Update)

Full Revision
1999 2001 2003 2005 2007 2009
(Odd years)
Update 2000 2002 2004 2006 2008
(Even years) Update Update Update Update Update

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (14/11)

ITRS, System Driver, and MPU
Emerging Modeling & Simulation Test & Test Equipment
Research Materials
Design Metrology
Emerging Process Integration,
Research Devices Devices & Structure

Environment,
Safety & Health System Drivers
ITRS
Yield Enhancement Interconnect
Microprocessor (MPU) requires
- Leading edge process and device
Assembly & Packaging
- Highest Front End Processes
frequency / integration / power

Factory Integration
We develop RF and AMS
a power-constrained Lithography
MPU roadmap
to tradeoff power and performance
UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (15/11)
Capacitance Density Model
• Capacitance density due to transistors M1 Half-Pitch
• Capacitance of a transistor (F)

Ctr  Wg C g A-Factor
(Alogic , ASRAM)
• Cg: gate cap. per unit width from PIDS*
• Wg: average width of a transistor (=5F)
Unit-Cell Area
• Capacitance density of transistors (Ulogic , USRAM)
Dcap,tr  DtrCtr
Transistor Density
(Dlogic , DSRAM)
• Capacitance density due to interconnect
Dcap,int  Dl ,eff Cint Capacitance Density
(Dcap,logic , Dcap,SRAM , Dcap,int)

• Dl,max: maximum interconnect density (/cm2) from INT**,

Power Density
assuming every third track is occupied
(Ddynamic , Dstatic)
• Dl,eff : effective interconnect density,1/3 (Dl,max),
considering routing congestion and power/ground network
MPU Power
• Cint: unit length interconnect capacitance from INT** (P)
*PIDS: Process Integration, Devices and Structure
** INT: Interconnect
UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (16/11)
Power Model – Dynamic Power Density
• Active capacitance density M1 Half-Pitch
Dcap,logic   Dcap,tr  Dcap,int  (F)

• Not all capacitances are working A-Factor

• : switching ratio, assumed as 15% in 2007 (Alogic , ASRAM)

• Dynamic power density for logic area Unit-Cell Area

 
f    1   
1
Ddynamic,logic  Dcap,logicVHP
2 (Ulogic , USRAM)
 3 
• : ratio of high performance (HP) transistors, assumed Transistor Density
(Dlogic , DSRAM)
as 10%
• Non-timing critical parts can have smaller activity (1/3)
Capacitance Density
• Dynamic power density for SRAM area (Dcap,logic , Dcap,SRAM , Dcap,int)

Ddynamic, SRAM   Ddynamic,logic

Power Density
• SRAM can have different (maybe slower) frequency, (Ddynamic , Dstatic)
different operation modes, e.g., disabled, different VDD,
etc.  SRAM dynamic power estimation is hard!
MPU Power
• : ratio of SRAM dynamic power to logic dynamic power (P)

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (17/11)

Power Model – Static Power Density
• Static power density for logic area M1 Half-Pitch

Dstatic,logic  0.5Dtr,logicVHP I off , HP  1   I off , LSTP 

(F)

A-Factor
• : ratio of high performance (HP) transistors, assumed (Alogic , ASRAM)
as 10%
• (1- ): ratio of low standby power (LSTP) transistors Unit-Cell Area
• Ioff,HP and Ioff,LSTP are from PIDS (Ulogic , USRAM)

• Static power density for SRAM area

Transistor Density
Dstatic,logic  0.5Dtr ,logicVHP (Dlogic , DSRAM)

 OSRAM  1 
    
I off , HP  1   I off , LSTP 
1
I off , LSTP  Capacitance Density
(Dcap,logic , Dcap,SRAM , Dcap,int)
 OSRAM OSRAM 
• Bitcell array (1/OSRAM) uses LSTP transistors Power Density
(Ddynamic , Dstatic)
•  of peripheral part uses HP transistors
• (1- ) of peripheral part uses LSTP transistors MPU Power
(P)

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (18/11)