VERILOG HARDARE DESCRIPTION

LANGUAGE

LECTUER-4

DIVYA SHAH
26/02/09
Data flow modeling

DIVYA SHAH
26/02/09
 In data flow model we represent the design in
terms of the data flow between registers and how
a design processes the data.

 In data flow model we do not instantiate any

primitives.

 In Verilog we use continuous assignment

statement to represent the data flow model.

 Delays may be associated with continuous

assignment statement
DIVYA SHAH
26/02/09
Continuous assignment statement

Syntax
assign <delay> <continuous_assign_var> = <list of assignments>;
Eg
assign #10 out=in1 & in2;

 Left hand side of the expression must always be scalar or

vector net or concatenation of scalar and vector net.It cant be scalar or
vector register.

 The operands on the right hand side can be registers or nets or

function calls. Registers and nets can be scalars or vectors.

 Continuous assignment statements are always active.itis evaluated as soon

as one of the RHS operands changes and value is assigned to LHS net.

 Delay values control time between the change in RHS operandand when the
new value is assigned to LHS

DIVYA SHAH
26/02/09
Data Flow model of a 2 TO 1 MUX
circuit
module mux2to1(out, sel, inp1,inp2);
output out;
input sel, inp1, inp2;

assign out = sel ? inp1 : inp2;

endmodule

DIVYA SHAH
26/02/09
 Data Flow model of a 4 TO 1
MUX circuit
module mux_4_to_1(out, i0,i1,i2,i3,s1,s0);
output out;
input i0,i1,i2,i3,s0,s1;
assign out = (~s1 & ~s2 & i0) |
(~s1 & s0 & i1 ) |
(s1 & ~s0 & i2 ) |
(s1 & s2 & i3 ) ;
endmodule.
DIVYA SHAH
26/02/09
 LEVEL SENSITIVE LATCH
module level_sensitive_latch (D, Q, En);
input D, En;
output Q;
assign Q = en ? D : Q;
endmodule
//Using “assign” to describe sequential
logic

DIVYA SHAH
26/02/09
 Data Flow model of a full adder
circuit

module fadd(in1, in2, cin, sum,cout);

input in1,in2, cin;
output sum, cout;
assign {cout,sum} = in1 + in2 + cin ;
endmodule

DIVYA SHAH
26/02/09
 REDUCTION OPERATOR
• IT TAKES ONLY ONE OPERAND

• IT PERFORM A BITWISE OPERATION ON A SINGLE VECTOR

OPERAND AND YIELD A 1-BIT RESULT

• IT WORKS BIT BY BIT FROM RIGHT TO LEFT

• Eg
// x=4’b1010
& x// equivalent to 1 & 0 & 1 & 0.Results in1’b0
^ x// equivalent to 1 ^ 0 ^ 1 ^ 0.Results in1’b0
//a reduction xor and xnor can be used for even and odd //parity
generation of a vector

DIVYA SHAH
26/02/09
 Some Valid Statements

• assign outp = (p == 4’b1111);

• if (load && (select == 2’b01)) …….
• assign a = b >> 1;
• assign a = b << 3;
• assign f = {a, b};
• assign f = {a, 3’b101, b};
• assign f = {x[2], y[0], a};
• assign f = { 4{a} }; // replicate four times
• assign f = {2’b10, 3{2’b01}, x};

DIVYA SHAH
26/02/09
 8:1 MUX
module generate_mux (data, select, out);
input [0:7] data;
input [0:2] select;
output out;
assign out = data [select];
endmodule
//Non-constant index in expression on RHS
// generates a MUX

DIVYA SHAH
26/02/09
 DECODER
module generate_decoder (out, in, select);
input in;
input [0:1] select;
output [0:3] out;
assign out [select] = in;
endmodule
//Non-constant index in expression on LHS
//generates a decoder

DIVYA SHAH
26/02/09