FPGA Based System Design

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Course Objectives
1. To know how to design and develop complex digital
systems onto the reconfigurable devices such as Field
Programmable Gate Arrays (FPGA).
2. To enable the student to have command on
a) Verilog HDL to model a digital circuit.
a) Combinational
b) Sequential
c) FSM
d) FSMD
b) Understanding of Internal Architecture of FPGA.
c) FPGA Design flow to port the Verilog HDL on FPGA

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Course Material
1. Course Books
a) FPGA Prototyping by Verilog Examples by Pong. P . Cho.
b) FPGA Based System Design by Wayne Wolf

2. Reference Books
a) Verilog HDL: A Guide to Digital Design and Synthesis by
Samir Palnitkar.
b) Advanced Digital Design with the Verilog HDL by Michael D.
Ciletti

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Quizzes & Assignments

1. Quizzes and Assignments
a) 4 Quizzes (unannounced)
b) 3 Assignments (One Complex Engineering Problem, 2 Regular
assignments)

Course Title – FPGA Based System Design

Introduction
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Outline
• Why VLSI
• Moore’s Law
• Why FPGA
• FPGA System Design Process

Course Title – FPGA Based System Design

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Outline
• Why VLSI
• Moore’s Law
• Why FPGA
• FPGA System Design Process

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Why VLSI
• Integration improves the design:
– lower parasitics = higher speed;
– lower power;
– physically smaller.
• Integration reduces manufacturing cost-
(almost) no manual assembly.

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VLSI and You

• Microprocessors:
– personal computers;
– microcontrollers.
• DRAM/SRAM/flash.
• Audio/video and other consumer systems.
• Telecommunications.

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VLSI and You

• Types of ASIC
– Programmable ASIC (Processors)
– One can change the application function by
changing S/W.
– Non programmable ASIC (e.g. Graphic
Accelerator)
– Once manufactured one can not change its
function.

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Outline
• Why VLSI
• Moore’s Law
• Why FPGA
• FPGA System Design Process

Course Title – FPGA Based System Design

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Moore’s Law

• Gordon Moore: co-founder of Intel.

• Predicted that number of transistors per
chip would grow exponentially (double
every 18 months).
• Exponential improvement in technology is a
natural trend: steam engines, dynamos,
automobiles.

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Moore’s Law

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Moore’s Law

• Current cost: $2-3 billion.

• Typical fab line occupies about 1 city block,
employs a few hundred people.
• New fabrication processes require 6-8
months turnaround.
• Most profitable period is first 18 months-2
years.

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Outline
• Why VLSI
• Moore’s Law
• Why FPGA ?
• FPGA System Design Process

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Why FPGA ???

Q.1 Can we make prototype of our hardware before sending it

for fabrication ( like Bread Board Testing before PCB
manufacturing) ???

Q.2 What to do if we need less number of specific ICs???

Q.3 Can we update our product without throwing away our

stuffed PCBs if additional processing power is required ???

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Why FPGA ???

• FPGAs are programmable logic devices:
– Logic elements + interconnect.
– Provide multi-level logic.

LE LE

Interconnect
LE LE
network

LE LE

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Why FPGA ???

• FPGAs are manufactured by companies like
Xilinx and Altera.
• They are available in different sizes means
– Different number of Logic elements +
interconnect
• Now we have to see how use of FPGA
answer our Questions.

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Why FPGA ???

Q.1 Can we make prototype of our hardware before sending it
for fabrication ( like Bread Board Testing before PCB
manufacturing) ???
Ans: Why not, take an FPGA development board. Try your
Verilog or VHDL code by programming FPGA and see if it works.

Q.2 What to do if we need less number of specific ICs???

Ans: Take FPGA IC and implement your design on FPGA.
Populate this FPGA on the circuit board.

Q.3 Can we update our product without throwing away our

stuffed PCBs if additional processing power is required ???
Ans: Use a bigger FPGA in the design than actually required. By
updating its program you can add required hardware.
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Outline
• Why VLSI
• Moore’s Law
• Why FPGA ?
• FPGA Based System Design Process

Course Title – FPGA Based System Design

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FPGA Based System Design Process

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Course Title – FPGA Based System Design