CSE2001

Computer Architecture and Organization

K. Santhi
SITE
VIT
 Why Computer Architecture
• To acquire some understanding and
appreciation of computer systems functional
components, their characteristics, their
performance and their Interaction.
• To structure a program so that it runs more
efficiently on a real machine
• To know the basics of computer hardware.
 Introduction
• Definition of computer
• Difference between computer architecture
and organization
• History of computers
• Von Neumann Architecture
• Organization of IAS computer
• Questions
 Computer Definition
• “A computer is a complex system incorporating diverse technologies.
Typically, electronic technology is used for computation, magnetic for
long-term storage, and electromechanical for input and output.”
 Computer Architecture
Refers to those attributes of a system
visible to a programmer
or
Those attributes that have a direct impact
on the logical execution of a program

Ex: Instruction set, number of bits used to

represent various I/O mechanisms,
techniques for addressing memory.
 Computer Organization
• Describes HOW features are implemented

• Refers to the operational units and their

interconnections that realize the architectural
specifications

• Organizations differ between versions of the same

architecture.
A Brief History of Computers
The beginning of computing – Abacus
(3000BC)
Babbage’s Differential Engine (1823)
• ENIAC (Electronic Numerical Integrator and
Computer)
• Designed by Mauchly and Eckert
• University of Pennsylvania
• First general-purpose electronic digital computer
• Response to WW2 need to calculate trajectory
tables for weapons.
• Built 1943-1946 – too late for war effort.

• ENIAC DetailsDecimal (not binary)

• 20 accumulators of 10 digits
• Programmed manually by switches
• 18,000 vacuum tubes
• 30 tons
• 15,000 square feet
• 140 kW power consumption
• 5,000 additions per second

Vacuum Tube
ENIAC (1943-46) Electronic Numeric
Integrator and Calculator
 John Mauchly leaning on the
UNIVersal Automatic Computer
 Dr. Von-Neuman with IAS machine
•Stored Program Concept

•Main memory storing programs

and data

•ALU operating on binary data

•Control unit interpreting

instructions from memory and
executing

•Input and output equipment

operated by control unit

•Princeton Institute for Advanced

Studies (IAS).

•Completed 1952
The IBM 7094, a typical mainframe
computer
2nd Generation: Transistor Based Computers
 Transistors replaced
vacuum tubes
 Smaller
 Cheaper
 Less heat dissipation
 Made from Silicon (Sand)
 Invented 1947 at Bell Labs
 William Shockley et al.
 Commercial Transistor based
computers:
 NCR & RCA produced
small transistor machines First transistor computer – Manchester University 1953.

 IBM 7000
 DEC – 1957 (PDP-1)
 Second Generation (1958-1964)
• 1958 Philco introduces TRANSAC S-2000
– first transistorized commercial machine
• IBM 7070, 7074 (1960), 7072(1961)
• 1959 IBM 7090, 7040 (1961), 7094 (1962)
• 1959 IBM 1401, 1410 (1960), 1440 (1962)
• FORTRAN, ALGOL, and COBOL are first standardized
programming languages
3rd Generation: Integrated Circuits
 A single, self-contained transistor is called a discrete component.
 Transistor based computers – discrete components manufactured
separately, packaged in their
own containers, and soldered
or wired together onto circuit
boards.
 Early 2nd generation
computers contained
about 10,000
transistors – but grew to
hundreds of thousands!!!!
 Integrated circuits
revolutionized electronics.
Silicon Chip – Collection of tiny transistors
 Third Generation (1964-1971)
• April 1964 IBM announces the System/360
– solid logic technology (integrated circuits)
– family of “compatible” computers
• 1964 Control Data delivers the CDC 6600
• nanoseconds
• telecommunications
• BASIC, Beginners All-purpose Symbolic Instruction Code
 Fourth Generation (1971)

• Large scale integrated circuits (MSI, LSI)

• Nanoseconds and picoseconds
• Databases (large)
• Structured languages (Pascal)
• Structured techniques
• Business packages
Generations of Computers
 Vacuum tube - 1946-1957 (One bit  Size of a hand)
 Transistor - 1958-1964 (One bit  Size of a fingernail)

 Small scale integration - 1965 on

Up to 100 devices on a chip
Thousands of bits
 Medium scale integration - to 1971 on the size of a
100-3,000 devices on a chip hand

 Large scale integration - 1971-1977

3,000 - 100,000 devices on a chip
 Very large scale integration - 1978 to date
100,000 - 100,000,000 devices on a chip
Millions of bits
 Ultra large scale integration on the size of a
fingernail.
Over 100,000,000 devices on a chip
 Intel processors
• CPU Year Data Memory MIPS
• 4004 1971 4 1K
• 8008 1972 8 16K
• 8080 1974 8 64K
• 8088 1980 8 1M .33
• 80286 1982 16 1M 3
• 80386 1985 32 4G 11
• 80486 1989 32 4G 41
• Pentium1993 64 4G 111
 The Von Neumann Machine - IAS
• IAS
– By von Neumann at the Princeton Institute for Advanced Studies
• Von Neumann was a consultant on the ENIAC project
– Stored program concept
• The ability to store its instructions in its internal memory and process
them in its arithmetic unit, so that in the course of a computation they
may be not just executed but also modified at electronic speeds
• Included in the proposal for EDVAC in 1945
– Started in 1946 and completed in 1952
– All modern computer systems are called Von Neumann machines
• The same structure and the same functions
– Processor, memory, inputs, and outputs
– Stored program concept, PC, MAR
– 1000 x 40 bit words
• Binary number
• 2 x 20 bit instructions
 Interconnection of Components
• Functional components of the computer needs to be
interconnected

• A group of lines/wires that serves as a connecting

path for several devices is called a Bus

• The collection of paths connecting the various

modules is called the interconnection structure

• Bus that connects the major components are called

System Bus

• Bus is a shared transmission medium

Bus Structures
 Speed Issue
• Different devices have different
transfer/operate speed.

• If the speed of bus is bounded by the slowest

device connected to it, the efficiency will be
very low.

• How to solve this?

• A common approach – use buffers.

The Von Neumann Machine & IAS
 Organization of Von-Neumann Machine
(IAS Computer)
• The task of entering and altering programs for ENIAC was
extremely tedious
• Stored program concept – says that the program is
stored in the computer along with any relevant data
• A stored program computer consists of a processing unit
and an attached memory system.
• The processing unit consists of data-path and control.
The data-path contains registers to hold data and
functional units, such as arithmetic logic units and
shifters, to operate on data.
Structure of Von Neumann Machine
Memory of the IAS
 1000 storage locations called words.
 Each word 40 bits.
 A word may contain:
 A numbers stored as 40 binary digits (bits) – sign bit + 39 bit value
 An instruction-pair. Each instruction:
 An opcode (8 bits)
 An address (12 bits) – designating one of the 1000 words in memory.
 Size of
• AC –40 bits
• MQ –40 bits
• MBR –40 bits
• IBR –20 bits
• IR –8 bits
• MAR –12 bits
• PC – 12 bits
Von Neumann Machine
 MBR: Memory Buffer Register
- contains the word to be stored in
memory or just received from memory. AC MQ

 MAR: Memory Address Register

- specifies the address in memory of
the word to be stored or retrieved.
MBR
 IR: Instruction Register - contains the
8-bit opcode currently being executed.
 IBR: Instruction Buffer Register
- temporary store for RHS instruction
from word in memory. IBR PC

 PC: Program Counter - address of

next instruction-pair to fetch from IR MAR
memory.
 AC: Accumulator & MQ: Multiplier
quotient - holds operands and results
of ALU ops.
k.santhi, SITE
 ACAC= 7
3 MQ
MEMORY
1. LOAD M(X) 500, ADD M(X) 501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
501. 4 LOAD 500
M(X)
MBR
ADD MBR =500
M(X) 43
501
(OtherSTOR
Ins) M(X)

PC 21
MAR 501
500
21
MBR LOAD
STOR
M(X)
M(X)500,
500,
3 ADD
4 (Other
M(X)
Ins)501
IR LOAD
STOR
ADD M(X)M(X)
IBR ADD
(Other
M(X) Ins)
501
AC 7
3 501
IBR
Add M(X) PC
PC←
Mar
MAR ==PC
12
←PC
LOAD M(X) 500, 3
ADD M(X) 501
4
STOR M(X) 500, (Other Ins)
IR MARadd== 501
MAR 12
501
MAR==500
MAR =500
add == 500
add
add =12
IAS Instruction set
IAS Instruction set (continued)

Example of an Instruction-pair.
Load M(100), Add M(101)
 IAS Computer AC MQ

MARPC
MBRM[MAR] Input/output
Arithmetic & Logic Circuits
IBRMBR<20..39> IBRMBR<20..39> Equipments
IRMBR<0..7> IRMBR<0..7>
MARMBR<8..19> MARMBR<8..19> MBR
MBRM[MAR] MBRAC
ACMBR M[MAR}MBR
IRIBR<0..7> IRIBR<0..7>
MARIBR<8..19> IBR PC
MBRM[MAR]
ACAC + MBR Main
PCPC+1 Memory
MARPC IR
MBRM[MAR] MAR

Control
Circuits
 Register transfer operation for addition
operation

1. LOAD M(X) 500, ADD M(X) 501

• Register transfer operations: (PC = 1)
– MAR ← PC
– MBR ← M[MAR]
– IBR ← MBR[20:39]
– IR ← MBR[0:7]
– MAR ← MBR[8:19]
– MBR ← M[MAR]
– AC ← MBR
– IR ← IBR[0:7]
– MAR ← IBR[8:19]
– MBR ← M[MAR]
– AC ← AC + MBR
 Problem
Write an appropriate assembly language code
for the following operation and interpret to
Von Neumann IAS architecture
X=Y*Z
Where Z->40 bit data and Y->40 bit data
Result would be more than 40 bit.
 Solution for X=Y*Z
Assume that data variables ‘Y’ & ‘Z’ available at
memory locations 800 & 801 resly. And X will
be stored 803 onwards.
LOAD MQ, M(801) MQM[801]
MUL M(802) AcMQ * M[802]
STOR M(803) M[803]Ac
LOAD MQ AcMQ
STOR M(804) M[804]Ac
 LOAD MQ, M(801) MQM[801]
MARPC MUL M(802) AcMQ * M[801] 0
MBRM[MAR] STOR M(803) M[803]Ac
LOAD MQ AcMQ
LOAD M(801)
IBRMBR<20..39> STOR M(804) M[804]Ac
IRMBR<0..7>
MUL M(802) 0051
MARMBR<8..19> MARMBR<8..19>
MBRAC 0052
MBRM[MAR]
STOR M(803) 0053
MQMBR M[MAR]MBR
LOAD MQ IRIBR<0..7> 0054
IRIBR<0..7>
ACMQ 0055
MARIBR<8..19>
STOR M(804)
MBRM[MAR] PCPC+1 0056
ACMQ * MBR < 0..39> IBRMBR<20..39>
MQMQ * MBR < 40..79> IRMBR<0..7>
PCPC+1 MARMBR<8..19> 0801
MARPC MBRAC
0802
MBRM[MAR] M[MAR]MBR
0803
IBRMBR<20..39>
IRMBR<0..7> 0804
0805
 Registers
• Memory Hierarchy
– Registers
– Cache memory
– Main memory
– Secondary memory
• At higher levels of hierarchy, memory is faster, smaller and
more expensive.
• Number and function vary between processor designs - one
of the major design decisions
• Top level of memory hierarchy
• Two roles
– User-visible registers
– Control and status registers
 User-Visible Registers
• General Purpose
• Data
• Address
• Condition Codes
 General Purpose Registers
• True general purpose registers – register can contain the
operand for any Opcode
• Restricted – used for specific operations – floating point and
stack operations. (dedicated registers)
• Data registers – used only to hold data and cannot be
employed in the calculation of an operand address –
Accumulator (AC)
• Address registers
– Segment registers – holds the address of the base of the segment.
– Index registers – used for indexed addressing and may be auto-indexed
– Stack pointer – points to the top of the stack (if there is a user-visible
stack addressing, stack is in memory)
 Design Issues
• Specialized registers
– Implicit in the Opcode, Saves bits (small instructions) –
because of less number of specialized registers, Less
flexibility
• General purpose registers
– Increased instruction size, increased flexibility and
programmer options
– Fewer registers result in more memory references
 Control & Status Registers
• Not visible to the user
• May be visible in a control or operating system mode
(supervisory mode)
• Registers essential to instruction execution:
– Program Counter (PC)
– Instruction Register (IR)
– Memory Address Register (MAR) – connects to address bus
– Memory Buffer Register (MBR) – connects to data bus,
feeds other registers
 Program Status Word
• Contains status information
• Condition Codes:
– Sign (of last result)
– Zero (last result)
– Carry (multiword arithmetic)
– Equal (two latest results)
– Overflow
– Interrupts enabled/disabled
– Supervisor/user mode
Example Register Organizations
 Register Files (RF)
• Set of general purpose registers.
• It functions as small RAM and implemented using
fast RAM technology.
• RF needs several access ports for simultaneously
reading from or writing to several different registers.
Hence RF is realized as multiport RAM.
• A standard RAM has just one access port with an
associated address bus and data bus.
 A register file with three access ports -
symbol

Data in C
16
2
Address C Port C

Register File
RF
2 2
Address A Port A Port B Address B

16 16
Data out A Data out B
 A Register File with three access ports – logic diagram
Ex: R3 ← R1 + R2
Data in C Read Address A = 01
16 Read Address B = 10
Write 11 2 Write Address C = 11
4-way 16-bit
address C S demultiplexer

16 16 16 16

16-bit register R3 16-bit register R2 16-bit

0101register R1 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

01 S multiplexer multiplexer S
Read Read
address A 16 16 address B
Data out A
Data out B
 A Register File with three access ports – logic diagram

1011 Ex: R3 ← R1 + R2
Data in C Read Address A = 01
16 Read Address B = 10
2 Write Address C = 11
Write 11 4-way 16-bit
S demultiplexer
address C

16 16 16 16

16-bit register R3 16-bit

0110register R2 16-bit
0101register R1 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

01 S multiplexer multiplexer S 10
Read Read
address A 16 16 address B
Data out A
Data out B
 Quiz
• If the 8 registers are used
– How many bits are needed for read/write address?
– What is the size of the demultiplexer and multiplexer
required?
• If 4 multiplexers are used, how many parallel reads
can be performed?
• If 2 demultiplexers are used, how many parallel
writes can be performed?
• Give an example with 4 parallel reads and 2 parallel
writes.(how many registers are required?)
 References
• http://www.computersciencelab.com/Comp
uterHistory/HistoryPt1.htm
• W. Stallings, Computer organization and
architecture, Prentice-Hall,2000