CHAPTER 2

CMOS TECHNOLOGY
GROUP 2 ECE 5-1
2.1

2.2

2.3

2.4

2.5

2.6
2.1
Silicon IC Technologies

Bipolar Bipolar/MOS MOS

Junction Dielectric PMOS Al

CMOS NMOS
Isolated Isolated gate

Aluminum Aluminum
Silicon gate Silicon gate
gate gate
2.1
 2.1

Two methods of growing single-crystal Silicon

material:
1. CZOCHRALSKI METHOD (1971)
2. FLOAT ZONE METHOD
- produces crystals of high purity and is often
used for power devices

Crystals
- normally grown in either (100) or (111) crystal orientation
- cylindrical and have a diameter of 75-300 mm and length of 1 m
- sliced into wafers of thickness 0.5 – 0.7 mm of size 100 – 150 mm
 2.1

• oxide growth, is a process by which a layer of

silicon dioxide (SiO2 ) is formed in the surface of
the silicon wafer
• 56% - is the oxide thickness (tox ) above the
original surface
• 44% - thickness of the silicon substrate below

Oxide Thickness (tox ) can be grown thru:

a. Dry technique – lower defect densities
b. Wet technique
 2.1
Oxide thickness (tox )
- varies from less than 150Å for gate oxides to
more than 10,000Å for field oxides
- takes place at temperatures ranging 700 to
1100C

Silicon Dioxide
tox
0.44 tox Original Silicon Surface

Silicon substrate
 2.1

• Defined in semiconductor material as the movement of

impurity atoms at the surface of the materials into the
bulk of the material
• Takes place at temperatures in the range of 800-1400 C

Two types of Diffusion Mechanism:

a. Infinite-source Diffusion (Predeposition)
b. Finite-source Diffusion (Drive-in)

• 𝟓 × 𝟏𝟎𝟐𝟎 to 𝟐 × 𝟏𝟎𝟐𝟏 atoms/ cm3 - range for the solid

solubility limit
 2.1

Infinite-source Diffusion Finite-source Diffusion

N0

N(x)

NB

• Junction depth – the distance between the

surface of the semiconductor and the junction
• 0.1m (predeposition) and 10m (drive-in)
- typical junction depths for diffusion
 2.1

• It is the process by which ions of a particular dopant

(impurity) are accelerated by an electric field to a high
velocity and physically lodge within the semiconductor
material
• 0.1 – 0.6m – average depth of penetration depending on
the velocity and angle at which the ions strike the
silicon wafer
• It can be used in place of diffusion since in both cases
the objective is to insert impurities into the
semiconductor material
 2.1

Advantages of Ion Implantation over Thermal Diffusion

1. Accurate control of doping – to within ±5%
2. Suitability of operation at room temperature
3. Possible implantation through thin layer
4. Control over the profile of the implanted impurities
 2.1

• The means by which films of various materials may be

deposited on the silicon wafer
Deposition techniques:
a. Evaporation
- a solid material is placed in a vacuum and heated until
it evaporates
b. Sputtering
- uses positive ions to bombard the cathode, which is
coated with the material to be deposited
- usually done in vacuum
Types: dc, radio frequency (RF), magnetron
 2.1

c. Chemical-vapor deposition (CVD)

- uses a process in which a film is deposited by a
chemical reaction or pyrolytic decomposition in the gas
phase, which occur in the vicinity of the silicon wafer
- used to deposit polysilicon, silicon dioxide (SiO2 ), or
silicon nitride (Si3 N4 )
- usually performed at atmospheric pressure

• Low-Pressure Chemical-vapor Diffusion (LPCVD)

- done at low pressures where diffusivity increases
significantly
 2.1

• The process of removing exposed (unprotected) material

• Mask – protective layer, covers the film except in the
area that is to be etched

2 Properties in Etching
a. Selectivity – characteristic of the etch whereby only the
desired layer is etched with no effect on either the
protective layer (masking layer) or underlying layer.

Desired layer etch rate(A)

SA−B =
Undesired layer etch rate (B)
 2.1

b. Anisotropy – property of the etch to manifest itself in

one direction; that is, a perfectly anisotropic etchant will
etch in one direction only.
Lateral etch rate
A = 1−
Vertical etch rate

2 Types of Etching Techniques

a. Wet etching – uses chemicals to remove the material to
be etched
e.g. Hydrofluoric acid (HF) – use to etch silicon dioxide ;
phosphoric acid (H3 PO4 ) – for silicon nitride ;
nitric acid, acetic acid, HF – for polysilicon ;
potassium hydroxide – for etching silicon ;
phosphoric acid mixture – for removal of metal
 2.1

b. Dry etching / Plasma etching – uses ionized gases that

are rendered chemically active by an RF-generated
plasma
- requires significant characterization to optimize
pressure, gas flow rate, gas mixture, and RF power
- very similar to sputtering
- used for submicron technologies since it achieves
anisotropic profiles (no undercutting)
• Reactive ion etching (RIE) – induces plasma etching
accompanied by ionic bombardment
 2.1

• It refers to the complete process of transferring an

image from a photomask or computer database to a
wafer
• 2 Components:
a. Photoresist – is an organic polymer whose
characteristics can be altered when exposed to UV light
Classified into:
1. Positive photoresist – used to create a mask where
patterns exist (where photomask is opaque to UV light)
2. Negative photoresist – creates a mask where
patterns do not exist (where photomask is transparent to
UV light)
 2.1

PHOTOLITHOGRAPHIC PROCESS
Steps:
1. Apply photoresist to the surface to be patterned.
2. “Soft bake” the wafer to drive off solvents in the
photoresist.
3. Selectively exposed the wafer to UV light, using
positive or negative photoresist, and then developed.
4. “Hard bake” the developed photoresist at a higher
temperature to achieve maximum adhesion of the
remaining photoresist.
5. Remove photoresist with solvents or plasma ashing
that will not harm underlying layers. Repeat process
for each layer of the integrated circuit.
2.1
 2.1

Printing – process of exposing selective areas of a wafer

to light through a photomask

3 Basic Types of Printing:

a. Contact printing – simplest and most accurate method
- uses a glass plate (photomask) a little larger than
the size of the actual wafer with the image of the
desired pattern on the side of the glass that comes in
physical contact with the wafer
- system results in high resolution, high throughput,
and low cost
- introduces impurities and defects, because of the
physical contact
 2.1

b. Proximity printing – in this system, the photomask and

wafer are placed very close to one another but not in
intimate contact
- as the gap between the photomask and the wafer
increases, resolution decreases, thus not useful where
minimum feature size is below 2m

c. Projection printing – separates the wafer from the

photomask by a relatively large distance
Two approaches:
1. Scanning method – passes light through the
photomask, which follows a complex optical path
reflecting off multiple mirrors imaging the wafer with an
arc of illumination optimized for minimum distortion
 2.1

2. Step-and-repeat method – most used today

Applied in two ways:
i. Reduction projection printing – uses a scaled
image, typically 5x, on the photomask. Defects are
reduced by scale amount
ii. Nonreduction projection printing – does not
have the above benefit, thus greater burden for low
defect densities is placed on the manufacture of the
photomask itself
2.1
2.1
2.1
2.1
2.2

PHYSICAL MODEL OF A PN JUNCTION

The impurity concentration changes abruptly from ND donors in the n-type

semiconductor to NA acceptors in the p-type semiconductor. This situation is called
a step junction.
 2.2

b). Impurity concentration (cm-3)

The distance x is measured to the right from the metallurgical junction at x = 0.

When two semiconductor materials are formed in this manner, the free carriers
in each type move across the junction by the principle of diffusion . As these free
carriers cross the junction, they leave behind fixed atoms that have a charge
opposite to the carrier.
 2.2

c). Depletion charge concentration

d). Electric Field

e). Electrostatic Potential

qND represents that when the electrons near the junction of the n-type
material diffuse across the junction they leave fixed donor atoms of opposite
charge (+) near the junction of the n-type material.
 2.2

Depletion Region

- is defined as the region about metallurgical junction which is depleted of

the free carriers.

𝒙𝒅 = 𝒙𝒏 - 𝒙𝒑

Xn – the distance which the donor atoms have (+) charge.

Xp – the distance which the acceptor atoms have (-) charge.
Note that Xp < 0
 2.2

Due to electrical neutrality, the charge on either side of the junction must be
equal.
𝒒𝑵𝑫 𝒙𝒏 = −𝒒𝑵𝑨 𝒙𝑷

q – charge of electron (1.60x10-19 C)

The electric field distribution in 𝒅𝑬

the depletion
𝒙 𝒒𝑵region can be obtained using
the point form of Gauss’s law. =
𝒅𝒙 𝜺𝒔𝒊
 2.2

To obtain the maximum electric field occurs at the junction E0 , integrate

either side of the junction.

𝜺𝟎 𝟎 −𝒒𝑵𝑨 𝒒𝑵𝑨 𝒙𝑷 −𝒒𝑵𝑫 𝒙𝑵

𝑬𝟎 = ‫𝑬𝒅 𝟎׬‬ = ‫𝒊𝒔𝜺 𝒑𝒙׬‬ 𝒅𝑿 = =
𝜺𝒔𝒊 𝜺𝒔𝒊

εsi – dielectric constant of silicon (11.7 ε0 )

ε0 = 8.85 x 10 -14
 2.2

The voltage drop across the depletion region is expressed as :

−𝑬𝟎(𝒙𝒏 − 𝒙𝒑 )
∅𝟎 − 𝒗𝒅 =
𝟐

𝑣𝑑 - applied external voltage

∅0 – barrier potential
 2.2

Using the formulas given, the width of the depletion region in the n-type
and p-type semiconductors can be obtained

𝟏
𝟐𝜺𝒔𝒊 ∅𝟎 − 𝒗𝒅 𝑵𝑨
𝑿𝒏 = 𝟐
𝒒𝑵𝑫 𝑵𝑨 + 𝑵𝑫

𝟏
𝟐𝜺𝒔𝒊 ∅𝟎 − 𝒗𝒅 𝑵𝑫
𝑿𝒑 = 𝟐
𝒒𝑵𝑨 𝑵𝑨 + 𝑵𝑫

𝟏 𝟏
𝟐𝜺𝒔𝒊 𝑵𝑨+𝑵𝑫
𝑿𝒅 = 𝒒𝑵𝑨 𝑵𝑫
𝟐
(∅𝟎 − 𝒗𝒅) 𝟐
 2.2

Depletion charge
𝟏 𝟏
𝟐𝜺𝒔𝒊𝒒𝑵𝑨𝑵𝑫 𝟐
𝑸𝒋 = 𝑨𝒒𝑵𝑨𝑿𝒑 = 𝑨𝒒𝑵𝑫𝑿𝒏 = 𝑨 [ ] (∅𝟎 − 𝒗𝒅) 𝟐
𝑵𝑨+𝑵𝑫

Depletion layer Capacitance

𝒅𝑸 𝜺 𝒒𝑵𝑨𝑵𝑫 / 𝟏 𝑪
𝑪𝒋 = 𝒅𝒗 𝒋 = 𝑨 [𝟐 𝒔𝒊𝑵 ]𝟏 𝟐 = [𝟏− 𝒗 𝒋𝟎/∅
𝒅 𝑨
+𝑵𝑫 (∅𝟎−𝒗𝒅)1/2 𝒅 𝟎
𝒎
 2.2

Impurity concentration profile

for diffused pn junction

Depletion capacitance as a function of

externally applied junction voltage
 2.2

CHARACTERISTICS OF A PN JUNCTION
Maximum reverse bias voltage or Breakdown voltage (BV)

𝜺𝒔𝒊 𝑵𝑨+𝑵𝑫
𝐁𝐕 ≅ [ ] E2max
𝟐𝒒 𝑵𝑨𝑵𝑫

Where for silicon,

Emax = 3x105 V/cm
 2.2

Example :

Find the value of the breakdown voltage given the values NA = 5x1015 /cm3, ND = 10x1020 /cm3

Answer : BV = 58.2 V

Solve

Intro conduction mech

 2.2

Conduction Mechanisms

Avalanche Multiplication

- caused by the high electric fields present in the pn junction.

Zener Breakdown

- is a direct disruption of valence bonds in high electric fields. It does not

require the presence of energetic ionizing carrier.
 2.2

intro .. combination of

Actual Reverse Current

1
𝑖𝑅𝐴 = 𝑀𝑖𝑅 = ( 𝑉𝑅 𝑛 )iR
1− 𝐵𝑉

M – avalanche multiplication factor

n – exponent that adjusts the sharpness of the knee of the curve (explain curve)
 2.2

Minority carrier concentrations for a forward biased PN junction

explain
 2.2

Total current density

𝑫𝒑𝒑𝒏𝟎 𝑫𝒏𝒏𝒑𝟎 𝑽𝑫
J(0) = Jp(0) + Jn(0) = q + 𝒆𝒙𝒑 −𝟏
𝑳𝒑 𝑳𝒏 𝑽

Saturation Current

𝑫𝒑𝒑𝒏𝟎 𝑫𝒏𝒏𝒑𝟎 𝑽𝑫
iD = qA + 𝒆𝒙𝒑 −𝟏
𝑳𝒑 𝑳𝒏 𝑽
 2.2

CALCULATION OF THE SATURATION CURRENT

Calculate the saturation current of a pn junction diode with NA = 5x1015

/cm3, ND = 10x1020 /cm3 , Dn = 20 cm2 /s, Dp = 10 cm2 /s, Ln = 10μm , Lp =
5μm , and A = 1000 μm3

Answer : iD = 1.34 x 10-15 A

Solve hehe
2.4

Capacitors
- required when designing analog integrated circuits.
- used as compensation capacitors in amplifier designs,
gain determining components in charge amplifiers,
bandwidth determining components in gm/C filters,
charge storage devices in switched capacitor filter and
digital-to-analog converters.
 2.4

Desired characteristics of capacitors

• Good matching accuracy
• Low voltage coefficient
• High ratio of desired capacitance to parasitic
capacitance
• High capacitance per unit area
• Low temperature dependence
 2.4

For such analog processes, there are basically three

types of capacitors made available.

First type MOS capacitor

- is formed using one of the available interconnect
layers (metal or silicon) on top of crystalline silicon
separated by a dielectric (silicon dioxide layer).
- the mask-defined implanted region becomes the
bottom plate of the capacitor.
 2.4

- The capacitance achieved using this technique

is inversely proportional to gate oxide thickness.
- This capacitor achieves a high capacitance
per unit area and good matching performance but
has a significant voltage-dependent parasitic
capacitance.

Polysilicon - oxide channel

 2.4
Second type MOS capacitor
- formed by providing an additional polysilicon
layer on top of gate polysilicon (separated by
dielectric). The dielectric is formed by a thin silicon
dioxide layer.
- it is the best of all possible choices for high-
performance capacitors.

Polysilicon - oxide channel

 2.4

Third type MOS Capacitor

- it is constructed by putting an n-well underneath
in n-channel transistor. It is similar to the first type
capacitor except of its bottom plate (n-well) which
has much higher resistivity.
- it is not used in circuits where a low voltage
coefficient is important.
- it offers a very high capacitance per unit area , it
can be matched well and it is available in all CMOS
processes.
 2.4

Accumulation MOS capacitor

 2.4

Approximate Performance Summary of Passive Components

in a 0.8μm CMOS Process
Component Type Range of Values Matching Temperature Voltage
Accuracy Coefficient Coefficient
MOS Capacitor 2.2 – 2.7 Ff/μm2 0.05% 50ppm/℃ 50ppm/V

Poly/poly 0.8 – 1.0 Ff/μm2 0.05% 50ppm/℃ 50ppm/V

capacitor
M1-Poly capacitor 0.021-0.025 Ff/μm2 1.5% - -

M2-M1 capacitor 0.021-0.025 Ff/μm2 1.5% - -

M3-M2 capacitor 0.021-0.025 Ff/μm2 1.5% - -

P+ diffused 80-150 Ω 0.4% 1500ppm/℃ 200ppm/V

resistor
N+ diffused 50-80 Ω 0.4% 1500ppm/℃ 200ppm/V
resistor
Poly resistor 20-40 Ω 0.4% 1500ppm/℃ 100ppm/V

n-well resistor 1-2kΩ - 8000ppm/℃ 10kppm/V

 2.4

Side view illustrations of various ways to implement capacitors

using available interconnect layers. M1, M2 and M3 represent
the first, second, and third metal layers, respectively.

a). Vertical parallel plate structures

 2.4

b. Horizontal parallel plate structures

 2.4

Top plate parasitic

Bottom plate parasitic

Parasitic capacitors can give rise to a significant source of error in analog sampled-
data circuits. Parasitics are very dependent on the layout of the device.

Top plate – smallest parasitic capacitance

Bottom plate – larger parasitic capacitance

These two parasitic capacitances depend on the capacitor size, layout and technology.
 2.4

Resistors
- resistors which are compatible with MOS
technology include diffused, polysilicon, and n-well
(or p-well) resistors.

Diffused Resistor
- it is formed using source/drain diffusion.
- it has a voltage coefficient of resistance in the
100-500 ppm/V range.
 2.4

- the sheet resistance of this resistor in a non

salicide process is usually in the range of 5 -
150Ω/square and 5 – 15Ω/square in salicide process.
 2.4

Polysilicon Resistor
- It is surrounded by thick oxide and has a sheet
resistance in the range of 30-200 Ω/square,
depending on doping levels.
- For polysalicide process, the effective
resistance of polysilicon is about 10 Ω/square.
 2.4

n-well Resistor
- it is made up of strip of n-wells contacted at
both ends with n+ source/drain diffusion.
- it has a resistance 1-10k Ω/square and has a
high value for its voltage coefficient.
- it is very useful when accuracy is not required.
2.5

Includes Limitations
- Latch-up
- Temperature
- Noise
Substrate BJT available from bulk CMOS process
Minority-carrier concentrations for a bipolar junction transistor
In terms of current densities, the collector current density is
Combining both equations and multiplying by the area of the BE
junction A gives the collector current as
Where Is is defined as

Base current is expressed as

Latch-up in integrated circuits may be defined as a high current state
accompanied by a collapsing or low-voltage condition. Upon application
of a radiation transient or certain electrical excitations, the latched or
high current state can be triggered.

Can be initiated by at least three regenative mechanisms:

1. The four-layer, silicon-controlled rectifier (SCR), regenerative
switching action
2. Secondary breakdown
3. Sustaining voltage breakdown
Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS
integrated circuits
Equivalent circuit of the SCR formed from the parasitic bipolar transistors
Regeneration Occurs in three conditions:
1. Loop gain must exceed unity

2. Both of the base-emitter junctions must become forward biased.

3. The circuits connected to the emitter must be capable of sinking and
sourcing a current greater than the holding current of the PNPN device.
Latch-up can also be prevented by keeping the potential of the
source/drain of the p-channel device from being higher than
VDD or the potential of the souce/drain of the n-channel device
from going below VSS
The temperature behavior of passive components is usually expressed in
terms of a fractional temperature coefficient TC, defined as

The temperature dependence of the carrier mobility ɥ 𝑖s given

The temperature dependence of the threshold voltage can be

approximated by the following expression
The diode current is given as
The TCF for the reverse diode current can be expressed as

• The reverse diode current is seen to double approximately every 5

degree Celsius increase as illustrated
CALCULATION OF THE REVERSE DIODE CURRENT
TEMPERATURE DEPENDENCE AND TCF

Assume that the temperature is 300 K (room temperature) and

calculate the reverse diode current change and the TCF.
Answer : TCF = 0.165
The forward biased pn-junction diode current is given by

Differentiating this expression with respect to temperature and assuming

that the diode voltage is a constant (vD = VD) gives
The fractional temperature coefficient for iD is

From the diode current formula, vD can ba get as

Differentiating the vD with respect to temperature gives

Noise – one limitation of CMOS components

Shot Noise is associated with the dc current flow across a pn junction. It
typically has the form
Thermal noise generally has the form

The typical form of the flicker noise is given as

Thank You