Professional Documents
Culture Documents
The Drain (D) and Source (S) connect to the to n-doped regions. These N-doped
regions are connected via an n-channel. This n-channel is connected to the Gate (G) via
a thin insulating layer of SiO2. The n-doped material lies on a p-doped substrate that
may have an additional terminal connection called SS.
Depletion-Type MOSFET Construction
• VGS is set to 0V by the direct
connection from one terminal to the
other.
• VDS is applied across the drain-to-
source terminals.
• The result is an attraction for the
positive potential at the drain by the
free electron of the n-channel and a
current similar to that established
through the channel of the JFET.
• In the figure, VGS has been set at a
negative voltage (-1V)
Depletion-Type MOSFET Construction
• Negative potential at gate will tend to pressure
electron towards the p-type substrate and
attract holes from the p-type substrate.
• Depending on negative bias established by
VGS, a level recombination between
electron and hoes will occur.--- it will
reduce the number of free electron in the n-
channel available for conduction.
• The more negative bias, the higher the rate
of recombination
• ID decrease, negative bias for VGS increase
Basic Operation
A Depletion MOSFET can operate in two modes: Depletion or Enhancement mode.
Depletion-type MOSFET in Depletion Mode
Depletion mode
The characteristics are similar to the JFET.
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS
The formula used to plot the Transfer VGS 2
Curve still applies: ID IDSS (1 )
VP
Depletion-type MOSFET in
Enhancement Mode
Enhancement mode
VGS > 0V, ID increases above IDSS
The formula used to plot the
VGS 2
Transfer Curve still applies: ID IDSS (1 )
VP
(note that VGS is now a positive polarity)
p-Channel Depletion-Type MOSFET
The p-channel Depletion-type MOSFET is similar to the n-channel except
that the voltage polarities and current directions are reversed.
Symbols
Enhancement-Type MOSFET
Construction
The Drain (D) and Source (S) connect to the to n-doped regions.
These n-doped regions are connected via an n-channel. The
Gate (G) connects to the p-doped substrate via a thin insulating
layer of SiO2. There is no channel. The n-doped material lies
on a p-doped substrate that may have an additional terminal
connection called SS.
Enhancement-Type MOSFET Construction
• VGS=0, VDS some value, the absence of an n-channel will result in a current
of effectively 0A
• VDS some positive voltage, VGS=0V, and terminal SS is directly connected
to the source, there are in fact 2 reversed-biased p-n junction between the
n-doped regions and p substrate to oppose any significant flow between
drain and source.
• VDS and VGS have been set at some positive voltage greater than 0V,
establishing the D and G at a positive potential with respect to the source
• The positive potential at the gate will pressure the holes in the p substrate
along the edge of the SiO2 layer to leave the area and enter deeper regions
of the p-substrate
• The result is a depletion region near the SiO2 insulating layer void of holes
Enhancement-Type MOSFET Construction
• The electrons will in the p substrate will be attracted to
the +G and accumulate in the region near the surface of
the SiO2 layer
• The SiO2 layer and its insulating qualities will prevent
the negative carriers from being absorbed at the gate
terminal
• VGS increase, the concentration of electrons near the
SiO2 surface increase until eventually the induced n-
type region can support a measurable flow between D
and S
• The level of VGS that results in the significant increase
in drain current is called the threshold voltage, VT.
• VGS increase beyond the VT level the density of the
carriers in the induced channel will increase and I D also
increase
Enhancement-Type MOSFET Construction
• If VGS constant and increase the level
of VDS, ID will eventually reach a
saturation level as occurred for the
JFET
• Applying Kirchoff’s voltage law to
the terminal voltage of the MOSFET
VDG = VDS- VGS
• If VGS fixed at some value, 8V, VDS
increased from 2 – 5V, the VDG will
drop from -6V to -3V and the gate
will become less and less positive
with respect to the drain
Enhancement-Type MOSFET Construction
The Enhancement-type MOSFET only operates in the enhancement mode.
Protection:
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
• Apply voltage limiting devices between the Gate and Source, such
as back-to-back Zeners to limit any transient voltage.