De 19cse33

DE-19CSE33
Course Name: Digital Electronics
Course Code: 19CSE33
Prepared by Asha Rani Borah, CSE dept., NHCE Page 1

DE-19CSE33
Module 1 -: Analog devices for Digital Electronics

Syllabus: BJT vs FETs, EMOS FET, CMOS, Diode as Clipper and Clamper, Bistable
Multivibrators, IC Multivibrators: Astable and Monostable, Types of Oscillator, Crystal
Oscillator
BJT vs FET
BJT (Bipolar Junction Transistor) FET (Field Effect Transistor)
1. Current controlled device => input current Voltage controlled device => input
IB controls output current IC voltage VGS controls output current ID
2. Bipolar device => Current due to both Unipolar device => Current due to
electrons and holes carriers majority (either electrons and holes)
carriers
3. Output IC changes linearly with change in Output ID changes non- linearly with
input IB change in input VGS
4. Input resistance less than FET Input resistance more than BJT
In range of KΩ In range of MΩ
5. Construction size more than FET Construction size smaller than BJT
6. Poor thermal stability Better thermal stability
7. Highly sensitive to changes in the input Less sensitive to changes in the input
signal signal
8. Effected by radiation Not Effected by radiation
9. Noisy due to carriers crossing two junctions Less noisy since no junction
10. Better gain than FET Less gain
11. Only Two types=> PNP and NPN Many types => MOSFET, CMOS, FET
etc
N-Channel Depletion MOSFET (DE- MOSFET)

Construction:
 It consists of a highly doped P-type substrate
 Two blocks of heavily doped N+ material forming the source and drain.
 An N-channel between the source(S) and drain (D).
 A thin layer of SiO2 dielectric is grown over the entire surface
 SiO2 layer results in an extremely high input impedance.
 The P-substrate may have an additional terminal connection called SS
 Gate not connected to the semiconductor material.

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Symbol (Draw the 3 terminal symbol)
Operation:
 DE-MOSFET operates in two modes: 1. Depletion mode
2. Enhancement mode
1. When VGS =0: Zero Bias
 Electrons of N channel moves towards Drain (+ve) causing current I D to flow between
drain to source.
 As VDS increases the channel width at drain reduces due to depletion of electrons
which cause ID to become constant.
 This is known as pinch off condition
 The voltage known as VP = pinch off voltage and the constant current known as IDSS

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2. When VGS = -ve: Depletion mode

 the gate repels some of the negative charge carriers out of the N-channel to recombine
with holes of P-substrate
 Due to recombination the ID current value reduces.
 As VDS increases the channel width at drain reduces due to depletion of electrons
which cause ID to become constant.
 With increase in negative voltage at the gate, the drain current decreases.
 Since the ID is decreasing, this mode of operation is referred as depletion-mode
3. When VGS = +ve: Enhancement mode

 Gate (+ve) attracts the negative charge (minority) carriers from the P-substrate to the
N-channel, increasing the carriers in N-channel.
 Thus it increases carriers in channel and increases ID drain-current.
 The more positive the gate is made, the more drain current flows.
 Since IDis increasing, this mode of operation is referred as enhancement-mode
Characteristics :
In Depletion MOSFET operation:
 When VGS = 0V, ID = IDSS

 When VGS< 0V, ID< IDSS=> depletion mode
 When VGS > 0V, ID> IDSS=>enhancement mode
The formula used to plot the Transfer Curve, is:
2
 VGS 
ID = IDSS  1 - 
 VP 

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Transfer characteristics Output characteristics
NOTE: P-Channel depletion MOSFET
Operation:
In P-channel DE-MOSFET operation:
 When VGS = 0V, ID = IDSS

 When VGS=+ve, ID< IDSS=> depletion mode
 When VGS = -ve, ID> IDSS=>enhancement mode

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N-channel Enhancement-MOSFET(E-MOSFET)
Construction:
 It consists of a highly doped P-type substrate
 Two blocks of heavily doped N+ material forming the source and drain.
 No channel between the source(S) and drain (D).
 A thin layer of SiO2 dielectric is grown over the entire surface
 SiO2 layer results in an extremely high input impedance.
 The P-substrate may have an additional terminal connection called SS
Operation:
 E-MOSFET works only in enhancement mode

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1. When VGS =0:
 Since no channel between drain and source, ID= 0
2. When VGS =-ve:

 Since no channel between drain and source, ID= 0
3. When VGS =+ve:

 The negative (i.e. minority) charge carriers within the substrate are attracted to the
positive gate since gate is positive and accumulate close to the SiO2 layer.
 As the gate voltage is increased, more and more electrons accumulate under the gate.
 Since these electrons cannot flow across the insulated layer of silicon dioxide to the
gate, so they accumulate at the surface of the substrate just below the gate.
 These accumulated minority charge carriers N -type channel stretching from drain to
source. When this occurs, a channel is induced by forming N-type channel.
 The drain current ID starts flowing.
 The strength of the drain current depends upon the channel resistance i.e. depends
upon the number of charge carriers attracted to the positive gate.
 Thus drain current is controlled by the gate potential.
 Since the conductivity of the channel is enhanced by the positive bias on the gate so
this device is also called the enhancement MOSFET or E- MOSFET.
 The minimum value of gate-to-source voltage VGS that is required to form the channel
is termed the gate-to-source threshold voltage VT.
 VGS < VT, ID = 0 =>E-MOSFET is OFF
 VGS >VT, ID flows =>E-MOSFET is ON

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Parameters:
The IDof E- MOSFET is given as:
ID = k (VGS - VT)2
where VT = threshold voltage or voltage at which the MOSFET turns on.
ID(on)
k=
(VGS(ON) - VT)2
Characteristics:
P-channel E-MOSFET
Operation:
 The working of P-channel Enhancement mode MOSFET is similar to the n-channel
except that the voltage polarities and current directions are reversed.
 When VGS = 0V, ID = 0
 When VGS=+ve, ID=0
 When VGS = -ve, IDincreases =>enhancement mode

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 VGS > VT, ID = 0 =>E-MOSFET is OFF

 VGS <VT, ID flows =>E-MOSFET is ON
CMOS- Complementary MOSFET

 It has complementary pair of P-channel and N-channel E-MOSFET
 Advantages: high input impedance,
low power consumption,
requires very less space compared to transistor
 Used in designing Logic circuits
Construction:
 N-channel induced on the right MOSFET: has P-well with N+ drain and N+ source
and P+ substrate
 P-channel induced on the left MOSFET: has N-well with P+ drain and P+ source and
N+ substrate

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CMOS as Inverter:
1. When Vin = 0, logic LOW
 P-channel VGS = -ve => Q2 ON
 N-channel VGS = 0 => Q1 OFF
 Q2 offers low impedance path for VDD and Q1 offers high impedance.
 So, Vout = VDD => Logic High
2. When Vin = high voltage, logic HIGH
 P-channel VGS = +ve => Q2 OFF
 N-channel VGS = -ve => Q1 ON
 Q1 offers low impedance path and Q2 offers high impedance.
 So, Vout = 0=> Logic Low
Diode as clipper
 Used to clip or remove whole or part input signal

 Examples of wave shaping circuits
 Also known as non linear circuit, slicers, amplitude selectors
 Two types: series and shunt clippers
Series Clipper: (for your reference only, for exam study shunt clippers)
 Positive Series clipper:

 Diode is series with input signal
 During +ve input cycle, D = OFF, so no current in circuit => No output
 During -ve input cycle, D = ON, so current in circuit flowing through resistor,
Output voltage α Input voltage

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 Negative Series clipper:

 Diode is series with input signal
 During +ve input cycle, D = ON, so current in circuit flowing through resistor,
 During -ve input cycle, D = OFF, so no current in circuit => No output
Shunt Clippers:
Positive Clipper with Bias
 Diode parallel to input signal

 During +ve input cycle,
0 <Vin <V => D = OFF, so current in circuit flowing to output,
V <Vin <Vm => D = ON, so current in circuit flowing gnd,
Output = V
 During -ve input cycle, D = OFF, so current in circuit flowing to output,

Negative Clipper with Bias
 Diode parallel to input signal

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 During +ve input cycle, D = OFF, so currnt in circuit flowing to output,

 During -ve input cycle,
0 <Vin < - V => D = OFF, so current in circuit flowing to output,
- V <Vin < -Vm => D = ON, so current in circuit flowing to gnd,
Output = -V
Diode as Clamper
Negative Clamper:
 During +ve input cycle, D = ON, so current flows through the diode giving a path for
C to charge. Capacitor charges to positive peak of Input (Vm). The output across
diode is zero.
 During -ve input cycle,
D = OFF, so no current through diode. So the Input flows to output. Since
input potential has changed, capacitor starts discharging from (Vm).
Output voltage α Input voltage + voltage discharged by capacitor
Vo= - Vm + ( - Vm) = -2 Vm
 During next +ve input cycle, D = ON,
Since RC >>> t of input signal, capacitor will discharge slowly and stay at peak
value for long time.
So, at positive peak of input => output will be 0
At negative peak of input => output is – 2Vm

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Positive Clamper:
 During -ve input cycle, D = ON, so current flows through the diode giving a path for
C to charge. Capacitor charges to negative peak of Input ( -Vm). The output across
diode is zero.
 During +ve input cycle,
D = OFF, so no current through diode. So the Input flows to output. Since
input potential has changed, capacitor starts discharging from (Vm).
Output voltage α Input voltage + voltage discharged by capacitor
Vo = Vm + Vm = 2 Vm
 During next -ve input cycle, D = ON,
Since RC >>> t of input signal, capacitor will discharge slowly and stay at peak
value for long time.
So, at negative peak of input => output will be 0
At positive peak of input => output is 2Vm

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Q. What is Multivibrators? Mention the types of Multivibrators.

Q.Explain the various types of multivibrator. Also mention the applications.
Ans:
A multivibrator is an electronic circuit that switches between two states due to
regenerative feedback. It is used to implement a variety of simple two-state systems such
as oscillators, timers and flip-flops. It is characterized by two amplifying devices cross-
coupled by resistors or capacitors. There are three types of multivibrator circuit depending on
the circuit operation:
 ASTABLE, in which the circuit is not stable in either state —it continually
switches from one state to the other. It does not require an external trigger pulse.
Also known as free running multivibrator.
 MONOSTABLE, in which one of the states is stable, but the other state is quasi
(unstable). A trigger causes the circuit to enter the quasi state. After entering the
quasi state, the circuit will return to the stable state after a set time. Such a circuit is
useful for creating a timing period of fixed duration in response to some external
event. This circuit is also known as a one shot or mono shot.
 BISTABLE, in which the circuit has two stable states. The circuit can be flipped
from one state to the other by an external trigger. Also known as flip-flop.
Q. With a circuit diagram, and waveform explain the working of transistor based
Bistable multivibrator circuits.
ANS:
 Bistable Multivibrators have TWO stable states and maintain a given output state
indefinitely unless an external trigger is applied.
 Switches from one stable state to the other by the application of an external trigger
pulse thus, it requires two external trigger pulses.
 Since has two stable states they are more commonly known as Latches and Flip-
flops for use in sequential type circuits.( it "flips" into one logic state, remains there
and then changes or "flops" back into its first original state)
Construction:
 Has two NPN transistors Q1 and Q2.
 Collector of Q1 coupled to base of Q2 through R1.
 Collector of Q2 coupled to base of Q1 through R2.
Operation:
1. Initial condition:
 When Vcc is applied both transistor starts conducting.
 Since no two transistors have identical characteristics, one transistor will conduct
more as compared to other one.
 Assuming Q2 starts conducting more than Q1, Q2 draws more input current as
compared to Q1.
 The output current of Q2 will be more than Q1, so as I C2 increases IB1decreases.
 Since IB1is coupled to base of Q1, base voltage of Q1 decreases which causes output
of Q1 to decrease further.
 As IC1 decreases, IB2 increases which is coupled to base of Q2.

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 So, base voltage of Q2 increases which causes output of Q2 to increase further.

 This cycle repeats which causes base voltage of Q2 to keep increasing and base
voltage of Q1 to keep decreasing.
 This drives Q1 towards cut off and Q2 towards saturation.
 This is known as regenerative feedback.
 Since Q2 is in saturation, Vout = LOW (Vsat)= Stable state
 Vout will remain LOW till trigger is not applied.
Note: To remember, don’t write in exam:

Q2 better than Q1, IC2> IC1,
IC2 increases => IB1 decreases => IC1 decreases=> IB2 increases => IC2 increases
As cycle continues, IB1 decrease => Q1 => cut off
IB2 Increase => Q2 => saturation
Vout = LOW
2. When negative trigger applied at Q2 base:

 A negative pulse at Q2 base will decrease the voltage at base which will drive Q2 to
conduct towards cut off.
 As IB2 decreases, IC2 decreases which is coupled to base of Q1 by I B1.
 As base voltage of Q1 increases,IC1increases, IB2decreases which is coupled to base of
Q2.
 Again due to regenerative feedback, Q2 will drive to cut off and Q1 will go to
saturation.
 Since Q2 is in cut off, Vout = HIGH= Stable state
 Vout will remain HIGH till next trigger is not applied.

When negative trigger applied at Base 2,
IB2 decreases => IC2 decreases=> IB1 increases => IC1 increases=> IB2 decreases
Vout = HIGH

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3. When negative trigger applied at Q1 base:

 A negative pulse at Q1 base will decrease the voltage at base which will drive Q2 to
conduct towards saturation and Q1 to cut off.
 Again Vout = LOW.

When negative trigger applied at Base 1,
IB1 decreases => IC1 decreases=> IB2 increases => IC2 increases=> IB1 decreases
Vout = LOW
 C1 and C2 capacitors are known as speed up capacitors. Their function is to increase

the speed of the circuit in making transition from one stable state to another stable
state faster.
 The base resistors R3 and R4 of both the transistors are connected to a common source
(-VBB) to ensure one of the transistor remains in cut off region.
Waveform:
Uses:
1. In timing circuits as frequency divider
2. In counting circuits
3. In computer memory circuits
Q. Explain the internal block diagram of 555 timer IC.
Ans:
Pin 1: Grounded Terminal: All the voltages are measured with respect to this terminal.

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Pin 2: Trigger Terminal: This pin is an inverting input to a comparator that is responsible
for transition of flip-flop from set to reset. The output of the timer depends on the amplitude
of the external trigger pulse applied to this pin. When a negative going pulse of amplitude
greater than 1/3 VCC is applied to this pin, the output of the timer high. The output remains
high as long as the trigger terminal is held at a low voltage.
Pin 3: Output Terminal: Output of the timer is available at this pin.
Pin 4: Reset Terminal: To disable or reset the timer a negative pulse is applied to this pin
due to which it is referred to as reset terminal. When this pin is not to be used for reset
purpose, it should be connected to + VCC.
Pin 5: Control Voltage Terminal: The function of this terminal is to control the threshold
and trigger levels. When this pin is not used, it should be connected to ground through a 0.01
μF capacitor to avoid any noise problem.
Pin 6: Threshold Terminal: This is the non-inverting input terminal of comparator 1, which
compares the voltage applied to the terminal with a reference voltage of 2/3 V CC. When the
voltage at this pin is greater than or equal to the threshold voltage 2/3 VCC, the output of the
timer low.
Pin 7: Discharge Terminal: This pin is connected internally to the collector of transistor and
mostly a capacitor is connected between this terminal and ground. It is called discharge
terminal because when transistor saturates, capacitor discharges through the transistor. When
the transistor is cut-off, the capacitor charges at a rate determined by the external resistor and
capacitor.
Pin 8: Supply Terminal: A supply voltage of + 5 V is applied to this terminal with respect
to ground (pin 1).

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Q. Discuss briefly the working operation of Astable multivibrator using IC 555 timer.
Q. With neat figure and relevant wave forms explain the operation of astable
multivibrator using IC 555 timer.
Q. With the aid of circuit pin diagram and waveforms, explain the operation of 555
timer as an ASTABLE multi vibrator to get 50% duty cycle.
Ans:
Working:
 Let output VOUT = high, Q =1, Q = 0
 Since Q=0, the discharging transistor is cut-off and the capacitor C begins charging
toward VCC through resistances RA and RB.
 Because of this, the charging time constant
 tc or THIGH = 0.693 (RA + RB) C
 As capacitor charges towards +2/3 VCC, the threshold voltage(PIN 6) exceeds +2/3
VCC, the comparator 1 has a high output and triggers the flip-flop, so Q = high and Q
= 0.
VOUT =low
 Since Q = high, the discharge transistor saturates and pin 7 grounds so that the
capacitor C discharges through resistance RB.
 The discharging time constant,
td or TL0W = 0.693 RB C
 With the discharging of capacitor, trigger voltage at inverting input of comparator 2
decreases.
 When it drops below 1/3VCC, the output of comparator 2 goes high and this reset the
flip-flop, so Q = low and Q = 1.
VOUT = high.
 Since Q=0, the discharging transistor is cut-off and the capacitor C begins charging.
Thus the cycle repeats.

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Module 2 - Simplification of Boolean Functions:

Syllabus : Review of Boolean algebra, logic gates, canonical
forms, Three Variable K – Maps, Four Variable K – Maps, Quine-
McCluskey minimization technique, Reduced prime implicants
Tables, Map Entered Variables, Introduction to HDL.
Digital Electronics circuits or Logic Circuits are categorized into 2 types:
1. Combinational Logic Circuits: Circuits without memory

2. Sequential Logic Circuits: Circuits with memory
Combinational Logic Circuits

The output of combinational logic circuit depends only on the current inputs.
There are two fundamental approaches in logic design:

 The Sum-of-Products (SOP)
– Solution results in an AND -OR or NAND-NAND network
 The Product-of-Sums (POS) Method
– Solution results in an OR-AND or NOR-NOR network
Boolean Algebra
BASIC LAWS OF BOOLEAN ALGEBRA

1. COMUTATIVE LAW:
A+B=B+AA.B=B.A
2. ASSOCIATIVE LAW:
A + (B + C) = (A + B) + C A(BC) = (AB)C
3. DISTRIBUTIVE LAW:
A(B + C) = AB + AC
4. A + 0 = A
5. A + 1 = 1
6. A . 0 = 0
7. A . 1 = A
8. A + A = A
9. A + A = 1
10.A . A = A
11.A . A = 0
12.A = A
13.A + AB = A
14.A + AB = A + B
15. (A+B)(A+C) = A+BC
DE MORGAN’S THEOREMS
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1. AB = A + B
2. A + B = A . B
Logic gates
AND gate
OR gate
NOT gate
NAND gate
NOR gate
SOP
SUM OF PRODUCTS METHOD
• The fundamental products are also called minterms.

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Sum-of-Products (SOP) Equation

The SOP equation can be represented by an expression that is a sum of minterms, where each
minterm is ANDed with the value of Y for the corresponding valuation of input
variables.Consider the following Truth table:
 Here, we have to locate output 1 in the truth table and write down the minterm.
 For instance, the second output 1 appears for an input A=0, B=1. The corresponding
minterm is A'B.
 The next output 1 appears for A=1, B=0. The corresponding minterm is AB'.
Y = m1 + m2 + m3
= A’ . B + A . B’ + A . B
 Compact form
Y = f(A, B) = Σ m(1, 2, 3)
 Logic circuit: using AND –OR gate
 Using NAND gate

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Example:
Truth table
 Y=A'BC+AB'C+ABC'+ABC
 Y=F(A,B,C)=∑m(3,5,6,7)
POS
PRODUCT OF SUMS METHOD
• Given a truth table, identify the fundamental sums needed for a logic design.
• Then by ANDing these sums, we get the product-of-sums equation corresponding to the
truth table.
• The fundamental sum produces an output 0 for the corresponding input condition.
 In POS, each sum term is called maxterm and is designated by M.

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 Locate each output 0 in the truth table and write down its fundamental sum.
 To get the product-of-sums equation, AND the fundamental sums.
Y= (A+B+C)(A+B'+C')(A'+B'+C)
Y= ∏M (0,3,6)
K-MAP (Karnaugh maps)
 Karnaugh map (K-map) is a visual display of the fundamental products foa a

SOP equation f
 Developed by Maurice Karnaugh, an American Physicist
KMAP METHOD FOR SIMPLIFYING BOOLEAN EQUATIONS

1. Enter a 1 on map for each fundamental product that produces a 1 output in truth
table. Enter 0s elsewhere.
2. Encircle the octets. (Octet is a group of eight 1s. It eliminates three variables and
their complements.)
3. Encircle the quads. (A quad is a group of four 1s that are horizontally or Vertically
adjacent. It eliminates 2 variables and their complements.)
4. Encircle the pairs.(A pair is a group of two 1s that are horizontally or vertically
adjacent. It eliminates one variable and its complement.)
5. If any isolated 1s remain, encircle each.
6. Eliminate any redundant group.

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7. Write boolean equation by ORing the products corresponding to the encircled

group. This gives SOP terms.
Two variable K Map
Cell numbering K map for the given truth table
Y= A
Three variables K MAP
Y= ∑m (2, 6, 7)
BC BC BC BC
BC BC BC BC
A 0 1 3 2
A 0 0 0 11
A 4 5 7 6
A 0 0 11 111
Y = AB + BC
Four Variables K Map

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Y=F(A,B,C,D)=∑m(2,6,7,14)
Y = ABC + BCD + A BCD
DON’T CARE CONDITIONS

• In some logic circuits, certain input conditions never occur; therefore the
corresponding output never appears.
• In such cases, the output level is not defined; it can be either HIGH or LOW. These
output levels are indicated by'X' in the truth tables and are called don't care
conditions

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Y= f (A, B, C, D) = ∑ m (9) + dc ( 10, 11, 12, 13, 14, 15)
Y = AC
POS Simplification

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A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
f(A, B, C, D) = πM(0, 2, 4, 10, 11, 14, 15)
C+D C+D C+D C+D
A+B 0 1 3 2
A+B 4 5 7 6
A+B 12 13 15 14
A+B 8 9 11 10

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Y = (A + B + D) ( A + C + D) ( A + C)
EXAMPLE 1:
Y = f(A, B, C) = Σ m (2, 3, 4, 6) = A’BC’ + A’BC + AB’C’ + ABC’
The simplified expression Y = A’B + AC’
EXAMPLE 2:
Simplify Y = f(A, B, C) =Σ m (1, 2, 3, 5, 6, 7)

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The simplified expression Y= B + C.
EXAMPLE 3:
Simplify Y = Σ m (0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13).
The simplified equation is Y = C’ + A’D’ + B’D’.
EXAMPLE 4:
Simplify Y = Σ m ( 2, 3, 6, 7, 8, 9) + dc (10, 11, 12, 13, 14, 15)

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The simplified equation is Y = A + C
Conversion between SOP and POS
SOP and POS occupy complementary locations in a truth table. One representation
can be obtained by the other by
1. Identifying complementary locations
2. Changing minterm to maxterm or reverse
3. Changing summation by product or reverse
Example:
1. Consider Y = f(A, B, C) = πM(0, 3, 6).

The SOP equivalent is Y= Σm(1, 2, 4, 5, 7).
2. Consider Y = f(A, B, C, D) = Σm(0, 3, 5, 6, 12, 14).

The SOP equivalent is Y= πM (1, 2, 4, 7, 8, 9, 10, 11, 13, 15).
3. Consider Y = f(A, B, C, D) = Σm (0, 3, 6, 9,11,13,15) + dc (2, 10, 14)

The SOP equivalent is Y= πM (1, 4, 5, 7, 8, 12)+ dc (2, 10, 14)
LIMITATIONS OF KMAP
• The map method depends on the user's ability to identify patterns that gives largest
size.
• The map method becomes difficult to adapt for simplification of 5 or more variables .
SIMPLIFICATION BY QUINE Mc-CLUSKEY METHOD
• Quine McCluskey method is a systematic approach for logic simplification that does
not have the limitations of K Map and also can easily be implemented in a digital
computer.
• Quine McCluskey method involves preparation of 2 tables:

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→ one determines prime implicants and

→ other selects essential prince implicants to get minimal expression.
• Prime implicants are expressions with least number of literals that represents all the
terms given in a truth table.
• Prime implicants are examined to get essential prime implicants for a particular
expression that avoids any type of duplication.
PROCEDURE USED FOR DETERMINING ESSENTIAL PRIME IMPLICANTS
• In stage 1 of the process, find out all the terms that gives output 1 from truth table
and put them in different groups depending on how many 1 input variable
combinations have.
For example, first group has no 1 in input combination, second group has only one
1,third two1s,fourth three 1s and fifth four 1s. We also write decimal equivalent of
each combination to their right for convenience.
• In stage 2, try to combine first and second group of stage 1,on a member to
member basis.
• The rule is to see if only one binary digit is differing between two members and
mark that position by '-'. This means corresponding variable is not required to
represent those members.
• In stage 3, combine members of different groups of stage 2 in a similar way. Now it
will have two '-'elements in each combination. This means each combination
requires 2 literals to represent it.
• Repeat stage 4 as stage 3 if required. It will have three '-'elements in each
combination. This means each combination requires 1 literal to represent it.
• Next step is to select essential prime implicants and remove redundancy or
duplication among them. For this, prepare a table, along with the row lists all the
prime implicants and along columns lists all minterms.
• The cross-point of a row and column is ticked if the term is covered by
corresponding prime implicants.

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Y=A'B'+B'C+AB'+AC
Y=A'B'+B'C+AB or Y=A'B'+AC+AB
Example 2:
Simplify the following function:
Y = f(A, B, C, D) = Σ m(0, 1, 2, 3, 10, 11, 12, 13, 14, 15)

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Prime implicants: Y = A’B’ + AB + AC + B’ C
Y = A’B’ + AB + AC
VARIABLE ENTERED MAP

A variable entered map (VEM) is a Karnaugh map in which the size of the map is reduced by
removing one or more of the variables from the specification of the map cell locations.
Instead of having only the 1's and 0's in the cells of the original map, the cells of the VEM
contain functions of the variables which were removed. It allows a smaller map to handle
large number of variables. This is done by writing output in terms of input.
The variable moved from input to output is known as map entered variable.
Steps to follow:
1. Draw the truth table for given numerical.
2. Draw the reduced truth table.
3. Draw the VEM K map.
4. Follow the Map rules given below to find the answer.
Map rules
1. First Map ‘1’s by considering other variables as 0.
2. Convert ‘1’s to don’t cares (‘X’)
3. Consider one variable and other variables as 0
4. Map LIKE entries
5. Use don’t cares in any manner
6. Ensure to repeat 3&4 for all variable entries

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Example 1:
F(A,B,C) = (0,1,2,5)
Step 1: truth table
B’ B
Step 2: reduced
truth table
Step 3: VEM K map

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A’ 1 C’
A C 0
Example 2:
F(A,B,C,D) = M (5, 7, 8, 9, 10, 11, 12, 14)
Step 1: truth table
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
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1 1 1 1 0
Step 2: Reduced truth table
A B C Y
0 0 0 0
0 0 1 0
0 1 0 D
0 1 1 D
1 0 0 1
1 0 1 1
1 1 0 D’
1 1 1 D’
Step 3: K map
Step 4: Simplification

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Y= AB’
D as MEV:
Y= AB’ + A’B D
D’ as MEV:
Y= AB’ + A’B D + AD’

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Module 3: Combinational Logic Circuits

Syllabus: Introduction, Adders, Subtractors, Carry Look Ahead Adder, Parallel
Adder, Magnitude Comparator, Priority Encoders, Decoders, Multiplexers, Read
Only memories (ROM), Programmable Logic Arrays (PLAs), Verilog implementation
of combinational circuits.
Arithmetic Circuits
Half adder:
INPUTS OUTPUTS
A B S CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Sum = A B’ + A’ B = A XOR B Carry = AB
FULL ADDER:

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SUM = A XOR B XOR Cin
Cout = AB + Cin (A XOR B)
Half Subtractor:
Subtraction rules:
1.0-0 = 00 2. 0-1 = 11 3.1-0 = 01 4.1-1 = 00
INPUTS OUTPUTS
A B D Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Difference = A B’ + A’ B = A XOR B Borrow= AB
FULL SUBTRACTOR:
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Difference = A XOR B XOR C Bout = AB + C (A XNOR B)
Parallel Adder
 Parallel Adder is a digital circuit capable of finding the arithmetic sum of two
binary numbers by operating on corresponding pairs of bits in parallel.
 It consists of full adders connected in a chain where the output carry from
each full adder is connected to the carry input of the next higher order full
adder in the chain.
 A n bit parallel adder requires n full adders to perform the operation.
 The given figure is 4 bit parallel adder

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Working of parallel Adder –
1. As shown in the figure, firstly the full adder FA0 adds A0 and B0 along with
the carry C0 to generate the sum S0 (the first bit of the output sum) and the
carry C1 which is connected to the next adder in chain.
2. Next, the full adder FA1 uses this carry bit C1 to add with the input bits A1
and B1 to generate the sum S1(the second bit of the output sum) and the
carry C2 which is again further connected to the next adder in chain and so
on.
3. The process continues till the last full adder.
In case of parallel adders, the binary addition of two numbers is initiated when all
the bits of the augend and the addend must be available at the same time to
perform the computation. In a parallel adder circuit, the carry output of each full
adder stage is connected to the carry input of the next higher-order stage, hence
it is also called as ripple adder.
Parallel Adder/Subtractor
 The addition and subtraction operations can be done using an Adder-
Subtractor circuit. The figure shows the logic diagram of a 4-bit Adder-
Subtractor circuit.
 When M = 0, the output of XOR gate will be Bi ⊕ 0 = Bi.
 If the full adders receive the value of B, and the input carry C0 is 0, the circuit
performs A plus B.
’
 When M = 1, the output of XOR gate will be Bi ⊕ 1 = Bi .
 If the full adders receive the value of B’, and the input carry C 0 is 1, the circuit
performs A plus 1’s complement of B plus 1, which is equal to A minus B.

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Propagation Time
In parallel adder circuits, it is not possible to produce the sum and carry outputs of
any stage until the input carry occurs. So there will be a considerable time delay in
the addition process, which is known as carry propagation delay. In any
combinational circuit, signal must propagate through the gates before the correct
output sum is available in the output terminals.
The propagation time is equal to the propagation delay of the typical gate times the
number of gate levels in the circuit. For example, if each full adder stage has a
propagation delay of 20n seconds, then S4 will reach its final correct value after 80n
(20 × 4) seconds.
The following are the methods to get the high speed in the parallel adder to produce
the binary addition.
1. By employing faster gates with reduced delays, we can reduce the
propagation delay. But there will be a capability limit for every physical logic
gate.
2. Another way is to increase the circuit complexity in order to reduce the carry
delay time. There are several methods available to speeding up the parallel
adder, one commonly used method employs the principle of look ahead-carry
addition by eliminating inter stage carry logic.
Carry Lookahead Adder

A carry-Lookahead adder is a fast parallel adder as it reduces the propagation delay
by more complex hardware, hence it is costlier.
This method makes use of logic gates so as to look at the lower order bits of the
augend and addend to see whether a higher order carry is to be generated or not.
If we define two variables as carry generate Gi and carry propagate

Pi then,

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Pi = Ai ⊕ Bi
Gi = Ai Bi
The sum output and carry output can be expressed as
Si = Pi ⊕ Ci
C i +1 = Gi + Pi Ci
Where Gi is a carry generate which produces the carry
when both Ai, Bi are one regardless of the input carry. Pi
is a carry propagate and it is associate with the
propagation of carry from Ci to Ci +1.
The carry output Boolean function of each stage in a 4

stage carry-Lookahead adder can be expressed as
C1 = G0 + P0 Cin
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 Cin
C3 = G2 + P2 C2
= G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 Cin
C4 = G3 + P3 C3
= G3 + P3 G2+ P3 P2 G1 + P3 P2 P1 G0 + P3 P2
P1 P0 Cin
From the above Boolean equations we can observe that C4 does not have to wait for
C3 and C2 to propagate but actually C4 is propagated at the same time as C3 and
C2. Since the Boolean expression for each carry output is the sum of products so
these can be implemented with one level of AND gates followed by an OR gate.
The implementation of three Boolean functions for each carry output (C2, C3 and
C4) for a carry-Lookahead carry generator shown in below figure .

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Therefore, a 4 bit parallel adder can be implemented with the carry-Lookahead

scheme to increase the speed of binary addition as shown in below figure. In this,
two Ex-OR gates are required by each sum output. The first Ex-OR gate generates
Pi variable output and the AND gate generates Gi variable.
Hence, in two gates levels all these P’s and G’s are generated. The carry-Lookahead
generators allows all these P and G signals to propagate after they settle into their
steady state values and produces the output carriers at a delay of two levels of
gates. Therefore, the sum outputs S2 to S4 have equal propagation delay times.
DATA PROCESSING CIRCUITS

Data-processing circuits are logic circuits that process binary data. Such circuits may
be multiplexers, demultiplexer, encoder, decoder.
Multiplexer
 Multiplex means many into one.
 In digital computer networks, multiplexing is a method by which multiple
digital data streams are combined into one signal over a shared medium.
 A digital circuit that performs the multiplexing of digital signals is called a
multiplexer (or MUX in short).
 Multiplexer is a combinational logic circuit that can select one of many inputs.
 Multiplexer is also called a data selector.

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General multiplexer block diagram
4:1 MUX
Selection Lines Output

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Y = S1’ S0’D0 + S1’ S0 D1 + S1 S0’D2 + S1 S0 D

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Multiplexer Logic
 Multiplexer can be used to realize a given Boolean equation. Multiplexer is
called universal logic circuit because a 2n-to-1 multiplexer can be used to
design solution for any n-variable truth table.
Y = ∑ m ( 0, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15)

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8:1
MUX
Multiplexer Trees
Design a 4-to-1 multiplexer 2 to 1 multiplexer.
Solve: Design a 32-to-1 multiplexer using two 16:1 and one 2:1 MUX.
Decoders: n: 2n
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A decoder is a circuit that changes a code into a set of signals. The basic function of
a decoder is to detect the presence of a specified combination of bits on its inputs
and to indicate that presence by a specified output level. A decoder has n input lines
o handles n bits and from one to 2 noutput lines to indicate the presence of one or
more n – bit combinations..
Design 2 to 4 Decoder using basic gates
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0.
The block diagram of 2 to 4 decoder is shown in the following figure.

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Design 4:16 using 3:8 decoder
Implement the given Boolean expression using Decoder:

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TO SOLVE:
1. Design 5:32 decoder using 4:16 decoder.
2. Design 3:8 decoder using basic gates.
3. Implement Full adder using 3:8 DECODER
4. Implement Full subtractor using 3:8 decoder.
Encoder: 2n : n
Encoder perform the function opposite to that of decoders. Encoders have up to

2n inputs and n outputs, and generate an n-bit word for each of the inputs.
Design 4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.
The block diagram of 4 to 2 Encoder is shown in the following figure.
At any time, only one of these 4 inputs can be ‘1’ in order to get the respective
binary code at the output. The Truth table of 4 to 2 encoder is shown below.

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Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Priority Encoder

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A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.
Here, the input, Y3 has the highest priority, whereas the input, Y0 has the lowest
priority. In this case, even if more than one input is ‘1’ at the same time, the output
will be the (binary) code corresponding to the input, which is having higher priority.
Consider one more output, V in order to know, whether the code available at
outputs is valid or not.
 If at least one input of the encoder is ‘1’, then the code available at outputs is
a valid one. In this case, the output, V will be equal to 1.
 If all the inputs of encoder are ‘0’, then the code available at outputs is not a
valid one. In this case, the output, V will be equal to 0.
The Truth table of 4 to 2 priority encoder is shown below.
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

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MAGNITUDE COMPARATOR
• It compares two n-bit binary numbers, say X and Y and activates one of these 3
outputs: X=Y, >Yand X<Y
• The logic equations for the outputs can be written as follows, where G, L, E stand
for greater than, less than andequal to respectively.
(X>Y): G=XY'
(X<Y): L=X'Y
(X=Y): E=X'Y'+XY =(XY'+X'Y)'=(G+L)'

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1-bit Magnitude Comparator
INPUTS OUTPUTS
X Y X >Y X=Y X< Y
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Design two bit magnitude comparator. (solve)
n- bit magnitude comparator:
For a 2-bit magnitude comparator:

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Similarly, for n-bit magnitude comparator will be:

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Programmable Array Logic(PAL)

 This is a programmable array of logic gates on a single chip.
 This is different from a PROM because it has a programmable AND array and
a fixed OR array.
 With a PROM programmer, we can burn in the desired fundamental products,
which are then ORed by the fixedoutput connections.
Realize a full adder using PAL

S = Σ m(1, 2, 4, 7)
Co = Σ m(3, 5, 6, 7)

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PROGRAMMABLE LOGIC ARRAYS (PLA)
 In this, the input signals are presented to an array of AND gates while the
outputs are taken from an array of OR gates.
 In a PROM, the input AND gate array is fixed and cannot be altered, while the
output OR gate array is fusible linked, and can thus be programmed.
 In PAL, the output OR gate array is fixed while the input AND gate array is
fusible linked and thus programmable.
 The PLA is much more versatile than the PROM or the PAL, since both its
AND gate array and its OR gate are fusible linked and programmable.
 PLA is also more complicated to utilize since the number of fusible links are
doubled.
1.Show how we can program a PLA.

f(a,b,c) = a’b’ + abc
g(a,b,c) = a’b’c’ + ab + bc
h(a,b,c) = c

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2. Realise BCD to seven segment display using PLA.

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Module 4 -: Sequential Logic Circuits

Syllabus: The Basic Flip-flop circuit, Clocked Flip-flops, Triggering of Flip-flops, types of Flip-
flop, Master Slave Flip-Flops, Conversion of Flip-flops, types of Shift Registers, applications of
shift register, Verilog implementation of Flip-flop and Shift registers.
Comparison between combinational and sequential logic circuits
Combinational circuits Sequential circuits

1. The output variables depends upon on the The output variables depends upon on the
combination of inputs variables present inputs variables and also on
previous history of these input variables.
2. Memory unit not required Memory unit is required to store the past
history of input variables
3. It does not require any feedback. It simply It involves feedback from output to input
outputs the input according to the logic that is stored in the memory for the next
designed. operation.
4. Faster in speed because the delay in only Slower in speed as delay is because of
due to propagation delay of gates used propagation delay and also due to input
between input and output stages. dependent on previous output.
5. Easy to design Complex than combinational to design
6. Logic gates are building block Flip Flops are building blocks
7. No clock required Clock required of operation
8. Used mainly for Arithmetic and Boolean Used for storing data
operations.
9. e.g. parallel adder, decoder, MUX e.g. Serial adder, flip flops, counters
Flip flop:
A flip-flop is a bistable electronic circuit that has two stable states. The first electronic flip-
flop was invented by British physicists William Eccles and F. W. Jordan in 1918. It was
initially called the Eccles- Jordan trigger circuit.
Types: SR, JK, D, T
Clocked SR Flip flop

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Construction:
 Two NAND gate added to inputs R & S to make RS latch as Flip flop.
 Clock is added as input to enable or disable the latch.
 Clock can be level or edge triggered
Working:
1. Clk =1, R=S=0,
Since Clk =1, Both Input NAND gate output depends upon S & R inputs
Assuming previous Q=0, Q’=1,

input S=0, X=1, Q’ =1 => output Q =0
input R=0, Y=1, Q =0 => output Q’=1
Assuming previous Q=1, Q’=0, NO change in state
input S=0, X=1, Q’ =0 => output Q =1
2. Clk = 1, S=0, R=1,
Since, input R=1, Y=0 => output Q’=1

input S=0, X=1,Q’ =1 => output Q =0 Q=0, Q’= 1
Reset condition
3. Clk =1, S=1, R=0,
Since, input S=1, X=0 => output Q =1

input R=0, Y=1, Q =1 => output Q’ =0 Q=1, Q’= 0
Set condition
4. Clk = 1, S=R=1,
inputS=1, X= 0, Q’ =1 => output Q =1
input R=1, Y=0, Q =0 => output Q’=1 both Q = Q’=1 not possible
inputS=1, X=0, Q’ =0 => output Q = 1 Illegal or forbidden state
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5. Clk = 0,
Since Clk =0, Both Input NAND gate output = 0
Input S & R has no control on the latch => S =R =don’t care
Since X=Y=0, SR latch stays in NO change condition
(NOTE: for ur reference only, NAND gate truth table)
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Excitation Table of SR flip flop
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Characteristics Equation
S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
SR FLIP FLOP TRUTH TABLE
K MAP OF Qn+1

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Qn+1 =S+RQn
Edge Triggered JK flip flop
Construction:
 To avoid the forbidden state of the SR flip flop =>Two AND gate added to inputs SR
Flip flop => this makes JK flip flop
 Enable is connected to positive edge triggered clock. Enable can be connected to
negative edge triggered clock also.
Working:
1. At positive edge triggered, J=K=0,
Both Input AND gate output depends upon J&K inputs
input J=0, AND gate output =>S=0
input K=0, AND gate output =>R=0
Since S=0, R =0, according to SR flip flop=>NO change in state
2.At positive edge triggered, J=0, K=1,

Both Input AND gate output depends upon J & K inputs
input J=0& Q’=1,AND gate output => S=0 Q=0, Q’=1
input K=1& Q=0, AND gate output => R=0
Q =0, Q’ =1
Assuming previous Q=1, Q’=0, Reset condition
input J=0 & Q’= 0, AND gate output => S=0 Q=0, Q’=1
input K=1 & Q=1, AND gate output => R=1

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3. At positive edge triggered, J=1, K=0,

input J=1 & Q’=1, AND gate output => S=1 Q=1, Q’=0
Q =1, Q’ =0
Assuming previous Q=1, Q’=0, Set condition
4. At positive edge triggered, J=1, K=1,
input J=1 & Q’=1, AND gate output => S=1 Q=1, Q’=0
Q = Q’
Assuming previous Q=1, Q’=0, Toggle condition
Excitation Table:
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1

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1 1 0 1
1 1 1 0
JK FLIP FLOP TRUTH TABLE
K MAP OF Qn+1
Qn+1 = JQn + KQn
Edge triggered D flip flop
Construction:
 NOT gate added from J to K input.
 Enable is connected to positive edge triggered clock.
 Enable can be connected to negative edge triggered clock also.
Working:
1. At positive edge triggered, D=0,
Since D=0,
J=0 and K =1=> Reset state of JK flip flop =>Q= 0, Q’ = 1
2.At positive edge triggered, D=1,

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Since D=1,
J=1 and K =0=> Set state of JK flip flop =>Q= 1, Q’ = 0
3. No positive trigger, flip flop is disabled, Output remains as previous state
Excitation Table:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
D FLIP FLOP TRUTH TABLE
K MAP OF Qn+1
Qn+1 = D
Edge triggered T flip flop

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Clock T Q(n+1)
0 X Qn
0 Qn
1 Qn
Construction:
 J connected to K input.
 Enable is connected to positive edge triggered clock. Enable can be connected to
negative edge triggered clock also.
Working:
1. At positive edge triggered, T=0,
Since T=0,
J=0 and K =0=>No change state of JK flip flop =>Q= Q, Q’=Q’
2. At positive edge triggered, T=1,
Since T=1,
J=1 and K =1=>Toggle state of JK flip flop =>Q= Q’
3. No positive trigger, flip flop is disabled, Output remains as previous state
Excitation Table:
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
T FLIP FLOP TRUTH TABLE
K MAP OF Qn+1
T’ T

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Qn’ 0 1
Qn 1 0
Qn+1 = Qn T + Qn T= T XOR Qn
Racing Problem in JK Flip Flop
 Consider the JK flip flop diagram, when clock is high and J&K=11 then two upper
and lower AND gates are only triggered by the complementary outputs Q and Q’.
 In this condition, according to the propagation delay one gate will be enabled and
another gate is disabled.
 If upper gate is disabled then it sets the output and in the next lower gate will be
enabled which resets the flip flop output.
 This condition is called race around condition.
Steps to avoid racing condition in JK Flip flop:

1. If the clock high level time is less than the propagation delay of the flip flop then
racing can be avoided. This is done by using edge triggering rather than level
triggering.
2. If the flip flop is made to toggle over one clock period then racing can be avoided. This
is done by Master Slave JK flip flop.
Master Slave J K Flip flop
 Master-slave flip flop is designed using two separate flip flops. Out of these, one acts
as the master and the other as a slave.
 The output of the master J-K flip flop is fed to the input of the slave J-K flip flop.
 The output of the slave J-K flip flop is given as a feedback to the input of the master
J-K flip flop.
 The clock pulse [Clk] is given to the master J-K flip flop and it is sent through a NOT
Gate and thus inverted before passing it to the slave J-K flip flop.
Working:
 When Clk is positive edge, the master J-K flip flop gets enabled and Slave is disabled.
 When Clk is negative edge, Master is disabled.

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 As Slave is enabled at negative edge. the output of Master reaches to the slave.
 So the next Slave output as input to the Master reaches only at next positive edge.
 The output changes only after one full cycle which eliminates race around condition.
Conversion of flip flops
1. SR Flip Flop to D Flip Flop
Input Preset Next State Flip Flop Inputs

State
D Qn Qn+1 S R
0 0 0 0 X
0 1 0 0 1
1 0 1 1 0
1 1 1 X 0
. SR Flip Flop to JK Flip Flop

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State
J K Qn Qn+1 S R
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1
JK Flip Flop to T Flip Flop

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State
T Qn Qn+1 J K
0 0 0 0 X
0 1 1 X 0
1 0 1 1 X
1 1 0 X 1
D Flip Flop to SR Flip Flop
Input Preset Next State Flip Flop

State Input
S R Qn Qn+1 D

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0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 X X
1 1 1 X X
T Flip Flop to JK Flip Flop
Input Preset Next State Flip Flop

State Input
J K Qn Qn+1 T

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0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1
K – map simplification
T = J Qn’ + K Qn
REGISTERS
• A register is a group of flip-flops used to momentarily store binary-information.
• Each flip-flop can store either 0 or 1.
• The flip-flops used to construct registers are usually edge-triggered JK, SR or D types.
• The register can also be used
→ to accept input-data from an alphanumeric keyboard and then present this data at the
input of a microprocessor-chip.
→ to momentarily store binary-data at the output of a decoder.
→ to perform various arithmetic operations. For ex: multiplication & division.
→ to count number of pulses entering into a system as up-counter, down-counter, ring-
counter or Johnson-counter.

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→ as serial-adder, sequence-generator and sequence-detector.
TYPES OF REGISTERS
• Shift-register is a group of flip-flops connected in such a way that a binary-number can be
shifted into or out of the flip-flops.
• The bits in a binary-number can be moved from one place to another in following 2 ways:
1. Serial shifting: Data-bits are shifted one after the other in a serial fashion with one bit
shifted at each clock transition
2. Parallel shifting: Data-bits are shifted simultaneously with a single clock transition.
SHIFTING SERIAL BINARY-DATA INTO THE REGISTER

 A common clock provides trigger at its negative edge to all the flip-flops
 The output of one D flip-flop is connected to input of the next.
 At every clock trigger, data stored in one flip-flop is transferred to the next flip-flop.
 Serial input ->d input -> Q -> R -> S->T
 Let the input be 0100
 At clock A, d input =0 , QRST = 0000
 At clock B, d input=0, QRST=0000.
 At clock C, d input=1, QRST=1000.
 At clock D, d input=0, QRST=0100.
SHIFTING BINARY-DATA OUT SERIALLY OF THE REGISTER
 Before Time A: The register holds QRST=1010

 At Time A: QRST=0101 and serial output =0

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 At Time B: QRST=0010 and serial output =1

 At Time C: QRST=0001 and serial output =0
 At Time D: QRST=0000and serial output =1.
 Thus, the binary-data stored is shifted out of the right-end of the register in a serial
fashion and lost after 4 clock cycles.
Types of shift registers
→ Serial in-Serial out - SISO
→ Serial in-Parallel out - SIPO
→ Parallel in-Serial out - PISO
→ Parallel in-Parallel out – PIPO
1. SISO- SERIAL IN SERIAL OUT
 In this shift register, when the clock signal is applied and the serial data is given; only
one bit will be available at output at a time in the order of the input data.
 The use of SISO shift register is to act as temporary data storage device.
 The main use of a SISO is to act as a delay element.
CLK Serial Q3 Q2 Q1 Q0 Serial

Input Output
0 0 0 0 0 0
1 1 0 0 0 0
2 0 1 0 0 0
3 1 0 1 0 0
4 1 0 1 0
5 0 1 0 1 0
6 0 0 1 0 1
7 0 0 0 1 0
8 0 0 0 0 1
2.PIPO – PARALLEL INPUT PARALLEL OUTPUT

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 There are no interconnections between any of the four flip flops.

 In one clock, parallel data goes in and parallel output is out.
 A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device
and also as a delay element similar to a SISO shift register.
CLK Parallel Q3 Q2 Q1 Q0
Input
0 0101 0 0 0 0
1 0 1 0 1
Parallel output
3. SIPO- SERIAL INPUT PARALLEL OUTPUT
 The output of Serial in Parallel out (SIPO) shift register is collected at each flip flop.
 The main application of Serial in Parallel out shift register is to convert serial data
into parallel data. Hence they are used in communication lines where demultiplexing
of a data line into several parallel line is required.
CLK Serial Q3 Q2 Q1 Q0 Serial

Input Output
0 0 0 0 0 0

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1 1 0 0 0 0
2 0 1 0 0 0
3 1 0 1 0 0
4 1 0 1 0
Parallel output
4. PISO- PARALLEL INPUT SERIAL OUTPUT
 The output of the previous flip flop and parallel data input are connected to the input
of the MUX and the output of MUX is connected to the next flip flop.
 A Parallel in Serial out (PISO) shift register converts parallel data to serial data.
Hence they are used in communication lines where a number of data lines are
multiplexed into single serial data line.
CLK Parallel Q3 Q2 Q1 Q0 Serial

Input Output
0 0101 0 0 0 0
1 0 1 0 1
2 0 0 1 0 1
3 0 0 0 1 0
4 0 0 0 0 1
5 0 0 0 0 0

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 For parallel input, Shift/ load’ input = LOW

 This makes G2,G4,G6 AND active, inputs A B C D enters the registers parallel
 For serial shifting, Shift/ load’ input = HIGH
 This makes G1, G3, G5 AND active, output previous Q enters next stage D input
allowing serial shifting.
Bidirectional shift register

 A bidirectional, or reversible, shift register is one in which the data can
be shift either left or right.
 For right shift, control line right/ left’ = High

 G1, G3, G5, G7 AND gates are active
 Serial input (right) -> D3, Q3 -> D2, Q2 -> D1,Q1 -> D0
 Serial output available at Q0
 For left shift, control line right/ left’ = LOW

 G2, G4, G6, G8 AND gates are active
 Serial input (left) -> D0, Q0 -> D1, Q1 -> D2, Q2 -> D3
 Serial output available at Q3

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Universal shift register

 Can perform SISO, SIPO, PIPO, PISO
 Also can do right and left shift
 MUX control the operation depending upon S0,S1
 When S1 S0 = 01, Right shift

 Serial input (right) -> D3, A3-> D2, A2 ->D1, A2 -> D0
(Indicated by green lines)
 When S1 S0 = 10, Left shift
 Serial input (left) -> D0, A0-> D1, A1 ->D2, A2 -> D3
(indicated by blue lines)
 When S1 S0 = 11, parallel loading
 Parallel inputs, I0 loads as A0, I1 loads as A1, I2 loads as A1, I3
loads as A3
(Indicated by orange lines)
 When S1 S0 = 00, holding or locking data
 Previous state output is feedback as input to get same output
 A0 fed back to D0, A1 fed back to D1,A2 fed back to D2,A3 fed
back to D3
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(Indicated by Red lines)
APPLICATIONS OF SHIFT REGISTER

1. RING COUNTER
 It is a basic shift registers with direct feedback such that the contents of the register
simply circulate around the register when the clock is running.
 The output of the most significant stage is fed back to the input of the least significant
stage.
 The following is a 4-bit ring counter constructed from D flip-flops. The output of each
stage is shifted into the next stage on the positive edge of a clock pulse.
 If the CLEAR signal is high, all the flip flops except the first one FF0 are reset to 0.
FF0 is preset to 1 instead.

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2. Johnson Counters
 Johnson counters are a variation of standard ring counters, with the inverted output of
the last stage fed back to the input of the first stage.
 They are also known as twisted ring counters or switched tail counter.
 An n-stage Johnson counter yields a count sequence of length 2n, so it may be
considered to be a mod-2n counter.
Verilog Code to be studied from class notes

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Module 5 -: Analysis of Sequential Circuit

Syllabus: Binary ripple counters, synchronous binary counters, Design of a synchronous
mod-n counter using clocked T, JK , D and SR flip-flops, Verilog implementation of
counters, Mealy and Moore Models, State Reduction and Assignment, Design Procedure,
Design with State Equations, Verilog implementation of Moore and Mealy.
Counter:
• This is a digital-circuit designed

→ to keep track of a number of events or
→ to count number of clock cycles (Figure 1.21).
• This can be constructed using
→ number of flip-flops (e.g. JK, SR, D and T) &
→ additional electronic circuits.
• This is similar to a register, since it is also capable of storing a binary number (e.g.
1011).
• The input to the counter is rectangular waveform CLOCK.
• Each time the clock signal changes state from low to high (0->1), the counter will
add one (1) to the number stored in its flip-flops. In other words, the counter will
count the number of clock-transitions from low to high.
Types of counters:
1) Asynchronous Counter (Serial Counter)
 Each flip-flop is driven by the output of the previous flip-flop i.e. the output of
a flip-flop isused as the clock-input for the next flip-flop
 Advantage: It requires less hardware.
 Disadvantage: It operates at low speed.
2) Synchronous Counter (Parallel Counter)
 All flip-flops change states simultaneously since all clock inputs are driven by
the same clock.i.e. all the flip-flops change states in synchronism.
 Advantage: It operates at high speed.
 Disadvantage: It requires more hardware.
Counters can also be classified as:

1) Up Counter
 It can be used to count upward from a 0 to maximum-count
0 ->1 ->2 ->3 -> 4(MOD-5)
 With each clock-transition, the content of the counter is increased by 1.
2) Down Counter:
 It can be used to count downward from a maximum-count to 0.
3 ->2 ->1->0.(MOD-4)
 With each clock-transition, the content of the counter is decreased by 1.
3) Up-down Counter:
 It is capable of counting in either an upward or a downward direction.
Mod 4 = COUNT 0 TO 3 (11 in binary)=> requires 2 2 => 2 flip flop
Mod 8 = COUNT 0 TO 7(111 in binary) => requires 2 3=> 3 flip flop

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Mod 14 = COUNT 0 TO 13(1101 in binary)=> requires 2 4=> 4 flip flop
Mod 128 = COUNT 0 TO 127(111 1111 in binary) => requires 2 7 => 7 flip flop
Q1. Explain a 3-bit binary Ripple UP counter. Also write the block diagram,
truth table and waveform.
ANS:
ASYNCHRONOUS 3-BIT UP-COUNTER (RIPPLE-COUNTER)
• Each flip-flop is driven by the output of the previous flip-flop i.e. the output of a flip-
flop is used as the clock-input for the next flip-flop.
Up-Counter:
 It can be used to count upward from a 0 to maximum-count.
i.e. it counts in an upward direction. 0 ->1 ->2 ->3->4->5->6->7
 A 3-bit counter can be used to count a maximum of 7 clock-transitions
 This can be constructed using clocked JK flip-flops.
 All J and K inputs of flip-flops are tied to +Vcc. This means, with each clock-
transition, the flip-flop will change its state (toggle
Working:
 The counter outputs are A, B, and C.
 The system-clock is used to drive(or trigger) flip-flop A.
 The output of flip-flop A is used to drive flip-flop B.
 Likewise, the output of flip-flop B is used to drive flip-flop C.
 The triggers move through flip-flops like a ripple in water. Hence, it is called
ripple counter.
 Flip-flop A toggles with each clock-transition.
 Flip-flop B will toggle each time A goes LOW (1 to 0).
 Likewise, flip-flop C will toggle each time B goes LOW (1 to 0).
 The overall propagation delay time is the sum of the individual delays.

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Q2) Explain a 3-bit binary Ripple Down counter. Also write the block diagram,
truth table and waveform.
ASYNCHRONOUS 3-BIT DOWN-COUNTER
 Each flip-flop is driven by the output of the previous flip-flop i.e. the output of a
flip-flop is used as the clock-input for the next flip-flop.
Down Counter:
 It can be used to count downward from a maximum-count to 0
it counts in an downward direction ( 7->6->5->4-> 3 ->2 ->1-> 0).
 With each clock-transition, the content of the counter is decreased by 1.
 A 3-bit counter can be used to count a maximum of 7 clock-transitions.
transition, the flip-flop will change its state (toggle).
Working:
 The counter outputs are A, B, and C.
 The system-clock is used to drive(or trigger) flip-flop A.,
 But, the complement of A (i.e. A') is used to drive flip-flop B,
 Likewise B' is used to drive flip-flop C.
 The triggers move through flip-flops like a ripple in water. Hence, it is called
ripple counter.
 Flip-flop A toggles with each clock-transition.
 But flip-flop B will toggle each time A goes HIGH (0 to 1).
 Likewise, flip-flop C will toggle each time B goes HIGH (0 to 1).
 The overall propagation delay time is the sum of the individual delays.

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Q3. Explain a 3-bit binary Ripple Up-down counter. Also write the
block diagram, truth table and waveform.
ASYNCHRONOUS 3-BIT UP-DOWN-COUNTER
Up-down Counter:
 It is capable of counting in either an upward or a downward direction.
 It is simply a combination of the up counter & down counter.
 A 3-bit counter can be used to count a maximum of 7 clock-transitions.
Working:
1) To operate in the Count-up Mode

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 If Count-up = high and the Count-down = low, the lower AND gates Y1 and Y2
are disabled.
 The clock applied to flip-flop A will be steered into the other flip-flops by AND
gates X1 and X2.
2) To operate in the Count-down Mode
 If Count-up = low and the Count-down =high, the upper AND gates X1 and X2
are disabled.
 The clock applied to flip-flop A will be steered into the other flip-
flops by AND gates Y1 and Y2.
 Drawbacks: The additional gates (AND & OR) introduce additional
delays.
Q4. Differentiate synchronous and asynchronous counter.
Asynchronous Counter Synchronous Counter

1. Flip flops are connected such that No connection between output from
output of first drives the clock for first to next flip flop clock.
the next flip flop
2. All flip flops are not clocked All the flip flops are clocked
simultaneously simultaneously
3. Simple logic circuit Complex logic circuit
4. Propagation delay is more as clock No propagation delay as
is propagated through number of simultaneous clock given to all flip
flip flops flops
5 Difficult to design Can be designed
Q 5) Explain a 3-bit binary synchronous up counter. Also write the block

diagram, truth table and waveform.

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SYNCHRONOUS 3 BIT UP-COUNTER (PARALLEL BINARY COUNTER)

 All flip-flops change states simultaneously since all clock inputs are driven by
the same clock
i.e. all the flip-flops change states in synchronism
Up Counter:
 It can be used to count upward from a 0 to maximum-count.
it counts in an upward direction (e.g. 0 ->1 ->2 ->3->4->5->6->7->0).
 A 3-bit counter can be used to count a maximum of 7 clock-transitions
Working:
 The clock is applied directly to the flip-flop A. As result, with each clock-
transition, flip-flop A will change its state (toggle).
 When A is high, hence it makes flip-flop B to toggle.
 When A & B are high, AND gate-Y is enabled & hence it makes flip-flop C
toggle.
CLK QA QB QC
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
9 0 0 0

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SYNCHRONOUS MOD 16 UP-COUNTER (PARALLEL BINARY COUNTER)
Working and truth table and waveform:

Similar to mod 8 above
COUNTER DESIGN AS A SYNTHESIS PROBLEM
Design a modulo-6 counter.

Solution:
 In mod-6 counter, there are 6 states. So, we need 3 flip-flops to design mod-6
counter.
 Let the three JK flip-flops be FF-A, FF-B and FF-C
 With 3 flip-flops, 8 different states are possible but states 110 & 111 are not
used.

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Excitation table of all flip flops
0 -> 1-> 2 -> 3-> 4->5 ->0
State diagram of Mod -6 counter
STEP 1: State table for Mod -6
STEP 1: K-MAP

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STEP 3: Circuit diagram for Mod-6 synchronous counter

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SELF-CORRECTING COUNTER
 Lock out of a counter means counter getting locked into unused states.
Solution: Use self-correcting counter
 Unused states 110 and 111 can no longer be considered as don't
care.
 This type of design is called self-correcting as the circuit comes out
on its own from an invalid state to a valid state.

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Q6. Design a modulo-4 irregular counter with following counting sequence using D
flip-flop.
00  10 11  01

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DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUIT
The first step in a sequential logic synthesis problem is to convert word description or
problem description to State transition diagram or Algorithm State Machine (ASM)
Chart.

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State Transition Diagram is done using two type of model: Moore Model or Mealy
Model.
Moore Model:
 The output is generated only from the current state variables.
Design sequence detector to detect a serial input sequence of110.
State Transition Diagram using Moore Model for sequence detector 011
State Synthesis Table

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Circuit Diagram
Mealy Model
 The output depends upon previous state as well as current input

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State Transition Diagram using Mealy Model for sequence detector 011
State Synthesis Table

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STATE REDUCTION TECHNIQUE
Two methods:
1, Row Elimination Method
2. Implication method
Row Elimination Method:
 In this method, we first prepare a state table where at any given state the next
state and present output(s) are written for each combination of input(s).
 In the present problem there are only two possible values of input X = 0 and X
= I.
 For 2 input circuits there will be 22 = 4 such combinations in this table.
 Now, two states are considered equivalent if they move to same or equivalent
state for every input combination and also generate same output.

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Implication Table Method

 Implication table provides a more systematic approach towards solution of a
complex state reduction problem.
 For n states in the initial description we have n-l rows in implication table and
as many number of columns.

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 The cross-point in an implication table is the location where a row and a

column meet.
 The conditions for equivalence between the states crossing each other are
tested.
 In Step 1, identify the states, which cannot be equivalent, as their outputs do
not match. This is denoted by putting a double-cross in respective cross
points.
 In Step 2, for other cross points, we write necessary conditions for

equivalence of intersecting states.
 In Step 3, we use relationships obtained in Steps 1 and 2, especially the ones
represented by double cross and double tick mark and check if any other
cross points can be crossed or ticked.
 In Step 4, we keep repeating Step 3 and cross or tick (if possible) as many
cross points in the implication table as possible.
 In Step 5, we check pair-wise equivalence starting from rightmost column e of
implication table.
Numerical to solve:
I. Design counter which counts:

 MOD- 5 up counter using SR.
 MOD- 12 up counter using D.
 MOD – 7 down counter using T.
 Decade counter (MOD-10) using J K.
 MOD-5 self correcting using D.
II. Design MOORE model for:
 To detect 11011 using D
 To detect 1011 using JK
 To detect 10110 using T

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III. Design MEALY model for:

 To detect 1101 using JK
 To detect 11011 using SR
IV. Reduce state using both the methods:

a)
b)
c)

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d)

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DE-19CSE33

Course Name: Digital Electronics

Course Code: 19CSE33

Prepared by Asha Rani Borah, CSE dept., NHCE Page 1

Module 1 -: Analog devices for Digital Electronics

6. Poor thermal stability Better thermal stability

10. Better gain than FET Less gain

N-Channel Depletion MOSFET (DE- MOSFET)

Prepared by Asha Rani Borah, CSE dept., NHCE Page 2

Symbol (Draw the 3 terminal symbol)

Prepared by Asha Rani Borah, CSE dept., NHCE Page 3

2. When VGS = -ve: Depletion mode

3. When VGS = +ve: Enhancement mode

In Depletion MOSFET operation:

 When VGS = 0V, ID = IDSS

The formula used to plot the Transfer Curve, is:

Prepared by Asha Rani Borah, CSE dept., NHCE Page 4

Transfer characteristics Output characteristics

NOTE: P-Channel depletion MOSFET

 When VGS = 0V, ID = IDSS

Prepared by Asha Rani Borah, CSE dept., NHCE Page 5

Prepared by Asha Rani Borah, CSE dept., NHCE Page 6

1. When VGS =0:

 Since no channel between drain and source, ID= 0

2. When VGS =-ve:

3. When VGS =+ve:

Prepared by Asha Rani Borah, CSE dept., NHCE Page 7

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 VGS > VT, ID = 0 =>E-MOSFET is OFF

CMOS- Complementary MOSFET

Prepared by Asha Rani Borah, CSE dept., NHCE Page 9

 Used to clip or remove whole or part input signal

 Positive Series clipper:

Prepared by Asha Rani Borah, CSE dept., NHCE Page 10

 Negative Series clipper:

Positive Clipper with Bias

 Diode parallel to input signal

 During -ve input cycle, D = OFF, so current in circuit flowing to output,

Negative Clipper with Bias

 Diode parallel to input signal

Prepared by Asha Rani Borah, CSE dept., NHCE Page 11

 During +ve input cycle, D = OFF, so currnt in circuit flowing to output,

Prepared by Asha Rani Borah, CSE dept., NHCE Page 12

Prepared by Asha Rani Borah, CSE dept., NHCE Page 13

Q. What is Multivibrators? Mention the types of Multivibrators.

Prepared by Asha Rani Borah, CSE dept., NHCE Page 14

 So, base voltage of Q2 increases which causes output of Q2 to increase further.

Note: To remember, don’t write in exam:

2. When negative trigger applied at Q2 base:

Note: To remember, don’t write in exam:

Prepared by Asha Rani Borah, CSE dept., NHCE Page 15

3. When negative trigger applied at Q1 base:

Note: To remember, don’t write in exam:

 C1 and C2 capacitors are known as speed up capacitors. Their function is to increase

Q. Explain the internal block diagram of 555 timer IC.

Prepared by Asha Rani Borah, CSE dept., NHCE Page 16

Pin 3: Output Terminal: Output of the timer is available at this pin.

Prepared by Asha Rani Borah, CSE dept., NHCE Page 17

Prepared by Asha Rani Borah, CSE dept., NHCE Page 18

Module 2 - Simplification of Boolean Functions:

1. Combinational Logic Circuits: Circuits without memory

Combinational Logic Circuits

There are two fundamental approaches in logic design: