BANK SWITCHING

ADDRESSING MODES….
• How CPU is accessing Data……

• IMMEDIATE (MOVLW 20H. Operand is a literal

constant. Operand comes immediately after opcode in
the instruction)
• DIRECT (MOVWF 40, MOVFF 40,50 Etc.. Address is
given after the opcode in the instruction)
• REGISTER INDIRECT

• INDEXED
 Recap….
• The 256-byte access bank file register is split into
two sections: The lower addresses, 00 to 7FH, are assigned to
the general purpose registers, and the upper addresses, F80-
FFFH, to the SFR.
•The access bank is the default bank when the PICI8 is

powered up. It is the minimum bank that all PICI8

processors have.
•The entire data RAM file register can be accessed using either direct

or register indirect addressing modes

 Direct Vs Immediate…….
• In direct addressing mode, the operand data is in a RAM

memory location whose address is known, and this address

is given as a part of the
instruction.
• In immediate addressing mode in which the operand data

itself is provided with the instruction

• letter "L" in the instruction means literal (immediate), the letter "F"
in the instruction signifies the address of the file
register location.
•The two direct addressing instructions :

• If we see the opcode in program memory, we can

see that the addresses are embedded in the
instruction.
 MOVWF Direct Addressing Opcode

• Address field is 8-bit wide.

• Can take values from OO-FFH.

• It is much easier to use names (Labels) instead of addresses in the

program
• File register data RAM does not support immediate addressing
mode. To move data into any file register, we must first move it to
WREG, and then move it from WREG to the file register using the
MOVWF instruction.
REGISTER INDIRECT ADDRESSING MODE
• Use ‘register direct’ or ‘register indirect’ addressing
modes to access data stored in the general purpose
RAM section of the file register.
• The ‘register indirect’ addressing mode uses a
register as a ‘pointer’ to the data RAM location.
• In the PIC18, three registers are used for this
purpose:
FSR0, FSR1, and FSR2.
REGISTER INDIRECT ADDRESSING MODE
•FSR stands for file select register.
• The FSR is a 12-bit register - access to the entire 4096
bytes of data RAM space in the PIC18 is now possible.
• Use LFSR instruction (load FSR) to load the RAM
address.
• When FSRx are used as pointers, they must be
loaded first with the RAM addresses.

LFSR 0, 0x30 ;load FSR0 with Ox30

LFSR 1, 0xA3 ;load FSR1 with OxA3

LFSR 2, 0x8E ;load FSR2 with Ox8E

 FSR …. SFR
• Because FSR0, FSR1, and FSR2 are 12-bit
registers they cannot fit into the
SFR space.

• Hence, they are split into pieces of

8- bit size and put into two registers.

• The FSR registers have the low-byte and

high-byte parts called FSRxL and FSRxH.
Indirect addressing registers……
• FSR0L and FSR0H, represents the low and high parts
of the 12-bit ‘FSR0’ register.
• FSRxH is only 4-bit and the upper 4 bits are not used.

• The indirect register ‘INDF’ is Another register

associated with the register indirect addressing mode.
• Each of the FSR0, FSR1, and FSR2 registers has an
INDF register associated with it, and these are called
INDF0, INDF1, and INDF2.
Indirect addressing registers……
• Indirect addressing is possible by using one of the INDF
registers.
• Any instruction using the INDF register actually
accesses the register indicated (Pointed) by the File Select
Register,
FSR.
• Reading the INDF register itself, indirectly (FSR = 0), will read
00h.
• Writing to the INDF register indirectly, results in a no
operation.
• The INDFn (0 ≤ n ≤ 2) register is not a physical register.
• Addressing INDFn actually addresses the register
whose address is contained in the FSRn register
(FSRn is a pointer). This is indirect addressing.
 Indirect addressing….
LFSR 0, 0x3a8 ;FSR0 = 3a8H RAM location address
MOVWF INDF0 ;copy contents of WREG into RAM
;location whose address is held by
;12-bit FSR0 register

• When we move data into INDFx we are moving data into a RAM
location pointed to by the FSRx.

• Similarly, when we read data from the INDFx register, we are

reading data from a RAM location pointed to by the FSRx register.

• In disassembly listing, ‘MOVWF INDF0’ will become ‘MOVWF

0xfef ’ , Where 0xfef is the address of the ‘INDF0’ SFR.
Advantages of register indirect addressing mode

• It makes data accessing dynamic rather than

static (for direct addressing).
• Copying 55H into RAM locations 40H to 45H.
 To load memory locations ….

Method 1 : Using direct addressing -

MOVLW Ox55 ;load WREG with value 55h

MOVWF Ox40 ;copy WREG to RAM location 40h

MOVWF Ox41 ;copy WREG to RAM location 41h

MOVWF Ox42 ;copy WREG to RAM location 42h
MOVWF Ox43 ;copy WREG to RAM location 43h
MOVWF Ox44 ;copy WREG to RAM location 44h
Method -2: Indirect addressing -
MOVLW 55H ;load WREG with value 55h
LFSR 0,0x40 ;load thepointer FSR0 = 40h
MOVWF INDF0 ;copy W to RAM location pointed by FSR0
INCF FSR0L,F ;increment pointer. Now, FSR0 = 41h
MOVWF INDF0 ;copy W to RAM location pointed by FSR0
INCF FSR0L,F ;increment pointer. Now, FSR0 = 42h
MOVWF INDF0 ;copy W to RAM location pointed by FSR0
INCF FSR0L,F ;increment pointer. Now, FSR0 = 43h
MOVWF INDF0 ;copy W to RAM location pointed by FSR0
INCF FSR0L,F ;increment pointer. Now, FSR0 = 44h
MOVWF INDF0 ;copy W to RAM location pointed by FSR0
• In this method, two instructions are repeated
numerous times.
• We can create a loop with those two instructions
as shown in next method.
 Method - 3: Indirect addressing -
COUNT EQU 0x10 ;location 10h as counter
MOVLW 0x5 ;WREG =5
MOVWF COUNT ;load the counter with count = 5
LFSR 0,0x40 ;load pointer. FSR0 = 40h, RAM address.
MOVLW 0x55 ;WREG = 55h, Value to be copied
B1 MOVWF INDF0 ;copy WREG to RAM loc., FSR0 points to.
INCF FSR0L,F ; increment pointer FSR0

DECF COUNT,F ; decrement the counter

BNZ B1 ;loop until counter = 0.
• This is the most efficient method and is possible only because of the

register indirect addressing mode.

• Must use "INCF FSR0L, F" to increment the pointer because there

is no ‘FSR0’ register, we have only FSR0L and FSR0H.

• Looping is not possible in direct addressing mode, that is the main

difference between the direct and register indirect addressing modes.

•Trying to send a string of data located in consecutive locations of data RAM is much
more efficient and dynamic using register indirect addressing mode than using direct
addressing mode.

• Use MPLAB IDE to see the memory locations after the execution of
these programs.
 Auto-increment option for FSR
• Because the FSR is a 12-bit register, it can go from 000 to
FFFH, which covers the entire 4K RAM space of the PIC18.
• Using the "INCF FSROL, F“ instruction to increment the
pointer can cause a problem when an address such as 5FFH is
incremented.
• The instruction "INCF FSROL, F" will not propagate the
carry into the FSR1H register.
• The PIC18 gives us the options of auto-increment and auto-
decrement for FSRn to overcome this problem.
The syntax used for such cases for the CLRF instruction
CLRF INDFn After clearing fileReg pointed to by FSRn, the FSRn stays the same.

CLRF POSTINCn After clearing fileReg pointed to by FSRn, the FSRn is incremented.

CLRF PREINCn The FSRn is incremented, then fileReg pointed to by FSRn is cleared.

CLRF POSTDECn After clearing fileReg pointed to by FSRn, the FSRn is

decremented.

CLRF PLUSWn Clears fileReg pointed to by (FSRn +WREG), FSRn & W unchanged.

• This table shows the syntax for the CLRF instruction, it works for all such
instructions.
• The auto-decrement or auto-increment affects the entire 12 bits of the FSRn
and has no effect on status register.
• This means that FSR0 going from FFF to 000 will not raise any flag.
• The option of PLUSWn is widely used for a RAM-based look-up table.
 Clear 16 RAM locations starting at
RAM address 60H.
COUNTREG EQU 0x10 ;fileReg loc for counter
CNTVAL EQU 0x16 ;counter value
MOVLW CNTVAL ;WREG = 16
;load the counter, Count = 16
MOVWF COUNTREG ;load pointer. FSR1 = 60H, RAM
LFSR l,Ox60 Address
B2 CLRF INDF1 ;clear RAM loc FSRI points to
INCF FSR1L,F ;increment FSR1L, point to next lo
DECF COUNTREG,F ;decrement counter
;loop until counter = zero
BNZ B2
COUNTREG EQU 0xl0 ;fileReg loc for counter
CNTVAL EQU 0'16' ;counter value

MOVLW CNTVAL ;WREG = 16

MOVWF COUNTREG;load the counter, Count = 16
;load pointer. FSR0 = 60H, RAM
LFSR 1,0x60
address
B3 CLRF POSTINC1 ;clear RAM, increment FSR1 pointer
DECF COUNTREG,F

BNZ B3 ;decrement counter

;loop until counter = zero
HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING

LFSR FSR0,0x100 ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
GOTO NEXT ; NO, clear next
CONTINUE ; YES, continue
INDIRECT ADDRESSING OPERATION
 Bank Switching…
• All the instructions we have used so far assumed the access bank as the

default bank.
• This was achieved by ignoring the letter A in instructions such as
"MOVWF fileReg, A".
• In other words, the instruction "MOVWF fileReg" is really
"MOVWF f i leReg, A" where the A bit can be 0 or 1.
• If A = 0, then the access bank is the default bank. If A = 1, however, then the
instruction will use the bank selector register (BSR) to select the bank instead of
using the access bank.
• If A is not stated in a given instruction, it means A = 0 and the access bank is the
default bank.
• It is for the simple reason of making the PIC18 Assembly language easier to
understand and master.
 The BSR register and bank switching
• To use banks other than the access bank, we need to set
bit A = 1 in the coding of the instruction.
• With A = 1, we use the BSR (bank select register) to choose
the desired bank.
• The BSR is an 8-bit register and is part of the SFRs.

• Of the 8 bits of the BSR, only 4 least-significant bits are

used in the PICI8.
• The upper 4 bits are set to zero and are ignored by the
PICI8.
•
 The BSR register and bank switching
• As we can see, no matter how much data RAM we have in the PICI8, the
GP register always starts at address 000 and goes up, while the SFRs
start at the other end of the 4 KB, at address FFF, and come down.
• Presently, PIC is using only the highest 128 bytes of bank F (F80H-FFFH
address) for the SFRs.
• In the future they might start to use the rest of bank F and may even use
bank E for SFRs, if the special functions embedded into the PIC 18 keep
increasing.
• Although the number of bytes in bank F used for SFRs in the PIC18 chip
varies depending on the functions embedded into the chip, the SFRs
always start at address FFF and go down.
 The BSR register and bank switching
• The 4-bit BSR gives us access to 16 banks.

• Because each bank is 256 bytes, we cover the

entire 4096 (16 x 256 = 4096) bytes of the data
RAM file register using BSR.
• The 4K (4096) bytes of the data RAM are
organized as banks 0 to F, where the lowest bank,
0, has an address of 000-0FFH, and the highest
bank is bank F with the addresses of F00-FFFH.
 The BSR register and bank switching
• In the PICI8, the last 128 bytes of bank F are always
set aside for the SFRs, while general purpose
registers always start at address 0 of bank 0.
• Upon power-on reset, BSR = 0 (0000 binary), which
indicates that only the lowest addresses of data
RAM, from 000 to 0FFH, can be used for the general-
purpose register in addition to the SFRs, which
always reside in the last half of bank F.
 The BSR register and bank switching

• If we make BSR = 1 (0001 binary), then PIC18

selects bank 1 using the 100-1FFH addresses in
addition to the SFRs, which use only the last half of
the bank with addresses of F80-FFFH.
• To select bank 2, we load BSR with the value 2
(0010 binary), which allows access to the bank
addresses 200-2FF in addition to the SFR
addresses of F80-FFFH.
The BSR register and bank switching
Bank switching and "INCF F, 0, A" instruction
Bank switching and "INCF F, 0, A" instruction
 The BSR register and bank switching
• Now to use banks other than the access bank, two things must be done:

• 1. Load the BSR with the desired bank number (Use ‘MOVLB’ instruction to
do this.)

2. Make A = 1 in the instruction itself.

• Instruction "INCF MYREG, F, 1" has a totally different meaning from "INCF
MYREG, F, 0".
• A = 1 means to use the bank pointed to by BSR.

• BSR contains the higher 4 bits of the 12 bit RAM address (ie, the Bank No.).

This is needed when only 8 bit space is available in the instruction for the
address –For such instructions, remaining 4 bits have to be taken from the
BSR, to cover the 4k space.
• Eg. MOVWF instruction can contain only 8 bit address.
MYREG EQU 0x40
MOVLB 0x2   ;load 2 into BSR (use bank 2)
MOVLW 0   ;WREG = 0
MOVWF MYREG, 1 ;loc 0x240 (0) , WREG 0, Notice A =1

INCF MYREG, F, 1 ;loc 0x240 (1) , WREG = 0, Notice A = 1

INCF MYREG, F, 1 ;loc 0x240 (2) , WREG =0, Notice A =1

INCF MYREG, F, 1 ;loc 0x240 (3) , WREG = 0

MYREG EQU 0x40

MOVLB 0x2   ;load 2 into BSR (use bank 2)
MOVLW 0   ;WREG = 0
MOVWF MYREG ;loc 0x40 (0) , WREG 0, Notice A = 0
INCF MYREG, F ;loc 0x40 (1) , WREG = 0, Notice A = 0
INCF MYREG, F ;loc 0x40 (2) , WREG =0, Notice A = 0
INCF MYREG, F ;loc 0x40 (3) , WREG = 0
• Although we loaded BSR, because the A bit was not
indicated, MPASM defaults it to zero, which means to use
location Ox40 of the access bank.

MOVLB 0x2 ;load 2 into BSR (use bank 2)

MOVLW 0 ;WREG = 0
MOVWF 0x20,1 ;loc Ox220 = (0), WREG = 0, D = W,A = 1
means Bank 2
INCF 0x20,W,1 ;loc Ox220 = (0), WREG = 1, D = W, A=1
INCF 0x20,W,1 ;loc Ox220 = (0), WREG = 1, D = W, A=1
INCF 0x20,W,1 ;loc Ox220 = (0), WREG = 1, D = W, A=1
INCF 0x20,F,1 ;loc Ox220 = (1), WREG = 1, D = F, A=1
INCF 0x20,F,1 ;loc Ox220 = (2), WREG = 1, D = F, A=1
INCF 0x20,F,1 ;loc Ox220 = (3), WREG = 1, D = F, A=1
INCF 0x20,F,1 ;loc Ox220 = (4), WREG = 1, D = F, A=1
• Write a program to copy the value 55H into RAM
memory locations 340H to 345H using:
• 1. Direct addressing mode. (MOVWF f , a is the format)

MOVLB Ox3 ;BANK 3. Load 3 to BSR.

MOVLW Ox55 ;load WREG with value 55H
;copy WREG to RAM location 340H - Bank 3, Loc - 40.
MOVWF Ox40, 1
MOVWF Ox41, 1 ;copy WREG to RAM location 341H
MOVWF Ox42, 1 ;copy WREG to RAM location 342H
MOVWF Ox43, 1 ;copy WREG to RAM location 343H
MOVWF Ox44, 1 ;copy WREG to RAM location 344H
Using FSR register (indirect addressing) in a loop….

COUNT EQU 0xlO ;loc 10h

MOVLB 0x3 ;BANK 3. Load it to BSR. NO EFFECT.
MOVLW 0x5 ;WREG = 5
MOVWF COUNT ;load the counter, count = 5
LFSR 0,0x340 ;load pointer. FSRO = 340H, RAM
address
MOVLW 0x55 ;WREG = 55h value to be copied
Bl MOVWF INDF0,0* ;copy WREG to RAM loc FSR0 points
to.
INCF FSR0L ;increment FSROL pointer
DECF COUNT,F,0 ;decrement the counter
BNZ Bl ;loop until counter = zero

* Don’t make a=1 (bank in BSR) here. It will result in

erroneous result. As FSRx contains 12 bit address, it
can cater for the entire 4k RAM. No need to use BSR.
• In disassembly listing, ‘MOVWF INDF0,0’ will become ‘MOVWF
0xfef , ACCESS’ ,(mapped as 6EEF) Where 0xfef is the address
of the ‘INDF0’ SFR.
• Where as ‘MOVWF INDF0,1’ will become ‘MOVWF 0xef ,
BANKED’ (mapped as 6FEF). Hence, when we use BSR along
with this, the effective address become ‘0xnef’, where ‘n’ is the
bank number in BSR. FSR will not have any effect on this
instruction now.
• As FSRx itself can handle entire 12 bit address (4k RAM), don’t
use BSR and ‘a=1’ bit in instructions with INDFx.
 MOVFF and banks

• The MOVFF instruction is that there is no need

to worry about bank switching because it can
move data anywhere within the 4K of
RAM space
• The Absolute address (12 bits) of source and
destination are embedded in the instruction.
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