INTERFACING 8251

WITH 8086

z
z
CONTENTS AT A GLANCE

 8086 Trainer Board

 8251 (USART)

 Interfacing 8251 with 8085

 Pin Assignment with 8086

 Circuit Diagram to Interface 8251 with 8086

 Assembly program to interface 8251 with 8086

 z
8086 TRAINER BOARD

The MIC-8086 Development and Training System includes a target

board based on the 16-bit 8086 microprocessor. Designed as a
general purpose unit it simplifies the teaching of the 8086 CPU and
its commonly used peripherals. Suitable for use at all levels, from
simple programs flashing an LED to use as a controller in complex
projects. The MIC-8086 is used as a development system for 8086
Assembler Code programs, the EPROM based monitor providing a
user interface to a PC through its serial port. Assembler code
programs for the 8086 are constructed on the PC and downloaded
from the host in Intel Hex format. 
Programs can be entered into the integral WINDOWS based, LINE-
z
by-LINE assembler, disassembled and easily debugged with the
monitoring facilities. LINE assembled programs can also be saved
and re-loaded when required.

Standard connectors give full access to Data and Address buses so

that logic analyzers and other diagnostic equipment can be
connected easily for demonstration and debugging purposes.
All major components are retained in turned pin I/C sockets this
enables faults to be easily applied without fear of damage to the
target board for the teaching of fault finding techniques. The
teaching of Logic and Signature Analysis and In-Circuit Emulation
techniques is enhanced because the board may be set up for a
realistic dedicated application
 z
8251 (USART)

8251 USART is a universal synchronous and asynchronous controller

designed by Intel basically to facilitate
communication. USART stands for Universal Synchronous
and Asynchronous Receiver Transmitter and functions as an
intermediary that allows serial and parallel communication
between the microprocessor and the peripheral devices. We know
that microprocessors allow parallel communication. And in parallel
communication, the number of cables required for data
transmission is equal to the number of bits to be transmitted per
cycle. Thus the approach of transmitting data parallelly to long
distance is cost-ineffective. 
 z

 So, to reduce the overall cost of the system despite parallel data

communication between the processor and peripheral devices, the
serial transfer of data is permitted. Hence for this purpose, USART
acts as a mediator between the processor and peripheral devices
so, that the parallel data from the processor can be converted into
serial data and efficiently transferred to the peripheral devices. In a
similar way, the serial data from the peripheral devices is
converted by the USART into the parallel form so that it can be
accepted by the processor. Also, it allows both synchronous
and asynchronous transmission and reception thus is called so.
 z
INTERFACING 8251 WITH 8085

Now let us see how 8251 can be interfaced with 8085. In the
diagram, we can see that eight data lines D7-0 are connected to the
data bus of the microprocessor. And also the RD and WR of the 8251
are also connected with the RD and RD of 8051. The 8251 is getting
the clock from the CLK OUT pin of 8085. And the RESET is also
connected to the RESET OUT pin of the microprocessor.
 z

The C/D  pin is used to select either control register or data register.

This pin is connected to the A0 pin of 8085. The CS pin of 8251 is
attached to the output of an address decoder circuit. The address
decoder uses A7 to A1 lines of the microprocessor. In this diagram
the CS will be enabled when A7 and A4 is at logic 1, and all other
lines are at logic 0.
z
z

A0 RD WR Task Port
Address

0 0 1 Read Data Word 90H

0 1 0 Write Data Word 90H

1 0 1 Read Status Word 91H

1 1 0 Write Control Word 91H

z
PIN ASSIGNMENT WITH 8086
 z
CIRCUIT DIAGRAM TO INTERFACE
8251 WITH 8086

 The chip select for I/O mapped devices are generated by using a
3-to-8 decoder.

 The address lines A5, A6 and A7 are decoded to generate eight

chip select signals (IOCS-0 to IOCS-7) and in this, the chip select
signal IOCS-2 is used to select 825lA.

 The address line A0 and the control signal M/IO(low) are used as
enable for decoder.
 The linez A1 of 8086 is connected to C/D(low) of 8251A to provide
the internal addresses.

 The lines D0 – D7 connected to D0 – D7 of the processor to

achieve parallel data transfer.

 The RESET and clock signals are supplied by 8284 clock

generator. Here the processor clock is directly connected to 8251A.
This clock controls the parallel data transfer between the processor
and 825lA.

 8251A in I/O mapped in the system is shown in the figure.

z
 The peripheral
z clock (PCLK) supplied by 8284, is divided by
suitable clock dividers like programmable timer 8254 and then
used as clock for serial transmission and reception.

 In 8251A the transmission and reception baud rates can be

different or same.

 The TTL logic levels of the serial data lines and the control signals
necessary for serial transmission and reception are converted to
RS232 logic levels using MAX232 and then terminated on a
standard 9-pin D-.type connector.

 The device, which requires serial communication with processor,

can be connected to this 9-pin D-type connector using 9-core
cable.
 The signals TxEMPTY, TxRDY and RxRDY can be used as
interrupt
z signals to initiate interrupt driven data transfer scheme

between processor and 8251 A.

 The I/O addresses allotted to the internal devices of 8251A are

listed in table.
z

THANK YOU