GLA UNIVERSITY Mathura, Uttar Pradesh, India

Interfacing I/O Devices

• Using I/O devices data can be transferred between
the microprocessor and the outside world.

• This can be done in groups of 8 bits using the entire

data bus. This is called parallel I/O.

• The other method is serial I/O where one bit is

transferred at a time using the SI and SO pins on the
Microprocessor.
 I/O devices

 For communication between microprocessor and outside world

 Keyboards, CRT displays, Printers, Compact Discs etc.

 Data transfer types

Ports / Buffer IC’s

Microprocessor I/ O devices
(interface circuitry)

Programmed I/ O Memory mapped

Data transfer is accomplished through an
I/O port controlled by software I/O mapped

Interrupt driven I/ O
I/O device interrupts the processor and initiate
data transfer
Direct memory access
Data transfer is achieved by bypassing the
microprocessor

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 Dealing with I/O Devices

There are two ways to deal with I/O devices.

• Consider them like any other memory location:

They are assigned a 16-bit address within the address range of the 8085.
The exchange of data with these devices follows the transfer of data with memory. The user uses
the same instructions used for memory.
This is called memory-mapped I/O.

• Treat them separately from memory:

I/O devices are assigned a “port number” within the 8-bit address range of 00H to FFH.
The user in this case would access these devices using the IN and OUT instructions only.
This is called I/O-mapped I/O or Peripheral-mapped I/O.

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 Memory mapping
16 bit memory address are provided for I/O
devices
The I/O ports or peripherals can be treated like
memory locations and so all instructions
related to memory can be used for data
transmission between I/O device and processor
Data can be moved from any register to ports
and vice versa
When memory mapping is used for I/O
devices, full memory address space cannot be
used for addressing memory.
 Useful only for small systems where
memory requirement is less
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I/O mapping
8-bit I/O port address is provided for I/O
devices
Only IN and OUT instructions can be used for
data transfer between I/O device and processor
Data transfer takes place only between
accumulator and ports
Full memory space can be used for addressing
memory.
 Suitable for systems which require large
memory capacity
DMA Controller 8237/57
CPU having the control over the bus:
When DMA operates:
 8237 Modes
The 8257 processor works on two modes:

1) Master mode;

2) Slave mode;

An active-low input which enables the I/O Read or I/O Write input when the 8237 is
being read or programmed in the "slave" mode.

In the "master" mode. CS is automatically disabled to prevent the chip from selecting
itself while performing the DMA function.

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 DMA Controller 8237
The Intel 8237 is a 4-channel Direct Memory Access (DMA) controller. It is specifically
designed to simplify the transfer of data at high speeds for the Intel® microcomputer
systems. Its primary function is to generate, upon a peripheral request, a sequential
memory address which will allow the peripheral to read or write data directly to or from
memory. Acquisition of the system bus in accomplished via the CPU's hold function.

The 8257 has priority logic that resolves the peripherals requests and issues a
composite hold request to the CPU. It maintains the OMA cycle count for each channel
and outputs a control signal Jo notify the peripheral that the programmed number of
OMA cycles is complete. Other output control signals simplify sectored data transfers.
The 8237 represents a significant savings in component count for DMA-based
microcomputer systems and greatly simplifies the transfer of data at high speed
between peripherals and memories.
Functional Block Diagram of 8237:

The functional blocks of 8237 are data bus buffer, read/write logic, control
logic, priority resolver and four numbers of DMA channels.
Each channel has two programmable 16-bit registers named as address
register and count register.

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 Block diagram
The 8257 is a programmable. Direct Memory Access (DMA) device which, when coupled with a single Intel®
8212 I/O port device, provides a complete four-channels DMA controller for use in Intel® microcomputer
systems. After being initialized by software, the 8237 could transfer a block of data, containing up to 16.384
bytes, between memory and a peripheral device directly, without further intervention required of the CPU.
Upon receiving a DMA transfer request from an enabled peripheral, the 8257:

1. Acquires control of the system bus.

2. Acknowledges that requesting peripheral which is connected to the highest priority channel.
3. Outputs the least significant eight bits of the memory address onto system address lines A0-A7. outputs
the most significant eight bits of the memory address to the 8212 I/O port via.the data bus (the 8212 places
these address bits on lines A8-A15), and
4. Generates the appropriate memory and I/O read/ write control signals that cause the peripheral to
receive or deposit a data byte directly from or to the addressed location in memory.
Programmable DMA controller
Primary function: a sequential memory access which allow the peripheral to read or write
data directly to or from memory
Has 4 independent channels each capable of transferring 64Kbytes of data
Must be interfaced with MPU and peripherals

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Programmable DMA controller. (a) Block diagram and (b) pin-out.

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 8237 – Block Diagram
1. DMA Channels

2. Data Bus Buffer

3. Read/Write Logic

4. Control Logic
 1. DMA Channels
# Four separate DMA channels (CH-0 to CH-3)

# Each channel includes two 16 bit registers

1. DMA address register

2. Terminal count register

# 14 bit count (N-1) is loaded into TC reg

2 msb’s give the type of DMA operation

# Signals DRQ0 to DRQ3, to

 Type of DMA Operation
Bit 15 Bit 14 Type of DMA Operation
0 0 Verify DMA Cycle
0 1 Write DMA Cycle
1 0 Read DMA Cycle
1 1 (Illegal)
 2. Data Bus Buffer

This is tristate bi-directional, eight bit buffer interfaces

the 8257 to the system data bus

D0 – D 7
 3.
#A –A
Read/Write Logic
0 3

# IOR, IOW

Input signals in slave mode

Output signals in master mode

# RESET

#CLK

# CS
 4. Control Logic
# ADSTB (Address Strobe):

This output strobes the most significant byte of the

memory address into the device from the data bus

# AEN (Address Enable):

Used to disable the system buses

# TC (Terminal Count)

# MARK (Modulo 128 Mark)

 DMA Execution: Slave
Mode
1. # MPU unit selects the DMA Controller through CS

2. # MPU writes control register

Note:- In slave mode, IOR and IOW of 8237 are input

signals and MEMR and MEMW are tri-stated.
DMA Execution: Master Mode
1. # Peripherals sends DRQ

2. # If Channel is enabled, ctrl logic sends HRQ

3. # MPU relinquishes buses and sends HLDA

4. # Controller asserts AEN high.

Places high order address on its data bus and low

order address on its address bus.

Then asserts ADSTB high which places high address

on A15 – A8
 DMA Execution: Master
Mode
5. # Once address is kept on bus, DMA sends DACK

6. # DMA controller continues data transfer

7. # At the end of data transfer, DMA sends TC to

peripheral

8. # DMA makes HRQ low

Pin diagram 8257

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DRQ0−DRQ3

These are the four individual channel DMA request

inputs, which are used by the peripheral devices for
using DMA services. When the fixed priority mode is
selected, then DRQ0 has the highest priority and DRQ3
has the lowest priority among them.

DACKo − DACK3

These are the active-low DMA acknowledge lines,

which updates the requesting peripheral about the status
of their request by the CPU. These lines can also act as
strobe lines for the requesting devices.
Do − D 7

These are bidirectional, data lines which are used to

interface the system bus with the internal data bus of
DMA controller. In the Slave mode, it carries command
words to 8237 and status word from 8237. In the master
mode, these lines are used to send higher byte of the
generated address to the latch. This address is further
latched using ADSTB signal.
IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to

read internal registers of 8257 in the Slave mode. In the master mode, it is used to
read data from the peripheral devices during a memory write cycle.

IOW

It is an active low bi-direction tri-state line, which is used to load the contents of
the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA
address register or terminal count register. In the master mode, it is used to load
the data to the peripheral devices during DMA memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA
channels.
Ao - A3

These are the four least significant address lines. In the slave
mode, they act as an input, which selects one of the registers to
be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables

the read/write operations to/from 8257. In the master mode, it
disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated
by DMA in the master mode.
READY

It is an active-high asynchronous input signal, which makes DMA ready by

inserting wait states.

HRQ

This signal is used to receive the hold request signal from the output device.
In the slave mode, it is connected with a DRQ input line 8257. In Master
mode, it is connected with HOLD input of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller

that the bus has been granted to the requesting peripheral by the CPU when
it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the
addressed memory locations during DMA read cycles.
MEMW

It is the active-low three state signal which is used to write the data
to the addressed memory location during DMA write operation.

ADST

This signal is used to convert the higher byte of the memory

address generated by the DMA controller into the latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA

cycle to the present peripheral devices.
MARK

The mark will be activated after each 128 cycles or

integral multiples of it from the beginning. It indicates
the current DMA cycle is the 128th cycle since the
previous MARK output to the selected peripheral
device.

Vcc

It is the power signal which is required for the operation

of the circuit.
Thank you!

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