VLSI Design

Circuits & Layout

Outline

 CMOS Gate Design

 Pass Transistors
 CMOS Latches & Flip-Flops
 Standard Cell Layouts
 Stick Diagrams
CMOS Gate Design
 A 4-input CMOS NOR gate

A
B
C
D
Y
Complementary CMOS
 Complementary CMOS logic gates
 nMOS pull-down network
 pMOS pull-up network pMOS
pull-up
network
 a.k.a. static CMOS
inputs
output

nMOS
pull-down
network

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)
 Series and Parallel
a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

 nMOS: 1 = ON a
0
a
0
a
1
a
1
a

g1

 pMOS: 0 = ON g2
b
0
b
1
b
0
b
1
b
(b) ON OFF OFF OFF
 Series: both must be ON
a a a a a
 Parallel: either can be ON g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
 Conduction Complement
 Complementary CMOS gates always produce 0 or 1

 Ex: NAND gate

 Series nMOS: Y=0 when both inputs are 1
 Thus Y=1 when either input is 0
 Requires parallel pMOS Y
A
B
 Rule of Conduction Complements
 Pull-up network is complement of pull-down
 Parallel -> series, series -> parallel
Compound Gates
 Compound gates can do any inverting function
 Ex: AND-AND-OR-INV (AOI22) Y  ( A  B )  (C  D)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
Example: O3AI

Y  ( A  B  C)  D
Example: O3AI

Y  ( A  B  C)  D

A
B
C D
Y
D
A B C
Pass Transistors
 Transistors can be used as switches
g

s d

s d
Pass Transistors
 Transistors can be used as switches
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
Signal Strength
 Strength of signal
 How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
 But degraded or weak 1
 pMOS pass strong 1
 But degraded or weak 0
 Thus NMOS are best for pull-down network
 Thus PMOS are best for pull-up network
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb
Tristates
 Tristate buffer produces Z when not enabled

EN

EN A Y A Y
0 0 Z
0 1 Z EN
1 0 0
1 1 1 A Y

EN
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
 Only two transistors
 But nonrestoring
 Noise on A is passed on to Y (after several stages, the

noise may degrade the signal beyond recognition)

EN

A Y

EN
Tristate Inverter
 Tristate inverter produces restored output
 Note however that the Tristate buffer
 ignores the conduction complement rule because we want a
Z output

A
EN
Y
EN
Tristate Inverter
 Tristate inverter produces restored output
 Note however that the Tristate buffer
 ignores the conduction complement rule because we want a
Z output

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A
Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 D0 0
0 X 1 Y
D1 1
1 0 X
1 1 X
Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed?
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed? 20
D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates
 Only 4 transistors
S

D0
S Y
D1

S
 Inverting Mux
 Inverting multiplexer
 Use compound AOI22
 Or pair of tristate inverters
 Essentially the same thing
 Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two
selects
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two
selects
 Two levels of 2:1 muxes
 Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3
D Latch
 When CLK = 1, latch is transparent
 Q follows D (a buffer with a Delay)
 When CLK = 0, the latch is opaque
 Q holds its last value independent of D

 a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q
 D Latch Design
 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

Old Q
CLK
D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

Q
 D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
CLK
CLK
D
Flop

D Q
Q
 D Flip-flop Design
 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

A “negative level-sensitive” latch A “positive level-sensitive” latch

D Flip-flop Operation
Inverted version of D

QM Q
D

CLK = 0

Holds the last value of NOT(D)

QM
D Q

Q -> NOT(NOT(QM))
CLK = 1

CLK

Q
Race Condition
 Back-to-back flops can
malfunction from clock skew
 Second flip-flop fires Early
 Sees first flip-flop change
and captures its result
 Called hold-time failure or
race condition
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
 As long as nonoverlap exceeds clock skew
 Good for safe design
 Industry manages skew more carefully instead

2 1
QM
D Q

2 2 1 1

2 1

1

2
Gate Layout
 Layout can be very time consuming
 Design gates to fit together nicely
 Build a library of standard cells
 Must follow a technology rule

 Standard cell design methodology

 VDD and GND should abut (standard height)
 Adjacent gates should satisfy design rules
 nMOS at bottom and pMOS at top
 All gates include well and substrate contacts
Example: Inverter
 Layout using Electric

Inverter, contd..
Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 
NAND3 (using Electric), contd.
Stick Diagrams
 Stick diagrams help plan layout quickly
 Need not be to scale
 Draw with color pencils or dry-erase markers
Stick Diagrams
 Stick diagrams help plan layout quickly
 Need not be to scale
 Draw with color pencils or dry-erase markers

VDD

Vin
Vout

GND
Wiring Tracks
 A wiring track is the space required for a wire
 4  width, 4  spacing from neighbor = 8 
pitch
 Transistors also consume one wiring track
Well spacing
 Wells must surround transistors by 6 
 Implies 12  between opposite transistor flavors
 Leaves room for one wire track
Area Estimation
 Estimate area by counting wiring tracks
 Multiply by 8 to express in 
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area


Y  ( A  B  C)  D
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
 Y  ( A  B  C)  D
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
 Y  ( A  B  C)  D