BASIC CMOS CIRCUITS

Dr. Zakir Ali,

Asstt. Prof .
Deptt. OF ECE.
Email : zakirali008@gmail.com

06/04/2020 CMOS Circuits Lect-6,

 MOS Inverter : Static Characteristics

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Introduction
• Inverter is fundamental logic gate uses single input.

• Basic principles employing in design and analysis of

inverter can be directly applied on complex gates.

• Therefore inverter design forms basis for digital circuits.

• First we start with DC Characteristics.

What do you understand by DC response of the

circuit?

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Introduction (contd.)
The DC response is Ultra Low Frequency response of the
Circuit.
– When you are at a logic low or high before switching it
is a DC condition.

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Actual Inverter Characteristics

General Model of inverter

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Noise Immunity and Noise Margins

• Output signal is transmitted through interconnect to next inverter.

• Interconnects are prone to noise. Suppose output of 1st inverter is
perturbed, and its level is higher than VIL than it can not be correctly
predicted at output of 2nd inverter.
• Thus VIL is max allowable input voltage which is low enough to ensure
‘1’ output.
• Similarly VIH is minimum allowable input voltage which is high enough
to ensure ‘0’ output.
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Noise Immunity and Noise Margins

• Noise tolerance also called Noise Margins and denoted by NM. Two
noise margins will be defined : for low signal level as NML and high
signal level as NMH as

• Justification for VIL and VIH

Vout  f (Vin ); Vout
'
 f (Vin  Vnoise )
dVout
V '
out  f (vin )  Vnoise
dVin
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Critical Parameters for Inverter design

• There are five critical voltage points
determine DC Characteristics and Noise
margins :

• VIL.
• VIH.
• VOL.
• VOH.
• VTH.

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CMOS INVERTER

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Region of operation:

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VTC Characteristic

A : P Lin N Off
B : P Lin N Sat
C : P sat N Sat
D : P Sat N Lin
E : P off N Lin

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If KR = 1 Then
 

Ideal Logic threshold

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value.
CMOS Circuits Lect-6,
 

06/04/2020 CMOS Circuits Lect-6,

 

Depletion-load NMOS Inverter

06/04/2020 CMOS Circuits Lect-6,

 

Depletion-load NMOS Inverter

06/04/2020 CMOS Circuits Lect-6,

 

Depletion-load NMOS Inverter

06/04/2020 CMOS Circuits Lect-6,

 

Depletion-load NMOS Inverter

06/04/2020 CMOS Circuits Lect-6,

 

Depletion-load NMOS Inverter

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Depletion-load NMOS Inverter

• Rough Calculation : Vto,D=1.0, VOH=VDD=5V,

Vtn,L=-3.5V, and (W/L)D=(W/L)L

Find VOL=?? Answer ≈ 1.53V.

• If its value is more than 1V, then low output is
high enough. This tells both Driver and Load can
not be of same size.

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Depletion-load NMOS Inverter

Calculation of logic threshold : both the transistors are

in saturation. Equate saturation current equations by
putting Vin = vout = Vth. Expression for Vth is
Vt , L (W / L) D
Vth  Vto , D  ; k
k (W / L) L
• Rough Calculation : Vto,D=1.0, Vtn,L=-3.5V, and
(W/L)D=(W/L)L=1,
• Value of Vth=4.5V.which is again not correct.
• Do the back calculation, find value of k by putting Vth=
VDD/2.
3.5
2.5  1  ; k  4; with k  4, VoL  0.29V
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Depletion-load NMOS Inverter

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Next Topic

MOS Inverter : Dynamic Characteristics

06/04/2020 CMOS Circuits Lect-6,