The Real Time Clock (RTC) is a set of counters for measuring time when

system power is on, and optionally when it is off.

It uses little power in Power-down mode. On the LPC2141/2/4/6/8, the

RTC can be clocked by a separate 32.768 KHz oscillator, or by a
programmable prescale divider based on the VPB clock.

The RTC is powered by its own power supply pin, VBAT, which can be
connected to a battery or to the same 3.3 V supply used by the rest of the
device.
FEATURES OF RTC:
Measures the passage of time to maintain a calendar and
clock.
 Ultra Low Power design to support battery powered
systems.
Provides Seconds, Minutes, Hours, Day of Month, Month,
Year, Day of Week, and Day of Year.
Dedicated 32 kHz oscillator or programmable prescaler
from VPB clock.
Dedicated power supply pin can be connected to a
battery or to the main 3.3 V.
REGISTERS IN RTC (32BIT REGISTERS) :
REGISTERS CLASSIFICATION:
The RTC includes a number of registers. The address
space is split into four sections by functionality.
The first eight addresses are the Miscellaneous
Register Group.
The second set of eight locations are the Time
Counter Group.
The third set of eight locations contain the Alarm
Register Group.
The remaining registers control the Reference Clock
Divider.
MISCELLANEOUS REGISTER GROUP
 INTERRUPT LOCATION REGISTER (ILR ):

The Interrupt Location Register is a 2-bits (used)register that

specifies which blocks are generating an interrupt . Writing a
one to the appropriate bit clears the corresponding interrupt.
Writing a zero has no effect. This allows the programmer to
read this register and write back the same value to clear only
the interrupt that is detected by the read.
CLOCK TICK COUNTER REGISTER (CTCR)
The Clock Tick Counter is read only. It can be reset to
zero through the Clock Control Register (CCR). The
CTC consists of the bits of the clock divider counter.
CLOCK CONTROL REGISTER (CCR ) :

The clock register is a 5-bit register that controls the

operation of the clock divide circuit.
COUNTER INCREMENT INTERRUPT REGISTER (CIIR ) :
The Counter Increment Interrupt Register (CIIR) gives
the ability to generate an interrupt every time a counter
is incremented. This interrupt remains valid until
cleared by writing a one to bit zero of the Interrupt
Location Register (ILR[0]).
ALARM MASK REGISTER (AMR ) :
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
For the alarm function, every non-masked alarm register must match the
corresponding time counter for an interrupt to be generated. The interrupt is
generated only when the counter comparison first changes from no match to
match. The interrupt is removed when a one is written to the appropriate bit of the
Interrupt Location Register (ILR). If all mask bits are set, then the alarm is disabled.
 CONSOLIDATED TIME REGISTER 0 (CTIME0) :
The values of the Time Counters can optionally be read
in a consolidated format which allows the programmer to
read all time counters with only three read operations.
The various registers are packed into 32-bit values The
least significant bit of each register is read back at bit 0, 8,
16, or 24.
The Consolidated Time Registers are read only.
 To write new values to the Time Counters, the Time
Counter addresses should be used.
 The Consolidated Time Register 0 contains the low order
time values: Seconds,Minutes,Hours, and Day of Week.
CONSOLIDATED TIME REGISTER 1 (CTIME1) :
The Consolidate Time register 1 contains the Day of
Month, Month, and Year values.
CONSOLIDATED TIME REGISTER 2 (CTIME2 ) :
The Consolidate Time register 2 contains just the Day
of Year value.
 TIME COUNTER GROUP :
The time value consists of the following eight counters and
these counters can be read or written at the locations as
shown below.
These values are simply incremented at the appropriate
intervals and reset at the defined overflow point.
They are not calculated and must be correctly
initialized in order to be meaningful.
ALARM REGISTER GROUP :
The alarm registers are shown below, the values in these
registers are compared with the time counters.
Alarm registers match their corresponding time counters
then an interrupt is generated. The interrupt is cleared
when a one is written to bit one of the Interrupt Location
Register (ILR[1]).
REFERENCE CLOCK DIVIDER (PRESCALER) :
The reference clock divider (prescaler) allows generation
of a 32.768 kHz reference clock from any peripheral clock
frequency greater than or equal to 65.536 kHz (2 × 32.768
kHz). This permits the RTC to always run at the proper
rate regardless of the peripheral clock rate. Basically, the
Prescaler divides the peripheral clock (PCLK) by a value
which contains both an integer portion and a fractional
portion.The result is not a continuous output at a
constant frequency, some clock periods will be one PCLK
longer than others.overall result can always be 32,768
counts per second.
 The reference clock divider consists of a 13-bit integer counter and a 15-bit
fractional counter.

PRESCALER INTEGER REGISTER (PREINT ) :

This is the integer portion of the prescale value, calculated as:
PREINT = int (PCLK / 32768) − 1.
The value of PREINT must be greater than or equal to 1.
PRESCALER FRACTION REGISTER (PREFRAC) :
This is the fractional portion of the prescale value,
and may be calculated as:
PREFRAC = PCLK − ((PREINT + 1) × 32768).