The document describes the design of a 3-8 decoder circuit using VHDL, including different methods to implement the circuit using constructs like if/elseif, case, with/select, and for loops. It also discusses defining packages and subprograms in VHDL to reuse common components like a color mixing procedure and function.
The document describes the design of a 3-8 decoder circuit using VHDL, including different methods to implement the circuit using constructs like if/elseif, case, with/select, and for loops. It also discusses defining packages and subprograms in VHDL to reuse common components like a color mixing procedure and function.
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The document describes the design of a 3-8 decoder circuit using VHDL, including different methods to implement the circuit using constructs like if/elseif, case, with/select, and for loops. It also discusses defining packages and subprograms in VHDL to reuse common components like a color mixing procedure and function.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online from Scribd
THIẾT KẾ SỐ BẰNG NGÔN NGỮ MÔ TẢ PHẦN CỨNG - VHDL DANH SÁCH NHÓM :
• NGUYỄN VĂN THỨC
• NGUYỄN HỒNG LÂM • NGUYỄN VĂN QUYỀN • BÙI XUÂN ANH • BÙI DANH HOÀNG • PHẠM GIA THỤ • VŨ ĐÌNH VINH • ĐÀO ĐÌNH XUÂN MẠCH GIẢI MÃ 3-8 • -- LED 7 THANH • library IEEE; • use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_STD.all; • entity led72 is • Port ( I : in STD_LOGIC_VECTOR (3 downto 0); • Y : out std_logic_vector(6 downto 0)); • end led72 ; • architecture LOGIC of led72 is • begin • PROCESS (I) MẠCH GIẢI MÃ 3-8 • BEGIN • CASE I is • when "0001" => Y <= "1000000"; -- so 0 • when "0011" => Y <= "1111001"; -- so 1 • when "0101" => Y <= "0100100"; -- so 2 • when "0111" => Y <= "0110000"; -- so 3 • when "1001" => Y <= "0011001"; -- so 4 • when "1011" => Y <= "0000000"; -- so 5 • when "1101" => Y <= "0010000"; -- so 6 • when "1111" => Y <= "0010000"; -- so 7 • when others => Y <= "1111111"; -- tat • END CASE; • END PROCESS; • end architecture LOGIC; MÔ PHỎNG CHƯƠNG TRÌNH • D:\TAI LIEU\VHDL\THUC HANH\led72\led 72.qpf • D:\TAI LIEU\VHDL\THUC HANH\led72\led 72.vwf MẠCH GIẢI MÃ 3-8 • -- MACH GIAI MA 3_8 DUNG LENH “elsif" • library IEEE; • use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; • entity mahoa3_8 is • port (A: in integer range 0 to 7); • Y: out unsigned (7 downto 0)); • end entity mahoa3_8; • architecture LOGIC of mahoa3_8 is • begin • process (A) MẠCH GIẢI MÃ 3-8 • begin • if(A=0) then Y<= " 00000001"; • elsif(A=1) then Y<= " 00000010"; • elsif(A=2) then Y<= "00000100"; • elsif(A=3) then Y<= "00001000"; • elsif(A=4) then Y<= "00010000"; • elsif(A=5) then Y<= "00100000"; • elsif(A=6) then Y<= "01000000"; • elsif Y<= "10000000"; • end if; • end process; • end architecture LOGIC; MẠCH GIẢI MÃ 3-8 • -- MACH GIAI MA 3_8 DUNG LENH “CASE " • library IEEE; • use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; • entity mahoa3_8 is • port (A: in integer range 0 to 7); • Y: out unsigned (7 downto 0)); • end entity mahoa3_8; • architecture LOGIC of mahoa3_8 is • begin • process (A) • begin MẠCH GIẢI MÃ 3-8 • case A is • when 0 => Y<="00000001"; • when 1 => Y<="00000010"; • when 2 => Y<="00000100"; • when 3 => Y<="00001000"; • when 4 => Y<="00010000"; • when 5 => Y<="00100000"; • when 6 => Y<="01000000"; • when 7 => Y<="10000000"; • end case; • end process; • end architecture LOGIC ; MẠCH GIẢI MÃ 3-8 • -- MACH GIAI MA 3_8 DUNG “WITH A SELECT” • library IEEE; • use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; • entity mahoa3_8 is • port (A: in integer range 0 to 7); • Y: out unsigned (7 downto 0)); • end entity mahoa3_8; • architecture LOGIC of mahoa3_8 is • begin • process (A) • begin • with A select MẠCH GIẢI MÃ 3-8 • Y<="00000001" when 0, • "00000010" when 1, • "00000100" when 2, • "00001000" when 3, • "00010000" when 4, • "00100000" when 5, • "01000000" when 6, • "10000000" when 7, • "00000000" when others; • end with; • end process; • end architecture LOGIC; MẠCH GIẢI MÃ 3-8 • -- MACH GIAI MA 3_8 DUNG “FOR” • library IEEE; • use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; • entity mahoa3_8 is • port (A: in integer range 0 to 7); • Y: out unsigned (7 downto 0)); • end entity mahoa3_8; • architecture LOGIC of mahoa3_8 is • begin • process (A) MẠCH GIẢI MÃ 3-8 • begin • for N 0 to 7 loop • if ( A =N) then • Y(N) = "1"; • else • Y(N)="0"; • end if; • end loop; • end process; • end architecture LOGIC; MẠCH GIẢI MÃ 3-8 • -- MACH GIAI MA 3_8 DUNG “ if ” • library IEEE; • use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; • entity mahoa3_8 is • port (A: in integer range 0 to 7); • Y: out unsigned (7 downto 0)); • end entity mahoa3_8; • architecture LOGIC of mahoa3_8 is • begin • process (A) MẠCH GIẢI MÃ 3-8 • begin • Y<= ( others =>"0"); • if (A = N ) then • Y(N)<= "1"; • exit; • else • Y(N)<= "0"; • end if; • end lopp; • end process; • end architecture LOGIC; CHƯƠNG TRÌNH CON • -- CAC CHUONG TRINH CON DINH NGHIA ; • --TREN TAP TIN HE THONG RIENG BIET ; • Library IEEE; • use Library IEEE.STD_LOGIC_1164.all,IEEE.Numeric_STD.all; • package COLOR_TYPES is • type pigmentcolorprime is ( red,yellow,Blue ); • type pigmentcolorsec is ( Orange, violet,green); • end package COLOR_TYPES ; CHƯƠNG TRÌNH CON • use work.COLOR_TYPES.all; • package SUBPROGS is • procedure Mixcolor • ( signal C1,C2: in pigmentcolorPrime; • signal Mix : out pigmentcolorPrime); • function Mixcolor (C1,C2: pigmentPrime); • return pigmentseccolor; • end package SUBPROGS; • package body SUBPROGS is • procedure Mixcolor • ( signal C1,C2: in pigmentcolorPrime; • signal Mix : out pigmentcolorsec) is CHƯƠNG TRÌNH CON • begin • if ( C1= red and C2= yellow ) then • Mix<= Orange; • elsif (C1= red and C2= lue) then • Mix<= violet; • else • (C1= yellow and C2= Blue) • mix<= Green; • end if; • end procedure Mixcolor; • function Mixcolor (C1,C2:pigmentcolorPrime) • return pigmentcolorsec is • variable Mix: Pigmentcolorsec; CHƯƠNG TRÌNH CON • begin • if(C1=red and C2=yellow) then • Mix:=violet; • else • (C1= yellow and C2=Blue ) then • Mix:= Green; • end if ; • return Mix; • end functon Mixcolor; • end package body SUBPROGS;