VLSI Design

(MEL G621)

Lecture 2: Understanding
I-V Characteristics for
MOS

EEE & ECE Department

BITS-Pilani, Hyderabad campus

November 23, 2021 VLSI Design 1

 Scopes & Objectives

Understanding Drain-to-Source
Current versus Voltage
relationships

November 23, 2021 VLSI Design 2

 I-V Relationship of MOS
• The drain side is more reverse biased than the
source side

• Depletion region will extend more on the

drain side than the source side

• The charge/area may be written as a function

of VT

November 23, 2021 VLSI Design 3

 I-V Relationship of MOS
W V 2

I  C [(V  V )V  ] DS

L 2
d ox GS T DS

• Device transconductance and process

transconductance

• Pinch-off voltage

• Saturation current
November 23, 2021 VLSI Design 4
 Non-ideal Effects

• Channel length modulation

• Voltage controlled resistor

• Voltage controlled current source

November 23, 2021 VLSI Design 5

 Deep Sub-micron Devices
• As L decreases, E becomes large and it
H

interacts with E V

• Saturation does not occur due to pinch-off but

due to velocity saturation
• I-V Characteistic is more linear than quadratic
• Saturation voltage is smaller than the
predicted value
• Subthreshold current

November 23, 2021 VLSI Design 6