Hardware-Based Speculation Techniques for Instruction Level Parallelism

CKV
Advanced VLSI Architecture

MEL G624
Lecture 20: Instruction Level Parallelism

CKV
Hardware-Based Speculation
A wide issue processor may execute a branch every clock cycle to
maintain maximum performance
Exploiting more parallelism requires that we overcome the limitation

of control dependence
Done by speculating the outcome of the branches and executing the

program as if our guesses were correct.
Mechanisms to handle situations where speculation is incorrect
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Dynamic branch prediction to choose which instructions to execute
Speculation to allow execution of instructions before control

dependences are resolved (with ability to undo the effects of an
incorrectly speculated sequence)
Dynamic scheduling to deal with scheduling of different combinations

of basic blocks
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To Support Tomasulo’s algorithm to support speculation
Separate bypassing of results from the actual completion of Instruction
Speculative Register Read Instruction no longer Speculative
Allow Register Write
Instruction Commit
Issue in order, execute out-of-order, commit in-order
Reorder Buffer
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Tomasulo’s Algorithm
Issue
Get the next instruction from the head of the instruction queue,
which is maintained in FIFO order
Issue the instruction if there is an empty reservation station and an

empty slot in the ROB;
Send the operands to the reservation station if they are available in

either the registers or ROB
Update the control entries to indicate ROB use; ROB entry allocated
for the result is also sent to the reservation station,
Stall if ROB is full or if reservation stations are full

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Execute
If one or more of the operands is not yet available, monitor the

common data bus while waiting for it to be computed.
When an operand becomes available, it is placed into any reservation

station awaiting it.
When all the operands are available, the operation can be executed at
the corresponding functional unit.
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Write Result
When the result is available, write it on the CDB and from there into
the ROB and into any reservation stations (including store buffers)
waiting for this result.
If the value to be stored is available, it is written into the Value field of

the ROB entry for the store.
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Commit
There are three different sequences of actions at commit depending
on whether
the committing instruction is a branch with an incorrect prediction,
It indicates that the speculation was wrong. The ROB is flushed and
execution is restarted at the correct successor of the branch.
store
when an instruction reaches the head of the ROB, update memory and
remove instruction from ROB
any other instruction (Normal commit)

when an instruction reaches the head of the ROB, update register file
and remove instruction from ROB
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Instruction Status
Instruction j k Issue Execution Write Result Commit
L.D F6, 34 (R2)
L.D F2, 45 (R3)
MUL.D F0, F2, F4
SUB.D F8, F6, F2
DIV.D F10, F0, F6
ADD.D F6, F8, F2
Reservation Stations Vk Qj
Busy Op Vj Qk A
Time Name
Load1
Load2
Add1
Add2
Add3
Mult1
Mult2
Register Status
F0 F2 F4 F6 F8 F10 F30
ROB No
Busy
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Reorder Buffer Status
Entry Busy Instruction State Destination Value

1
2
3
4
5
6
7
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ADD.D F6, F8, F2

ROB FP Registers
DIV.D F10, F0, F6 Qi
SUB.D F8, F6, F2 F0
Reg #
MUL.D F0, F2, F4 F2
L.D F2, 45 (R3)
F4
L.D F6, 34 (R2) Reg Data
F6
Address Unit F8
F10
Store Data Operand

Address Buses
Memory Unit
Reservation
Stations
FP Adders FP Multipliers
Common Data Bus (CDB)

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ADD.D F6, F8, F2

ROB FP Registers
SUB.D F8, F6, F2 F0
Reg #
MUL.D F0, F2, F4 F2
L.D F2, 45 (R3)
F4
F6
Address Unit F8
Load F10
Buffers
Store Data Operand
Load: 2 Cycles Buses
Address
Add: 2 Cycles
Memory Unit
Mul: 10 Cycles
Div: 40 Cycles
Reservation
Stations

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ADD.D F6, F8, F2

ROB FP Registers
SUB.D F8, F6, F2 1 F0
Reg #
MUL.D F0, F2, F4 2 F2
L.D F2, 45 (R3) 3 F4
4 F6
Address Unit 5 F8
Load 6 F10
Buffers
Store Data Operand
Address Buses
Memory Unit
Busy Op Vj Vk Qj Qk Busy Op Vj Vk Qj Qk
Reservation
Stations

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1 ADD.D F6, F8, F2
ROB FP Registers
SUB.D F8, F6, F2 1 LD F6 N F0
Reg #
MUL.D F0, F2, F4 2 F2
L.D F2, 45 (R3) 3 2.5 F4
IS L.D F6, 34 (R2) Reg Data
4 ROB1 F6
Address Unit 5 F8
Load 6 F10
Buffers
Store Data Operand
Address Buses
Memory Unit
Reservation
Stations

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1 ADD.D F6, F8, F2
ROB FP Registers
Reg #
MUL.D F0, F2, F4 2 F2
L.D F2, 45 (R3) 3 2.5 F4
IS L.D F6, 34 (R2) Reg Data
4 ROB1 F6
Address Unit 5 F8
Load 6 F10
Buffers
Store Data Operand
Address Buses
Memory Unit
Reservation
Stations

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2 ADD.D F6, F8, F2
ROB FP Registers
Reg #
MUL.D F0, F2, F4 2 LD F2 N ROB2 F2
IS L.D F2, 45 (R3) 3 2.5 F4
E L.D F6, 34 (R2) Reg Data
4 ROB1 F6
Address Unit 5 F8
6 F10
134 2
Store Data Operand

Address Buses
Memory Unit
Reservation
Stations

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2 ADD.D F6, F8, F2
ROB FP Registers
Reg #
IS L.D F2, 45 (R3) 3 2.5 F4
E L.D F6, 34 (R2) Reg Data
4 ROB1 F6
Address Unit 5 F8
6 F10
134 2
Store Data Operand

Address Buses
Memory Unit
Reservation
Stations

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3 ADD.D F6, F8, F2
ROB FP Registers
SUB.D F8, F6, F2 1 LD F6 N ROB3 F0
IS
Reg #
E L.D F2, 45 (R3) 3 ALU F0 2.5 F4
L.D F6, 34 (R2)
N
E Reg Data
4 ROB1 F6
Address Unit 5 F8
6 F10
134 1
245 2
Store Data Operand
Address Buses
Memory Unit
1 ML 2.5 ROB2
Reservation
Stations

CKV
4 ADD.D F6, F8, F2
ROB FP Registers
SUB.D F8, F6, F2 1 LD F6 N ROB3 F0
IS
Reg #
E L.D F2, 45 (R3) 3 ALU F0 2.5 F4
L.D F6, 34 (R2)
N
E Reg Data
4 ROB1 F6
Address Unit 5 F8
6 F10
134 0
245 1
Store Data Operand
Address Buses
Memory Unit
ROB1, 0.5 Busy Op Vj Vk Qj Qk Busy Op Vj Vk Qj Qk
1 ML 2.5 ROB2
Reservation
Stations

CKV
4 ADD.D F6, F8, F2
ROB FP Registers
SUB.D F8, F6, F2 1 LD F6 0.5 N
Y ROB3 F0
IS
Reg #
E L.D F2, 45 (R3) 3 ALU F0 2.5 F4
L.D F6, 34 (R2)
N
W Reg Data
4 ROB1 F6
Address Unit 5 F8
6 F10
245 1
Store Data Operand
Address Buses
Memory Unit
1 ML 2.5 ROB2
Reservation
Stations

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4 ADD.D F6, F8, F2
ROB FP Registers
IS SUB.D F8, F6, F2 1 LD F6 0.5 Y ROB3 F0
IS
Reg #
E L.D F2, 45 (R3) 3 ALU 2.5
F0 N F4
W L.D F6, 34 (R2) Reg Data
4 ALU F8 N ROB1 F6
Address Unit 5 ROB4 F8
6 F10
245 1
Store Data Operand
Address Buses
Memory Unit
1 Sub 0.5 ROB2 1 ML 2.5 ROB2
Reservation
Stations

CKV
5 ADD.D F6, F8, F2
ROB FP Registers
IS
Reg #
E L.D F2, 45 (R3) 3 ALU 2.5
F0 N F4
W L.D F6, 34 (R2) Reg Data
4 ALU F8 N ROB1 F6
6 F10
245 0
Store Data Operand
Address Buses
Memory Unit
1 Sub 0.5 ROB2 1 ML 2.5 ROB2
Reservation
Stations

CKV
5 ADD.D F6, F8, F2
ROB FP Registers
IS
Reg #
MUL.D F0, F2, F4 2 LD F2 1.5 N
Y ROB2 F2
W L.D F2, 45 (R3) 3 ALU 2.5
F0 N F4
C L.D F6, 34 (R2) Reg Data
4 ALU F8 N ROB1 0.5 F6
6 F10
ROB2, 1.5
245 0
Store Data Operand
Address Buses
Memory Unit
1 Sub 0.5 1.5 ROB2 1 ML 1.5 2.5 ROB2
Reservation
Stations

CKV
5 ADD.D F6, F8, F2
ROB FP Registers
IS DIV.D F10, F0, F6 Qi
IS SUB.D F8, F6, F2 1 ROB3 F0
IS
Reg #
MUL.D F0, F2, F4 2 LD F2 1.5 Y ROB2 F2
W L.D F2, 45 (R3) 3 ALU 2.5 F4
F0 N
C L.D F6, 34 (R2) Reg Data
4 ALU F8 N 0.5 F6
Address Unit 5 ALU F10 N ROB4 F8
6 ROB5 F10
Store Data Operand

Address Buses
Memory Unit
1 Sub 0.5 1.5 1 ML 1.5 2.5
1 Div 0.5 ROB3
Reservation
Stations

CKV
6
ROB FP Registers
IS ADD.D F6, F8, F2 Qi
IS DIV.D F10, F0, F6 1 ROB3 F0
E
IS
Reg #
SUB.D F8, F6, F2 2 LD F2 1.5 Y ROB2 1.5 F2
E
IS MUL.D F0, F2, F4 3 ALU F0 N 2.5 F4
C
W L.D F2, 45 (R3) Reg Data ROB6
4 ALU F8 N 0.5 F6
6 ALU F6 N ROB5 F10
Store Data Operand

Address Buses
Memory Unit
2 1 Sub 0.5 1.5 1 ML 1.5 2.5 10
1 Add 1.5 ROB4 1 Div 0.5 ROB3
Reservation
Stations

CKV
6
ROB FP Registers
IS ADD.D F6, F8, F2 Qi
IS DIV.D F10, F0, F6 1 ROB3 F0
E
IS
Reg #
SUB.D F8, F6, F2 2 1.5 F2
E
IS MUL.D F0, F2, F4 3 ALU F0 N 2.5 F4
C L.D F2, 45 (R3) Reg Data ROB6
4 ALU F8 N 0.5 F6
6 ALU F6 N ROB5 F10
Store Data Operand

Address Buses
Memory Unit
2 1 Sub 0.5 1.5 1 ML 1.5 2.5 10
Reservation
Stations

CKV
7
ROB FP Registers
Qi
IS ADD.D F6, F8, F2 1 ROB3 F0
IS
Reg #
DIV.D F10, F0, F6 2 1.5 F2
E
IS SUB.D F8, F6, F2 3 ALU F0 N 2.5 F4
E MUL.D F0, F2, F4 Reg Data ROB6
4 ALU F8 N 0.5 F6
6 ALU F6 N ROB5 F10
Store Data Operand

Address Buses
Memory Unit
1 1 Sub 0.5 1.5 1 ML 1.5 2.5 9
Reservation
Stations

CKV
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Hardware-Based Speculation Techniques for Instruction Level Parallelism

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CKV

Advanced VLSI Architecture

Lecture 20: Instruction Level Parallelism

Exploiting more parallelism requires that we overcome the limitation

Done by speculating the outcome of the branches and executing the

Mechanisms to handle situations where speculation is incorrect

Dynamic branch prediction to choose which instructions to execute

Speculation to allow execution of instructions before control

Dynamic scheduling to deal with scheduling of different combinations

Separate bypassing of results from the actual completion of Instruction

Speculative Register Read Instruction no longer Speculative

Allow Register Write

Issue in order, execute out-of-order, commit in-order

Issue the instruction if there is an empty reservation station and an

Send the operands to the reservation station if they are available in

Stall if ROB is full or if reservation stations are full

If one or more of the operands is not yet available, monitor the

When an operand becomes available, it is placed into any reservation

If the value to be stored is available, it is written into the Value field of

any other instruction (Normal commit)

Entry Busy Instruction State Destination Value

ADD.D F6, F8, F2

Store Data Operand

Common Data Bus (CDB)

ADD.D F6, F8, F2

Common Data Bus (CDB)

ADD.D F6, F8, F2

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Store Data Operand

Common Data Bus (CDB)

Store Data Operand

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Store Data Operand

Common Data Bus (CDB)

Store Data Operand

Common Data Bus (CDB)

Store Data Operand

Common Data Bus (CDB)

Store Data Operand

Common Data Bus (CDB)

Thank You for Attending

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