Lecture 18

CKV
Advanced VLSI Architecture

MEL G624
Lecture 18: Instruction Level Parallelism

CKV
Tomasulo’s Algorithm
Invented by Robert Tomasulo, used in IBM 360/91
Modified Algorithm
Register Renaming by reservation stations
Reservation station fetches and buffers an operand as soon as it is

available
CKV
Issue
Get the next instruction from the head of the instruction queue,
which is maintained in FIFO order
If there is a matching reservation station that is empty, issue the

instruction to the station with the operand values, if they are
currently in the registers.
If there is not an empty reservation station, then there is a structural

hazard and the instruction stalls
If the operands are not in the registers, keep track of the functional
units that will produce the operands.
CKV
Execute
If one or more of the operands is not yet available, monitor the

common data bus while waiting for it to be computed.
When an operand becomes available, it is placed into any reservation

station awaiting it.
When all the operands are available, the operation can be executed at
the corresponding functional unit.
To preserve exception behavior, no instruction is allowed to initiate

execution until all branches that precede the instruction in program
order have completed.
CKV
Write
When the result is available, write it on the CDB and from there into
the registers and into any reservation stations (including store buffers)
waiting for this result.
Stores are buffered in the store buffer until both the value to be
stored and the store address are available, then the result is written
as soon as the memory unit is free.
CKV
Instruction Status
Instruction j k Issue Execution Write Result
L.D F6, 34 (R2)
L.D F2, 45 (R3)
MUL.D F0, F2, F4
SUB.D F8, F6, F2
DIV.D F10, F0, F6
ADD.D F6, F8, F2
Reservation Stations Vk Qj
Busy Op Vj Qk A
Time Name
Load1
Load2
Add1
Add2
Add3
Mult1
Mult2
Register Status
F0 F2 F4 F6 F8 F10 F30
Qi
ADD.D F6, F8, F2 CKV
FP Registers
DIV.D F10, F0, F6
Instruction F0
SUB.D F8, F6, F2
Queue F2
MUL.D F0, F2, F4
L.D F2, 45 (R3) F4
L.D F6, 34 (R2) F6
Load-store
Operations F8
Store
Buffers Address Unit Floating Point F10
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
Reservation
Stations
FP Adders FP Multipliers
Common Data Bus (CDB)

Load: 2 Cycles Qi FP Registers
DIV.D F10, F0, F6
Add: 2 Cycles Instruction F0
SUB.D F8, F6, F2
Queue F2
Mul: 10 Cycles MUL.D F0, F2, F4
L.D F2, 45 (R3) F4
Div: 40 Cycles L.D F6, 34 (R2)
Load-store F6
Operations F8
Store
Load
Operations Operand
Buffers
Busy Busy Buses
Data Address
Memory Unit
Busy Op Vj Vk Qj Qk Busy Op Vj Vk Qj Qk
Reservation
Stations

FP Registers
1 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
F0
R2=100 MUL.D F0, F2, F4 F2
L.D F2, 45 (R3) 2.5 F4
R3=200 Load-store IS L.D F6, 34 (R2) LD1 F6
Operations F8
Store
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
Reservation
Stations

FP Registers
1 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
F0
R2=100 MUL.D F0, F2, F4 F2
L.D F2, 45 (R3) 2.5 F4
R3=200 Load-store IS L.D F6, 34 (R2) LD1 F6
Operations F8
Store
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
Reservation
Stations

FP Registers
2 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
F0
MUL.D F0, F2, F4 LD2 F2
R2=100
IS L.D F2, 45 (R3) 2.5 F4
R3=200 Load-store E L.D F6, 34 (R2) LD1 F6
Operations F8
Store
Load
Operations Operand
Buffers
134 2 Buses
Data Address
Memory Unit
Reservation
Stations

FP Registers
2 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
F0
R2=100
IS L.D F2, 45 (R3) 2.5 F4
Operations F8
Store
Load
Operations Operand
Buffers
134 2 Buses
Data Address
Memory Unit
Reservation
Stations

FP Registers
2 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
F0
R2=100
IS L.D F2, 45 (R3) 2.5 F4
Operations F8
Store
Load
Operations Operand
Buffers
134 2 Buses
Data Address
Memory Unit
Reservation
Stations

FP Registers
3 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
ML1 F0
IS MUL.D F0, F2, F4 LD2 F2
R2=100
E L.D F2, 45 (R3) 2.5 F4
Operations F8
Store
Load
Operations Operand
Buffers
134 1 Buses
245 2
Data Address
Memory Unit
1 ML 2.5 LD2
Reservation
Stations

FP Registers
4 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
ML1 F0
R2=100
E L.D F2, 45 (R3) 2.5 F4
Operations F8
Store
Load
Operations Operand
Buffers
134 0 Buses
245 1
Data Address
Memory Unit
LD1, 0.5 Busy Op Vj Vk Qj Qk Busy Op Vj Vk Qj Qk
1 ML 2.5 LD2
Reservation
Stations

FP Registers
4 DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
ML1 F0
R2=100
E L.D F2, 45 (R3) 2.5 F4
R3=200 Load-store W L.D F6, 34 (R2) LD1 0.5 F6
Operations F8
Store
Load
Operations Operand
Buffers
Buses
245 1
Data Address
Memory Unit
1 ML 2.5 LD2
Reservation
Stations

FP Registers
4 IS
DIV.D
SUB.D
F10, F0,
F8, F6,
F6
F2
Qi
ML1 F0
R2=100
E L.D F2, 45 (R3) 2.5 F4
R3=200 Load-store W L.D F6, 34 (R2) 0.5 F6
Operations AD1 F8
Store
Load
Operations Operand
Buffers
Buses
245 1
Data Address
Memory Unit
1 Sub 0.5 LD2 1 ML 2.5 LD2
Reservation
Stations

FP Registers
5 IS
DIV.D
SUB.D
F10, F0, F6
F8, F6, F2
Qi
ML1 F0
R2=100
E L.D F2, 45 (R3) 2.5 F4
R3=200 Load-store 0.5 F6
Operations AD1 F8
Store
Load
Operations Operand
Buffers
Buses
245 0
Data Address
Memory Unit
1 Sub 0.5 LD2 1 ML 2.5 LD2
Reservation
Stations

CKV
FP Registers
5 ADD.D
DIV.D
F6, F8,
F10, F0,
F2
F6
Qi
ML1 F0
IS SUB.D F8, F6, F2 LD2 F2
R2=100 IS MUL.D F0, F2, F4 2.5 F4
Operations AD1 F8
Store
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Sub 0.5 LD2 1 ML 2.5 LD2
Reservation
Stations

CKV
FP Registers
5 ADD.D
DIV.D
F6, F8,
F10, F0,
F2
F6
Qi
ML1 F0
IS SUB.D F8, F6, F2 LD2 1.5 F2
R2=100 IS MUL.D F0, F2, F4 2.5 F4
Operations AD1 F8
Store
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Sub 0.5 1.5 1 ML 1.5 2.5
Reservation
Stations

CKV
FP Registers
5 IS
ADD.D
DIV.D
F6, F8,
F10, F0,
F2
F6
Qi
ML1 F0
R2=100 IS SUB.D F8, F6, F2 1.5 F2
IS MUL.D F0, F2, F4 2.5 F4
R3=200 Load-store L.D F2, 45 (R3) 0.5 F6
Operations AD1 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Sub 0.5 1.5 1 ML 1.5 2.5
1 Div 0.5 ML1
Reservation
Stations

CKV
FP Registers
6 IS ADD.D F6, F8, F2
Qi
ML1 F0
R2=100
IS DIV.D F10, F0, F6 1.5 F2
E
IS SUB.D F8, F6, F2 2.5 F4
R3=200 Load-store
E
IS MUL.D F0, F2, F4 AD2 0.5 F6
Operations AD1 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
2 1 Sub 0.5 1.5 1 ML 1.5 2.5 10
1 Add 1.5 AD1 1 Div 0.5 ML1
Reservation
Stations

CKV
FP Registers
Qi
ML1 F0
R2=100
IS DIV.D F10, F0, F6 1.5 F2
E
IS SUB.D F8, F6, F2 2.5 F4
R3=200 Load-store
E
Operations AD1 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 1 Sub 0.5 1.5 1 ML 1.5 2.5 9
1 Add 1.5 AD1 1 Div 0.5 ML1
Reservation
Stations

CKV
FP Registers
Qi
ML1 F0
R2=100
IS DIV.D F10, F0, F6 1.5 F2
W
E
IS SUB.D F8, F6, F2 2.5 F4
R3=200 Load-store
E
Operations AD1 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
0 1 Sub 0.5 1.5 1 ML 1.5 2.5 8
1 Add 1.5 AD1 1 Div 0.5 ML1
Reservation
Stations
AD1, -1.0
CKV
FP Registers
Qi
ML1 F0
R2=100
IS DIV.D F10, F0, F6 1.5 F2
W
E
IS SUB.D F8, F6, F2 2.5 F4
R3=200 Load-store
E
Operations AD1 -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Sub 0.5 1.5 1 ML 1.5 2.5 8
1 Add -1.0 1.5 AD1 1 Div 0.5 ML1
Reservation
Stations
AD1, -1.0
CKV
FP Registers
9 Qi
ML1 F0
E
IS ADD.D F6, F8, F2
R2=100 1.5 F2
IS DIV.D F10, F0, F6
2.5 F4
R3=200 Load-store
E
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5 7
2 1 Add -1.0 1.5 1 Div 0.5 ML1
Reservation
Stations

CKV
FP Registers
10 Qi
ML1 F0
E
IS ADD.D F6, F8, F2
R2=100 1.5 F2
2.5 F4
R3=200 Load-store
E
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5 6
1 1 Add -1.0 1.5 1 Div 0.5 ML1
Reservation
Stations

CKV
FP Registers
11 Qi
ML1 F0
E
IS ADD.D F6, F8, F2
R2=100 1.5 F2
2.5 F4
R3=200 Load-store
E
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5 5
0 1 Add -1.0 1.5 1 Div 0.5 ML1
Reservation
Stations
AD2, 0.5 Common Data Bus (CDB)
CKV
FP Registers
11 Qi
ML1 F0
W
IS ADD.D F6, F8, F2
R2=100 1.5 F2
2.5 F4
R3=200 Load-store
E
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5 5
1 Add -1.0 1.5 1 Div 0.5 ML1
Reservation
Stations
AD2, 0.5 Common Data Bus (CDB)
CKV
14
13
15
12 Qi
ML1
FP Registers
F0
R2=100 1.5 F2
2.5 F4
R3=200 Load-store
E
IS MUL.D F0, F2, F4 0.5 F6
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5 123
4
1 Div 0.5 ML1
Reservation
Stations

CKV
FP Registers
16 Qi
ML1 F0
R2=100 1.5 F2
2.5 F4
R3=200 Load-store
W
E
IS MUL.D F0, F2, F4 0.5 F6
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5 0
1 Div 0.5 ML1
Reservation
Stations
ML1, 3.75
CKV
FP Registers
16 Qi
ML1 3.75 F0
R2=100 1.5 F2
2.5 F4
R3=200 Load-store
W
E
IS MUL.D F0, F2, F4 0.5 F6
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 ML 1.5 2.5
1 Div 3.75 0.5 ML1
Reservation
Stations
ML1, 3.75
CKV
FP Registers
17 Qi
3.75 F0
R2=100 1.5 F2
2.5 F4
R3=200 E
Load-store 0.5 F6
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Div 3.75 0.5 40

Reservation
Stations

CKV
FP Registers
18 Qi
3.75 F0
R2=100 1.5 F2
2.5 F4
R3=200 E
Load-store 0.5 F6
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Div 3.75 0.5 39

Reservation
Stations

CKV
FP Registers
57 Qi
3.75 F0
R2=100 1.5 F2
2.5 F4
R3=200 E
Load-store 0.5 F6
Operations -1.0 F8
Store ML2
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Div 3.75 0.5 0

Reservation
Stations
ML2, 7.5
CKV
FP Registers
57 Qi
3.75 F0
R2=100 1.5 F2
2.5 F4
R3=200 WE
Load-store 0.5 F6
Operations -1.0 F8
Store ML2 7.5 F10
Buffers Address Unit Floating Point
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
1 Div 3.75 0.5

Reservation
Stations
ML2, 7.5
CKV
Qi FP Registers
3.75 F0
1.5 F2
2.5 F4
Load-store 0.5 F6
Operations -1.0 F8
Store 7.5 F10
Buffers Address Unit Floating Point
Load
Operations Operand
Buffers
Buses
Data Address
Memory Unit
Reservation
Stations

CKV
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Lecture 18

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CKV

Advanced VLSI Architecture

Lecture 18: Instruction Level Parallelism

Register Renaming by reservation stations

Reservation station fetches and buffers an operand as soon as it is

If there is a matching reservation station that is empty, issue the

If there is not an empty reservation station, then there is a structural

If one or more of the operands is not yet available, monitor the

When an operand becomes available, it is placed into any reservation

To preserve exception behavior, no instruction is allowed to initiate

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

Common Data Bus (CDB)

1 Div 3.75 0.5 40

Common Data Bus (CDB)

1 Div 3.75 0.5 39

Common Data Bus (CDB)

1 Div 3.75 0.5 0

1 Div 3.75 0.5

Common Data Bus (CDB)

Thank You for Attending

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