CKV

Advanced VLSI Architecture

MEL G624

Lecture 17: Instruction Level Parallelism

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Dynamic Branch Prediction

Correlating Branch Predictors

Use the behaviour of other branches to make a prediction, also

called as two-level predictors.

An predictor uses the behaviour of the last branches to choose

from branch predictors, each of which is an -bit predictor for a
single branch.

Better Prediction rates than 2-bit predictor

Trivial amount of additional hardware.

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(2,2) Predictor with 16 entries

0……000: b1 10 1 01
00
00
2 bit 00
00
00
0……110: b2 2 bit
00
00
00
00
00
0…….101: b3 00
00
00
00
00
0…….100: b4
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Dynamic Branch Prediction
How many bits are in the (0,2) branch predictor with 4K entries?
How many entries are in a (2,2) predictor with the same number of
bits?
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Dynamic Branch Prediction

Correlating predictor
outperforms a simple
2-bit predictor
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Dynamic Branch Prediction

Tournament Predictors:

Correlating branch predictors combine global and local information

Tournament predictors take this insight to the next level

Uses multiple predictors,

Global Predictor
Selector
Local Predictor

Selectors selects one among two predictors using 2-bit prediction

scheme
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Dynamic Branch Prediction

Tournament Predictors:

Selector Predictor_1/Predictor_2
0/0, 1/1
0/0, 1/1, 0/1
1/0
Use Predictor 2 11 10 Use Predictor 2
0/1
0/1 1/0
1/0
Use Predictor 1 01 00 Use Predictor 1
0/1

0/0, 1/1 0/0, 1/1, 1/0

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Tournament Predictor 4K entries, 2-bit State
Alpha 21264, 12-bit global History

4K entries, 2-bit State

Global

0……000: b1
1K entries, 1K entries,
10-bit Local History 3-bit State

Local
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Dynamic Branch Prediction
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Dynamic Branch Prediction
Intel core i7 Branch Predictor
Smaller first level predictor to meet cycle constraints

Larger second level predictor

Each predictor combines three different predictors

A simple 2-bit predictor

A global history predictor

A loop exit predictor

Best predictor chosen by tracking the accuracy of each prediction

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Dynamic Scheduling
Scoreboarding issues

WAW Hazards, WAR Hazards

DIV.D F0,F2,F4
ADD.D F6,F0,F8
S.D F6,0(R1)
SUB.D F8,F4,F2
MUL.D F6,F4,F8

Antidependence between the ADD.D and the SUB.D

Output dependence between the ADD.D and the MUL.D,

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Dynamic Scheduling

DIV.D F0,F2,F4 DIV.D F0,F2,F4

ADD.D F6,F0,F8 ADD.D S,F0,F8
S.D F6,0(R1) S.D S,0(R1)
SUB.D F8,F4,F2 SUB.D T,F4,F2
MUL.D F6,F4,F8 MUL.D F6,F4,T

Register Renaming
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Dynamic Scheduling

Register
Architectural Physical
Allocation
Register File Register File
Table

Physical
Register File
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Dynamic Scheduling
ARF RAT PRF

F0 F0  P0 P0 = A
F2 F2  P2 P2 = B
Register
Architectural
F4
Register File F4  P4
Allocation P4 = C
Table
F6 F6  P6 P6 = D
F8 F8  P8 P8 = E
Physical
Register
P10 =File
P12 =
P14 =
Free Register
pool
P16 =
P18 =
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Dynamic Scheduling
ARF RAT PRF

F0 = A F0
F0 P10
P0 P0 = A
F2 = B Archite
F2  P2
Register
P2 = B
Architectural
F4 = C ctural
Allocation
Register File F4  P4 P4 = C
F6 = D
Register
Table
F6  P6 P6 = D
File
F8 = E F8  P8 P8 = E
Physical
Register=File
P10=B/C
P10
P12 =
DIV.D F0,F2,F4 DIV.D P10,F2,F4
ADD.D F6,F0,F8 ADD.D F6,F0,F8 P14 =
S.D F6,0(R1) S.D F6,0(R1) P16 =
SUB.D F8,F4,F2 SUB.D F8,F4,F2
MUL.D F6,F4,F8 MUL.D F6,F4,F8 P18 =
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Dynamic Scheduling
ARF RAT PRF

F0 F0
F0 P10
P0 P0 = A
F2 Archite
F2  P2
Register
P2 = B
Architectural
F4 ctural
Allocation
Register File F4  P4 P4 = C
F6
Register
Table
F6
F6 P12P6 P6 = D
File
F8 F8  P8 P8 = E
Physical
P10
P10=B/C
Register=File
P12 =(B/C+E)
P12 =
DIV.D F0,F2,F4 DIV.D P10,F2,F4
ADD.D F6,F0,F8 ADD.D P12,F0,F8 P14 =
S.D F6,0(R1) S.D F6,0(R1) P16 =
SUB.D F8,F4,F2 SUB.D F8,F4,F2
MUL.D F6,F4,F8 MUL.D F6,F4,F8 P18 =
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Dynamic Scheduling
ARF RAT PRF

F0 F0
F0 P10
P0 P0 = A
F2 Archite
F2  P2
Register
P2 = B
Architectural
F4 ctural
Allocation
Register File F4  P4 P4 = C
F6
Register
Table
F6
F6 P12P6 P6 = D
File
F8 F8  P8 P8 = E
Physical
P10
P10=B/C
Register=File
P12 =(B/C+E)
P12 =
DIV.D F0,F2,F4 DIV.D P10,F2,F4
ADD.D F6,F0,F8 ADD.D P12,F0,F8 P14 =
S.D F6,0(R1) S.D P12,0(R1) P16 =
SUB.D F8,F4,F2 SUB.D F8,F4,F2
MUL.D F6,F4,F8 MUL.D F6,F4,F8 P18 =
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Dynamic Scheduling
ARF RAT PRF

F0 F0
F0 P10
P0 P0 = A
F2 Archite
F2  P2
Register
P2 = B
Architectural
F4 ctural
Allocation
Register File F4  P4 P4 = C
F6
Register
Table
F6
F6 P12P6 P6 = D
File
F8 P14
F8
F8 P8 P8 = E
Physical
P10
P10=B/C
Register=File
P12 =(B/C+E)
P12 =
DIV.D F0,F2,F4 DIV.D P10,F2,F4
ADD.D F6,F0,F8 ADD.D P12,F0,F8 P14
P14 =
=(C-B)
S.D F6,0(R1) S.D P12,0(R1) P16 =
SUB.D F8,F4,F2 SUB.D P14,F4,F2
MUL.D F6,F4,F8 MUL.D F6,F4,F8 P18 =
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Dynamic Scheduling
ARF RAT PRF

F0 F0
F0 P10
P0 P0==B/C
P0 A
F2 Archite
F2  P2
Register
P2 = B
Architectural
F4 ctural
Register File F4  P4
Allocation P4 = C
F6
Register
Table
F6
F6 P16
P12P6 P6P6= =C*(C-B)
D
File
F8 P14
F8
F8 P8 P8==(C-B)
P8 E
Physical
Physical
P10
P10=B/C
Register=File
P12 =(B/C+E)
P12 =
DIV.D F0,F2,F4 DIV.D P10,F2,F4
ADD.D F6,F0,F8 ADD.D P12,F0,F8 P14
P14=(C-B)
=
S.D F6,0(R1) S.D P12,0(R1) P16
P16 =
=C*(C-B)
SUB.D F8,F4,F2 SUB.D P14,F4,F2
MUL.D F6,F4,F8 MUL.D P16,F4,P14 P18 =
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